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Mon, 28 Jul 2025 22:43:05 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGuKC49VBkZiHECTi9KBlMSNGzNAEaEP1WPkKqf/bdqrLtemg0XBkfBmt7Og8liW4pqUPQvvw== X-Received: by 2002:a17:903:2f0d:b0:23c:863d:2989 with SMTP id d9443c01a7336-23fb3065e41mr207262815ad.3.1753767785306; Mon, 28 Jul 2025 22:43:05 -0700 (PDT) Received: from hu-tdas-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-23fe9b67485sm54505235ad.47.2025.07.28.22.43.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Jul 2025 22:43:04 -0700 (PDT) From: Taniya Das Date: Tue, 29 Jul 2025 11:12:39 +0530 Subject: [PATCH v3 5/7] clk: qcom: clk-alpha-pll: Add support for Taycan EKO_T PLL Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250729-glymur-gcc-tcsrcc-rpmhcc-v3-5-227cfe5c8ef4@oss.qualcomm.com> References: <20250729-glymur-gcc-tcsrcc-rpmhcc-v3-0-227cfe5c8ef4@oss.qualcomm.com> In-Reply-To: <20250729-glymur-gcc-tcsrcc-rpmhcc-v3-0-227cfe5c8ef4@oss.qualcomm.com> To: kernel@oss.qualcomm.com, Pankaj Patil , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Taniya Das , Dmitry Baryshkov X-Mailer: b4 0.15-dev-aa3f6 X-Authority-Analysis: v=2.4 cv=JovxrN4C c=1 sm=1 tr=0 ts=68885f6b cx=c_pps a=MTSHoo12Qbhz2p7MsH1ifg==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=Wb1JkmetP80A:10 a=EUspDBNiAAAA:8 a=9yNAuCQw4ehsCnPPvT8A:9 a=QEXdDO2ut3YA:10 a=GvdueXVYPmCkWapjIL-Q:22 X-Proofpoint-ORIG-GUID: VXtGcKIHd83a-xzZ3lvxRVcKkJhDKDgJ X-Proofpoint-GUID: VXtGcKIHd83a-xzZ3lvxRVcKkJhDKDgJ X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzI5MDA0MSBTYWx0ZWRfX1Q7IQuC1JnEG VYJYtMculi+KLG6j66RmejXtRoO2k3BJNe3HY9duemJ0kGeh7PVPZdoJ7S1wyxQbJpxD+0Qii2g LN62yV6PlN85uXpIepNyFdsSlYWdxc8JQkyqsEGdsjxrAm5vrC0+r6E5v4E9qpMxE26vNcY+IBU Ey+L9DXyPOJtElIb6SO0lXO6X71e0blKx3legBs/ZMG7FJtppjRKDK5uzH1Yf/e1RNGJYA6CFz4 fEuSr8DQJKwCS/4jNZ4xsFAmK5mrUDndUgIQQJvTGpLmbc50gmQh3RVG18s9DISO6HfqogeGm9E nuplOZ+qeOrc1OFBOzor0EdS8a1CE2GMjjg587WwHsjNrF633JV8boLCyBL3FuQrHOp9jiUTFIR sjnSN8tDaRfjBxASXVqLcEpFGWoId+kZWmUjDTcwL73wOzNypUaoap+I7rR4FC65Vm4FnlBk X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-29_01,2025-07-28_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 clxscore=1015 priorityscore=1501 bulkscore=0 impostorscore=0 lowpriorityscore=0 phishscore=0 suspectscore=0 spamscore=0 mlxlogscore=999 mlxscore=0 adultscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507290041 Add clock operations and register offsets to enable control of the Taycan EKO_T PLL, allowing for proper configuration and management of the PLL. Reviewed-by: Dmitry Baryshkov Signed-off-by: Taniya Das --- drivers/clk/qcom/clk-alpha-pll.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-= pll.h index 7f35aaa7a35d88411beb11fd2be5d5dd5bfbe066..2294ae99cff3253ac54d916ad0b= d1d7e4146f2a8 100644 --- a/drivers/clk/qcom/clk-alpha-pll.h +++ b/drivers/clk/qcom/clk-alpha-pll.h @@ -29,6 +29,7 @@ enum { CLK_ALPHA_PLL_TYPE_LUCID_OLE, CLK_ALPHA_PLL_TYPE_PONGO_ELU, CLK_ALPHA_PLL_TYPE_TAYCAN_ELU, + CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T =3D CLK_ALPHA_PLL_TYPE_TAYCAN_ELU, CLK_ALPHA_PLL_TYPE_RIVIAN_EVO, CLK_ALPHA_PLL_TYPE_DEFAULT_EVO, CLK_ALPHA_PLL_TYPE_BRAMMO_EVO, @@ -192,14 +193,17 @@ extern const struct clk_ops clk_alpha_pll_zonda_ops; =20 extern const struct clk_ops clk_alpha_pll_lucid_evo_ops; #define clk_alpha_pll_taycan_elu_ops clk_alpha_pll_lucid_evo_ops +#define clk_alpha_pll_taycan_eko_t_ops clk_alpha_pll_lucid_evo_ops extern const struct clk_ops clk_alpha_pll_reset_lucid_evo_ops; #define clk_alpha_pll_reset_lucid_ole_ops clk_alpha_pll_reset_lucid_evo_ops extern const struct clk_ops clk_alpha_pll_fixed_lucid_evo_ops; #define clk_alpha_pll_fixed_lucid_ole_ops clk_alpha_pll_fixed_lucid_evo_ops #define clk_alpha_pll_fixed_taycan_elu_ops clk_alpha_pll_fixed_lucid_evo_o= ps +#define clk_alpha_pll_fixed_taycan_eko_t_ops clk_alpha_pll_fixed_lucid_evo= _ops extern const struct clk_ops clk_alpha_pll_postdiv_lucid_evo_ops; #define clk_alpha_pll_postdiv_lucid_ole_ops clk_alpha_pll_postdiv_lucid_ev= o_ops #define clk_alpha_pll_postdiv_taycan_elu_ops clk_alpha_pll_postdiv_lucid_e= vo_ops +#define clk_alpha_pll_postdiv_taycan_eko_t_ops clk_alpha_pll_postdiv_lucid= _evo_ops =20 extern const struct clk_ops clk_alpha_pll_pongo_elu_ops; extern const struct clk_ops clk_alpha_pll_rivian_evo_ops; @@ -232,6 +236,8 @@ void clk_pongo_elu_pll_configure(struct clk_alpha_pll *= pll, struct regmap *regma const struct alpha_pll_config *config); #define clk_taycan_elu_pll_configure(pll, regmap, config) \ clk_lucid_evo_pll_configure(pll, regmap, config) +#define clk_taycan_eko_t_pll_configure(pll, regmap, config) \ + clk_lucid_evo_pll_configure(pll, regmap, config) =20 void clk_rivian_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap= *regmap, const struct alpha_pll_config *config); --=20 2.34.1