From nobody Sun Oct 5 21:59:22 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BA5351DD0D4; Tue, 29 Jul 2025 04:51:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753764687; cv=none; b=iYYfVg2tFDbgu8RnABZqNWzpyMANoJ8yBdJu1j1aWZoPC4DnJMOlQv86z2byuyqlPILww3y3uw/gm3AUn0HoCgEDmz9teMwj9PQ2FOQjnLtIeqkhhPn3BIDs1pIZlq42vFpMhtqhgqAFhtGa5Qch+7L/3mwKknFJyjAsFUnzi0M= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753764687; c=relaxed/simple; bh=OQFXnvEMtBWVGYDn5R7enBvPUJwl4shicmIllfMRgn8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=EVwf94AOIr2LlaBqOg1zelvxH67V2C/vcKSlWlbN6G3K7BN4ZGbUyGMEJTjwnP2Wv5K+AxE1f7GyMpnNzuV/6vm8uBvh1njU0cIgeeHf50fG8xIWB4LBb2NYfiuJMwuS8aKdLX9OL1X1h/cTdl+n4ZBHhbN4WabFBx54RZmc944= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=FM8vyNwC; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="FM8vyNwC" Received: by smtp.kernel.org (Postfix) with ESMTPS id 64D6DC4CEF4; Tue, 29 Jul 2025 04:51:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1753764687; bh=OQFXnvEMtBWVGYDn5R7enBvPUJwl4shicmIllfMRgn8=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=FM8vyNwCT7Aide+GGwpEgUsm14DSuA2A0/IC0HgQ/TRHLXWZO2vq+jxVkgps9QHkh puJxEmoq4uWZmCaHAuVuVujQ9B8hWGn9aDW+7VXu7rz2nBkLDHWs0OEq/fbw736ddN ttiRIkX1oYUwNR2AFh7v2mR0wXj5XpYztCco+PdnqGdIwtGmGjDQPwmsrZm6SCkCta yR/aOYf8nSp49OPZYKv4uPFT1Zl+zIBPpTGM+B/TxUDk9YT5MZA9lnvx60X7mErXlX O9pSzJ6SGOs3E8APHmmY9IL4MeS8wHWRwoIB5rXpHJ18NX6loDCYztYhzfweyolyaS 3XvovhBrDSZgQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4CF74C83F26; Tue, 29 Jul 2025 04:51:27 +0000 (UTC) From: Fenglin Wu via B4 Relay Date: Tue, 29 Jul 2025 12:51:22 +0800 Subject: [PATCH v2 1/2] leds: flash: leds-qcom-flash: update torch current clamp setting Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250729-fix-torch-clamp-issue-v2-1-9b83816437a3@oss.qualcomm.com> References: <20250729-fix-torch-clamp-issue-v2-0-9b83816437a3@oss.qualcomm.com> In-Reply-To: <20250729-fix-torch-clamp-issue-v2-0-9b83816437a3@oss.qualcomm.com> To: kernel@oss.qualcomm.com, Lee Jones , Pavel Machek , Konrad Dybcio Cc: Subbaraman Narayanamurthy , linux-leds@vger.kernel.org, linux-kernel@vger.kernel.org, Fenglin Wu X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1753764686; l=5090; i=fenglin.wu@oss.qualcomm.com; s=20240327; h=from:subject:message-id; bh=snJpp7kKLVN9645UzePQuhIOL/EObRQyAzwlXq/N50o=; b=Ny18tnn6Yg9NSuvFQ+Lh42MNhqG44TFPz5X6LxFn6CNTQe8koFscHzs9LSMaJKuDhQoji1MsR odjvS0lyZ7QDUOIrSlGeSx5r8HGv9A6OAcF5egvQIIGp6+IlqHlRrXb X-Developer-Key: i=fenglin.wu@oss.qualcomm.com; a=ed25519; pk=BF8SA4IVDk8/EBCwlBehKtn2hp6kipuuAuDAHh9s+K4= X-Endpoint-Received: by B4 Relay for fenglin.wu@oss.qualcomm.com/20240327 with auth_id=406 X-Original-From: Fenglin Wu Reply-To: fenglin.wu@oss.qualcomm.com From: Fenglin Wu There is a register to clamp the flash current per LED channel when safety timer is disabled. It needs to be updated according to the maximum torch LED current setting to ensure the torch current won't be clamped unexpectedly. Fixes: 96a2e242a5dc ("leds: flash: Add driver to support flash LED module i= n QCOM PMICs") Signed-off-by: Fenglin Wu Reviewed-by: Konrad Dybcio --- drivers/leds/flash/leds-qcom-flash.c | 62 +++++++++++++++++++++-----------= ---- 1 file changed, 36 insertions(+), 26 deletions(-) diff --git a/drivers/leds/flash/leds-qcom-flash.c b/drivers/leds/flash/leds= -qcom-flash.c index 89cf5120f5d55bbb7e24faa8c3a946416f8fed46..db7c2c743adc755244f387febce= 663738bf3c0bd 100644 --- a/drivers/leds/flash/leds-qcom-flash.c +++ b/drivers/leds/flash/leds-qcom-flash.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2022, 2024 Qualcomm Innovation Center, Inc. All rights re= served. + * Copyright (c) 2022, 2024-2025 Qualcomm Innovation Center, Inc. All righ= ts reserved. */ =20 #include @@ -114,36 +114,39 @@ enum { REG_THERM_THRSH1, REG_THERM_THRSH2, REG_THERM_THRSH3, + REG_TORCH_CLAMP, REG_MAX_COUNT, }; =20 static const struct reg_field mvflash_3ch_regs[REG_MAX_COUNT] =3D { - REG_FIELD(0x08, 0, 7), /* status1 */ - REG_FIELD(0x09, 0, 7), /* status2 */ - REG_FIELD(0x0a, 0, 7), /* status3 */ - REG_FIELD_ID(0x40, 0, 7, 3, 1), /* chan_timer */ - REG_FIELD_ID(0x43, 0, 6, 3, 1), /* itarget */ - REG_FIELD(0x46, 7, 7), /* module_en */ - REG_FIELD(0x47, 0, 5), /* iresolution */ - REG_FIELD_ID(0x49, 0, 2, 3, 1), /* chan_strobe */ - REG_FIELD(0x4c, 0, 2), /* chan_en */ - REG_FIELD(0x56, 0, 2), /* therm_thrsh1 */ - REG_FIELD(0x57, 0, 2), /* therm_thrsh2 */ - REG_FIELD(0x58, 0, 2), /* therm_thrsh3 */ + [REG_STATUS1] =3D REG_FIELD(0x08, 0, 7), + [REG_STATUS2] =3D REG_FIELD(0x09, 0, 7), + [REG_STATUS3] =3D REG_FIELD(0x0a, 0, 7), + [REG_CHAN_TIMER] =3D REG_FIELD_ID(0x40, 0, 7, 3, 1), + [REG_ITARGET] =3D REG_FIELD_ID(0x43, 0, 6, 3, 1), + [REG_MODULE_EN] =3D REG_FIELD(0x46, 7, 7), + [REG_IRESOLUTION] =3D REG_FIELD(0x47, 0, 5), + [REG_CHAN_STROBE] =3D REG_FIELD_ID(0x49, 0, 2, 3, 1), + [REG_CHAN_EN] =3D REG_FIELD(0x4c, 0, 2), + [REG_THERM_THRSH1] =3D REG_FIELD(0x56, 0, 2), + [REG_THERM_THRSH2] =3D REG_FIELD(0x57, 0, 2), + [REG_THERM_THRSH3] =3D REG_FIELD(0x58, 0, 2), + [REG_TORCH_CLAMP] =3D REG_FIELD(0xec, 0, 6), }; =20 static const struct reg_field mvflash_4ch_regs[REG_MAX_COUNT] =3D { - REG_FIELD(0x06, 0, 7), /* status1 */ - REG_FIELD(0x07, 0, 6), /* status2 */ - REG_FIELD(0x09, 0, 7), /* status3 */ - REG_FIELD_ID(0x3e, 0, 7, 4, 1), /* chan_timer */ - REG_FIELD_ID(0x42, 0, 6, 4, 1), /* itarget */ - REG_FIELD(0x46, 7, 7), /* module_en */ - REG_FIELD(0x49, 0, 3), /* iresolution */ - REG_FIELD_ID(0x4a, 0, 6, 4, 1), /* chan_strobe */ - REG_FIELD(0x4e, 0, 3), /* chan_en */ - REG_FIELD(0x7a, 0, 2), /* therm_thrsh1 */ - REG_FIELD(0x78, 0, 2), /* therm_thrsh2 */ + [REG_STATUS1] =3D REG_FIELD(0x06, 0, 7), + [REG_STATUS2] =3D REG_FIELD(0x07, 0, 6), + [REG_STATUS3] =3D REG_FIELD(0x09, 0, 7), + [REG_CHAN_TIMER] =3D REG_FIELD_ID(0x3e, 0, 7, 4, 1), + [REG_ITARGET] =3D REG_FIELD_ID(0x42, 0, 6, 4, 1), + [REG_MODULE_EN] =3D REG_FIELD(0x46, 7, 7), + [REG_IRESOLUTION] =3D REG_FIELD(0x49, 0, 3), + [REG_CHAN_STROBE] =3D REG_FIELD_ID(0x4a, 0, 6, 4, 1), + [REG_CHAN_EN] =3D REG_FIELD(0x4e, 0, 3), + [REG_THERM_THRSH1] =3D REG_FIELD(0x7a, 0, 2), + [REG_THERM_THRSH2] =3D REG_FIELD(0x78, 0, 2), + [REG_TORCH_CLAMP] =3D REG_FIELD(0xed, 0, 6), }; =20 struct qcom_flash_data { @@ -156,6 +159,7 @@ struct qcom_flash_data { u8 max_channels; u8 chan_en_bits; u8 revision; + u8 torch_clamp; }; =20 struct qcom_flash_led { @@ -702,6 +706,7 @@ static int qcom_flash_register_led_device(struct device= *dev, u32 current_ua, timeout_us; u32 channels[4]; int i, rc, count; + u8 torch_clamp; =20 count =3D fwnode_property_count_u32(node, "led-sources"); if (count <=3D 0) { @@ -751,6 +756,12 @@ static int qcom_flash_register_led_device(struct devic= e *dev, current_ua =3D min_t(u32, current_ua, TORCH_CURRENT_MAX_UA * led->chan_co= unt); led->max_torch_current_ma =3D current_ua / UA_PER_MA; =20 + torch_clamp =3D (current_ua / led->chan_count) / TORCH_IRES_UA; + if (torch_clamp !=3D 0) + torch_clamp--; + + flash_data->torch_clamp =3D max_t(u8, flash_data->torch_clamp, torch_clam= p); + if (fwnode_property_present(node, "flash-max-microamp")) { flash->led_cdev.flags |=3D LED_DEV_CAP_FLASH; =20 @@ -917,8 +928,7 @@ static int qcom_flash_led_probe(struct platform_device = *pdev) flash_data->leds_count++; } =20 - return 0; - + return regmap_field_write(flash_data->r_fields[REG_TORCH_CLAMP], flash_da= ta->torch_clamp); release: while (flash_data->v4l2_flash[flash_data->leds_count] && flash_data->leds= _count) v4l2_flash_release(flash_data->v4l2_flash[flash_data->leds_count--]); --=20 2.34.1 From nobody Sun Oct 5 21:59:22 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9AD5A4A01; Tue, 29 Jul 2025 04:51:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753764687; cv=none; b=L3v1Gbi1jRd+P58+gNsp7TQVanjTUSiAw7UT4UbgPiSIksoMkGts+pOB9/n9HJvNDV2ALmWPqRrE6gg20NT5Dljcs38FA6kkHqQTHqw5O8jmpXAsnUtfHgIYkMmiUh57TBVb1+ZSBQFLeFum+5qWk6vwPe7+Rb6JfEpvGf7GM2o= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753764687; c=relaxed/simple; bh=cjeqSra3b1A1vbJsnaMuLQ3Inhk8Ki1dNA21mebRY+0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=mY5OLzHdCmZpV+490sqIlWNtWMkGlLBlUXgAArhyxyMW76MYZWWK08f5K4gDYJ0fd43MC1U5faGEGbC6CssZN+Uzqi9FEeNV33YGt+sn4pWVAV/B9v96WP/IL+6voN8yvUT+5/yVKdVnoPucrAQvXYpSp+YBKGVpFzjNk2cYSl4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=sL1OhUHt; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="sL1OhUHt" Received: by smtp.kernel.org (Postfix) with ESMTPS id 6AC1EC4CEF8; Tue, 29 Jul 2025 04:51:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1753764687; bh=cjeqSra3b1A1vbJsnaMuLQ3Inhk8Ki1dNA21mebRY+0=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=sL1OhUHtaAZEj/r+LETSqxQ3Y6n+/AT5PSJgctuTf3aPMRov3B27iGLECJkNHo8bx J7BdN8N4PQOwlPlwncOgn+GWXxZuxkh5ZyfSIJwaRE74OYDtF7u1pmiF/VfiKXBs+w YW2X2A1eu1lRzR0UgTNz5Vz6uu8pmKWVGQC79xMaxQzmS2hqK0DR0tNJXtNFQWAZFf BJnte+kRBXP88ZPRb3cAHpw7tAPWJCwJmsbymoXmrKJNDjr7cuwGJY2+FOBOtE+1hh UQT2Tenc2CUCdqitXwl5ICf5448G7GgOYhipFExnpiGVkL21mDs/KihSRzmqn5BOIf ZHE8ODPkp6XqA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 59C96C87FCA; Tue, 29 Jul 2025 04:51:27 +0000 (UTC) From: Fenglin Wu via B4 Relay Date: Tue, 29 Jul 2025 12:51:23 +0800 Subject: [PATCH v2 2/2] leds: flash: leds-qcom-flash: add a separate register map for PMI8998 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250729-fix-torch-clamp-issue-v2-2-9b83816437a3@oss.qualcomm.com> References: <20250729-fix-torch-clamp-issue-v2-0-9b83816437a3@oss.qualcomm.com> In-Reply-To: <20250729-fix-torch-clamp-issue-v2-0-9b83816437a3@oss.qualcomm.com> To: kernel@oss.qualcomm.com, Lee Jones , Pavel Machek , Konrad Dybcio Cc: Subbaraman Narayanamurthy , linux-leds@vger.kernel.org, linux-kernel@vger.kernel.org, Fenglin Wu X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1753764686; l=2384; i=fenglin.wu@oss.qualcomm.com; s=20240327; h=from:subject:message-id; bh=veBh7fJK3dHgrg1LPo1zZL/xU/qWzZ1meNlhvMaeZoo=; b=RdUWZ3ghKPMCnmxWq1BYbZyTm0Tt42RiAfPEZBXbyyd+BWxxM1zpVbV41Z5o6N9jxhFo7cIlR 5POYivvrf7HD8WauNaGHnXzcKyJ6NfJTI3cAZG57mR0ejlSrj6IUB15 X-Developer-Key: i=fenglin.wu@oss.qualcomm.com; a=ed25519; pk=BF8SA4IVDk8/EBCwlBehKtn2hp6kipuuAuDAHh9s+K4= X-Endpoint-Received: by B4 Relay for fenglin.wu@oss.qualcomm.com/20240327 with auth_id=406 X-Original-From: Fenglin Wu Reply-To: fenglin.wu@oss.qualcomm.com From: Fenglin Wu The 3-channel flash module in PMI8998 has several registers different than the others, such as: torch_clamp. Add different register fields for it. Signed-off-by: Fenglin Wu Reviewed-by: Konrad Dybcio --- drivers/leds/flash/leds-qcom-flash.c | 25 ++++++++++++++++++++++++- 1 file changed, 24 insertions(+), 1 deletion(-) diff --git a/drivers/leds/flash/leds-qcom-flash.c b/drivers/leds/flash/leds= -qcom-flash.c index db7c2c743adc755244f387febce663738bf3c0bd..b03a6833e3e3a076980bfcb46d5= bbde4f4183a19 100644 --- a/drivers/leds/flash/leds-qcom-flash.c +++ b/drivers/leds/flash/leds-qcom-flash.c @@ -118,6 +118,22 @@ enum { REG_MAX_COUNT, }; =20 +static const struct reg_field mvflash_3ch_pmi8998_regs[REG_MAX_COUNT] =3D { + [REG_STATUS1] =3D REG_FIELD(0x08, 0, 5), + [REG_STATUS2] =3D REG_FIELD(0x09, 0, 7), + [REG_STATUS3] =3D REG_FIELD(0x0a, 0, 7), + [REG_CHAN_TIMER] =3D REG_FIELD_ID(0x40, 0, 7, 3, 1), + [REG_ITARGET] =3D REG_FIELD_ID(0x43, 0, 6, 3, 1), + [REG_MODULE_EN] =3D REG_FIELD(0x46, 7, 7), + [REG_IRESOLUTION] =3D REG_FIELD(0x47, 0, 5), + [REG_CHAN_STROBE] =3D REG_FIELD_ID(0x49, 0, 2, 3, 1), + [REG_CHAN_EN] =3D REG_FIELD(0x4c, 0, 2), + [REG_THERM_THRSH1] =3D REG_FIELD(0x56, 0, 2), + [REG_THERM_THRSH2] =3D REG_FIELD(0x57, 0, 2), + [REG_THERM_THRSH3] =3D REG_FIELD(0x58, 0, 2), + [REG_TORCH_CLAMP] =3D REG_FIELD(0xea, 0, 6), +}; + static const struct reg_field mvflash_3ch_regs[REG_MAX_COUNT] =3D { [REG_STATUS1] =3D REG_FIELD(0x08, 0, 7), [REG_STATUS2] =3D REG_FIELD(0x09, 0, 7), @@ -862,13 +878,20 @@ static int qcom_flash_led_probe(struct platform_devic= e *pdev) return rc; } =20 - if (val =3D=3D FLASH_SUBTYPE_3CH_PM8150_VAL || val =3D=3D FLASH_SUBTYPE_3= CH_PMI8998_VAL) { + if (val =3D=3D FLASH_SUBTYPE_3CH_PM8150_VAL) { flash_data->hw_type =3D QCOM_MVFLASH_3CH; flash_data->max_channels =3D 3; regs =3D devm_kmemdup(dev, mvflash_3ch_regs, sizeof(mvflash_3ch_regs), GFP_KERNEL); if (!regs) return -ENOMEM; + } else if (val =3D=3D FLASH_SUBTYPE_3CH_PMI8998_VAL) { + flash_data->hw_type =3D QCOM_MVFLASH_3CH; + flash_data->max_channels =3D 3; + regs =3D devm_kmemdup(dev, mvflash_3ch_pmi8998_regs, + sizeof(mvflash_3ch_pmi8998_regs), GFP_KERNEL); + if (!regs) + return -ENOMEM; } else if (val =3D=3D FLASH_SUBTYPE_4CH_VAL) { flash_data->hw_type =3D QCOM_MVFLASH_4CH; flash_data->max_channels =3D 4; --=20 2.34.1