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Mon, 28 Jul 2025 12:45:05 -0700 (PDT) Received: from playground.localdomain ([82.79.237.20]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3b778f0c477sm9547837f8f.58.2025.07.28.12.45.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Jul 2025 12:45:04 -0700 (PDT) From: Laurentiu Mihalcea To: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , Shawn Guo , Sascha Hauer , Fabio Estevam Cc: Pengutronix Kernel Team , linux-pwm@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v3] pwm: imx-tpm: reset counter if CMOD is 0 Date: Mon, 28 Jul 2025 15:41:44 -0400 Message-Id: <20250728194144.22884-1-laurentiumihalcea111@gmail.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Laurentiu Mihalcea As per the i.MX93 TRM, section 67.3.2.1 "MOD register update", the value of the TPM counter does NOT get updated when writing MOD.MOD unless SC.CMOD !=3D 0. Therefore, with the current code, assuming the following sequence: 1) pwm_disable() 2) pwm_apply_might_sleep() /* period is changed here */ 3) pwm_enable() and assuming only one channel is active, if CNT.COUNT is higher than the MOD.MOD value written during the pwm_apply_might_sleep() call then, when re-enabling the PWM during pwm_enable(), the counter will end up resetting after UINT32_MAX - CNT.COUNT + MOD.MOD cycles instead of MOD.MOD cycles as normally expected. Fix this problem by forcing a reset of the TPM counter before MOD.MOD is written. Fixes: 738a1cfec2ed ("pwm: Add i.MX TPM PWM driver support") Cc: stable@vger.kernel.org Signed-off-by: Laurentiu Mihalcea --- Changes in v3: - added Fixes and Cc tags - rephrased the newly introduced comment such that the bit is understanda= ble w/o having to check the TRM. - Link to v2: https://lore.kernel.org/lkml/20250714123634.6442-1-laurenti= umihalcea111@gmail.com/ Changes in v2: - dropped the "VERY IMPORTANT" bit as per Uwe's suggestion. - Link to v1: https://lore.kernel.org/lkml/20250701220147.1007786-1-laure= ntiumihalcea111@gmail.com/ drivers/pwm/pwm-imx-tpm.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/pwm/pwm-imx-tpm.c b/drivers/pwm/pwm-imx-tpm.c index 7ee7b65b9b90..5b399de16d60 100644 --- a/drivers/pwm/pwm-imx-tpm.c +++ b/drivers/pwm/pwm-imx-tpm.c @@ -204,6 +204,15 @@ static int pwm_imx_tpm_apply_hw(struct pwm_chip *chip, val |=3D FIELD_PREP(PWM_IMX_TPM_SC_PS, p->prescale); writel(val, tpm->base + PWM_IMX_TPM_SC); =20 + /* + * if the counter is disabled (CMOD =3D=3D 0), programming the new + * period length (MOD) will not reset the counter (CNT). If + * CNT.COUNT happens to be bigger than the new MOD value then + * the counter will end up being reset way too late. Therefore, + * manually reset it to 0. + */ + if (!cmod) + writel(0x0, tpm->base + PWM_IMX_TPM_CNT); /* * set period count: * if the PWM is disabled (CMOD[1:0] =3D 2b00), then MOD register --=20 2.34.1