From nobody Mon Oct 6 01:51:35 2025 Received: from mail-wr1-f73.google.com (mail-wr1-f73.google.com [209.85.221.73]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CA61428641B for ; Mon, 28 Jul 2025 17:53:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.73 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753725240; cv=none; b=n3gQoI2+nWz+HpJFDyIRWMh+NbXcuhb98W9TZW25SL0bSYiX3OLX21tiHh85sPpQqSSRJqw3H4UuI677vqXyH0m9FefVOy3mmYdhAaipaqAC6nBZ3Q/u3FkyNPEMHh5vVfSAzGDD0xEjBbrw6+MFOrTIv6+nAbVWL4to3CPGBvw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753725240; c=relaxed/simple; bh=5CXwO+3dMDU4kX1Nb2jGlQpvWqjZDmaGhbdPDt03cYU=; h=Date:In-Reply-To:Mime-Version:References:Message-ID:Subject:From: To:Cc:Content-Type; b=iQc23UfoWyu7UmkO6n559yBWvkPmMWQqiksC4+drYvGPPvHdg4VFxnQLVnBUZ1twZBnmmCVpxAYn/6t8fRIUR5/F2flGtHyAdSxDaGG3EidHFRbchr9cgMp7YU8vd/bQYb/Ab04ICy551Q5xKsHqJ6Bx4aeFfDLq35vgSHreb3A= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com; spf=pass smtp.mailfrom=flex--smostafa.bounces.google.com; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b=p4rE+u/S; arc=none smtp.client-ip=209.85.221.73 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=flex--smostafa.bounces.google.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="p4rE+u/S" Received: by mail-wr1-f73.google.com with SMTP id ffacd0b85a97d-3b7892c42b7so888087f8f.0 for ; Mon, 28 Jul 2025 10:53:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1753725233; x=1754330033; darn=vger.kernel.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=DVGSgwZoE434l08ahOgSiVZME26vq9k77nmMG1Lfyxw=; b=p4rE+u/SjJU4Q9shhhnl1fROl3ThgD9DWdpgMd/YiiIGYT5SFCj5jFgSK9a/fBvPEd gnees0erMKzz1op8UajnLXadawfom/7rb3ZQSpXfy0x1meiGoEFaDF4kQeUIKw8btE7j RkB9ViPGPBenktg1tliNDc0TbiPcU87JMBMtU7/Worlt9ZtudAYx/qZJyjE3kHUMMytn 0yDPWuSgMfesy8RXR3CJQOlRh79rLVVWfH5+CbPa/4zTEazu/dLyak2dzMN+g76BN+iv POwGNGJuFqAM/+mlS+KiEHEl6V+ISr69xjsOUvAg0rG99//kdyQAh6oGXtSXd4mb+TRe 4ecw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1753725233; x=1754330033; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=DVGSgwZoE434l08ahOgSiVZME26vq9k77nmMG1Lfyxw=; b=tOqC/jegSfUUKIrhCUC+TMTOuIYpymgserKxhn6CvS8duZfKHsJ/y3DzF3QVpSSBYV U/XZZxGL2GznBiZiGsJKW9tQlnXDvq2ju5kbBngpuzbhIFh6W9KbI4CjbKuBaASiRZwo 93aSsboQUtaoqlhBuXbjISMMvaj37FFs1QPFXd6ZAbiPHVh806FB271YBSdEf/0mg52F FJ3jjgY1pFeZOKId1ekXuNtFkEn6hVJeTALCNjzDXcOhseNbRY7B8u7YV7iOcvQ+hu6N mdL7qSX9TCwkJKm0GQY77O3UoFf3Xz1iEPZbdFsFQOQFjH3cyg7bzWdAlHege88Ta21o ViKA== X-Gm-Message-State: AOJu0YxuH3aImFp039dyCMDiSl1+cKNe2f38PIxbReYYx3ilDJWF134t gfIFQrY9y7dQvaXVTlLmuFhq7VHJjCnmwCbhlcD6J6m2IECU+cL1QDYueAIGx3zHJG6sU0Jx0dj FnQY2/bFOiB05JVf3jLAnaDY7KyctM8qiIaHqtd2jEEqLR6m2yoBAh/4gWxhZWPKtOqcHf4d/gf 1jat815KjnK/1ko2pZYtUYQRkeH3fbLv/tCAA1Sohz+Eb9LgAp7wsFz/8= X-Google-Smtp-Source: AGHT+IE3DbSna5yWRpg9pDI/w3zNw6uczlG2QD/pr3gxP2WEiggoF+1EAE0R+toZgh10YxWOKOvftEYKiqbgHA== X-Received: from wrup1.prod.google.com ([2002:a5d:6381:0:b0:3a4:ddbd:cc32]) (user=smostafa job=prod-delivery.src-stubby-dispatcher) by 2002:a05:6000:40db:b0:3b7:7a4a:dbbf with SMTP id ffacd0b85a97d-3b77a4adc81mr6890156f8f.45.1753725232898; Mon, 28 Jul 2025 10:53:52 -0700 (PDT) Date: Mon, 28 Jul 2025 17:53:11 +0000 In-Reply-To: <20250728175316.3706196-1-smostafa@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20250728175316.3706196-1-smostafa@google.com> X-Mailer: git-send-email 2.50.1.552.g942d659e1b-goog Message-ID: <20250728175316.3706196-25-smostafa@google.com> Subject: [PATCH v3 24/29] iommu/arm-smmu-v3-kvm: Shadow the CPU stage-2 page table From: Mostafa Saleh To: linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev Cc: maz@kernel.org, oliver.upton@linux.dev, joey.gouly@arm.com, suzuki.poulose@arm.com, yuzenghui@huawei.com, catalin.marinas@arm.com, will@kernel.org, robin.murphy@arm.com, jean-philippe@linaro.org, qperret@google.com, tabba@google.com, jgg@ziepe.ca, mark.rutland@arm.com, praan@google.com, Mostafa Saleh Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Based on the callbacks from the hypervisor, update the SMMUv3 Identity mapped page table. Signed-off-by: Mostafa Saleh --- .../iommu/arm/arm-smmu-v3/pkvm/arm-smmu-v3.c | 161 +++++++++++++++++- .../iommu/arm/arm-smmu-v3/pkvm/arm_smmu_v3.h | 6 + 2 files changed, 166 insertions(+), 1 deletion(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/pkvm/arm-smmu-v3.c b/drivers/iom= mu/arm/arm-smmu-v3/pkvm/arm-smmu-v3.c index 5e988ffede92..38d81cd6d24a 100644 --- a/drivers/iommu/arm/arm-smmu-v3/pkvm/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/pkvm/arm-smmu-v3.c @@ -10,6 +10,7 @@ #include =20 #include "arm_smmu_v3.h" +#include "../../../io-pgtable-arm.h" =20 #define ARM_SMMU_POLL_TIMEOUT_US 100000 /* 100ms arbitrary timeout */ =20 @@ -48,6 +49,8 @@ struct hyp_arm_smmu_v3_device *kvm_hyp_arm_smmu_v3_smmus; smmu_wait(_cond); \ }) =20 +static struct io_pgtable *idmap_pgtable; + static int smmu_write_cr0(struct hyp_arm_smmu_v3_device *smmu, u32 val) { writel_relaxed(val, smmu->base + ARM_SMMU_CR0); @@ -130,6 +133,56 @@ static int smmu_send_cmd(struct hyp_arm_smmu_v3_device= *smmu, return smmu_sync_cmd(smmu); } =20 +static void __smmu_add_cmd(struct hyp_arm_smmu_v3_device *smmu, void *unus= ed, + struct arm_smmu_cmdq_ent *cmd) +{ + WARN_ON(smmu_add_cmd(smmu, cmd)); +} + +static int smmu_tlb_inv_range_smmu(struct hyp_arm_smmu_v3_device *smmu, + struct arm_smmu_cmdq_ent *cmd, + unsigned long iova, size_t size, size_t granule) +{ + arm_smmu_tlb_inv_build(cmd, iova, size, granule, + idmap_pgtable->cfg.pgsize_bitmap, smmu, + __smmu_add_cmd, NULL); + return smmu_sync_cmd(smmu); +} + +static void smmu_tlb_inv_range(unsigned long iova, size_t size, size_t gra= nule, + bool leaf) +{ + struct arm_smmu_cmdq_ent cmd =3D { + .opcode =3D CMDQ_OP_TLBI_S2_IPA, + .tlbi =3D { + .leaf =3D leaf, + .vmid =3D 0, + }, + }; + struct hyp_arm_smmu_v3_device *smmu; + + for_each_smmu(smmu) + WARN_ON(smmu_tlb_inv_range_smmu(smmu, &cmd, iova, size, granule)); +} + +static void smmu_tlb_flush_walk(unsigned long iova, size_t size, + size_t granule, void *cookie) +{ + smmu_tlb_inv_range(iova, size, granule, false); +} + +static void smmu_tlb_add_page(struct iommu_iotlb_gather *gather, + unsigned long iova, size_t granule, + void *cookie) +{ + smmu_tlb_inv_range(iova, granule, granule, true); +} + +static const struct iommu_flush_ops smmu_tlb_ops =3D { + .tlb_flush_walk =3D smmu_tlb_flush_walk, + .tlb_add_page =3D smmu_tlb_add_page, +}; + __maybe_unused static int smmu_sync_ste(struct hyp_arm_smmu_v3_device *smmu, u32 sid, uns= igned long ste) { @@ -377,6 +430,34 @@ static int smmu_init_device(struct hyp_arm_smmu_v3_dev= ice *smmu) return ret; } =20 +static int smmu_init_pgt(void) +{ + /* Default values overridden based on SMMUs common features. */ + struct io_pgtable_cfg cfg =3D (struct io_pgtable_cfg) { + .tlb =3D &smmu_tlb_ops, + .pgsize_bitmap =3D -1, + .ias =3D 48, + .oas =3D 48, + .coherent_walk =3D true, + }; + int ret =3D 0; + struct hyp_arm_smmu_v3_device *smmu; + + for_each_smmu(smmu) { + cfg.ias =3D min(cfg.ias, smmu->ias); + cfg.oas =3D min(cfg.oas, smmu->oas); + cfg.pgsize_bitmap &=3D smmu->pgsize_bitmap; + cfg.coherent_walk &=3D !!(smmu->features & ARM_SMMU_FEAT_COHERENCY); + } + + /* At least PAGE_SIZE must be supported by all SMMUs*/ + if ((cfg.pgsize_bitmap & PAGE_SIZE) =3D=3D 0) + return -EINVAL; + + idmap_pgtable =3D kvm_arm_io_pgtable_alloc(&cfg, NULL, ARM_64_LPAE_S2, &r= et); + return ret; +} + static int smmu_init(void) { int ret; @@ -398,7 +479,7 @@ static int smmu_init(void) goto out_reclaim_smmu; } =20 - return 0; + return smmu_init_pgt(); out_reclaim_smmu: while (smmu !=3D kvm_hyp_arm_smmu_v3_smmus) smmu_deinit_device(--smmu); @@ -406,7 +487,85 @@ static int smmu_init(void) return ret; } =20 +static size_t smmu_pgsize_idmap(size_t size, u64 paddr, size_t pgsize_bitm= ap) +{ + size_t pgsizes; + + /* Remove page sizes that are larger than the current size */ + pgsizes =3D pgsize_bitmap & GENMASK_ULL(__fls(size), 0); + + /* Remove page sizes that the address is not aligned to. */ + if (likely(paddr)) + pgsizes &=3D GENMASK_ULL(__ffs(paddr), 0); + + WARN_ON(!pgsizes); + + /* Return the larget page size that fits. */ + return BIT(__fls(pgsizes)); +} + +static void smmu_host_stage2_idmap(phys_addr_t start, phys_addr_t end, int= prot) +{ + size_t size =3D end - start; + size_t pgsize =3D PAGE_SIZE, pgcount; + size_t mapped, unmapped; + int ret; + struct io_pgtable *pgtable =3D idmap_pgtable; + + end =3D min(end, BIT(pgtable->cfg.oas)); + if (start >=3D end) + return; + + if (prot) { + if (!(prot & IOMMU_MMIO)) + prot |=3D IOMMU_CACHE; + + while (size) { + mapped =3D 0; + /* + * We handle pages size for memory and MMIO differently: + * - memory: Map everything with PAGE_SIZE, that is guaranteed to + * find memory as we allocated enough pages to cover the entire + * memory, we do that as io-pgtable-arm doesn't support + * split_blk_unmap logic any more, so we can't break blocks once + * mapped to tables. + * - MMIO: Unlike memory, pKVM allocate 1G to for all MMIO, while + * the MMIO space can be large, as it is assumed to cover the + * whole IAS that is not memory, we have to use block mappings, + * that is fine for MMIO as it is never donated at the moment, + * so we never need to unmap MMIO at the run time triggereing + * split block logic. + */ + if (prot & IOMMU_MMIO) + pgsize =3D smmu_pgsize_idmap(size, start, pgtable->cfg.pgsize_bitmap); + + pgcount =3D size / pgsize; + ret =3D pgtable->ops.map_pages(&pgtable->ops, start, start, + pgsize, pgcount, prot, 0, &mapped); + size -=3D mapped; + start +=3D mapped; + if (!mapped || ret) + return; + } + } else { + /* Shouldn't happen. */ + WARN_ON(prot & IOMMU_MMIO); + while (size) { + pgcount =3D size / pgsize; + unmapped =3D pgtable->ops.unmap_pages(&pgtable->ops, start, + pgsize, pgcount, NULL); + size -=3D unmapped; + start +=3D unmapped; + if (!unmapped) + return; + } + /* Some memory were not unmapped. */ + WARN_ON(size); + } +} + /* Shared with the kernel driver in EL1 */ struct kvm_iommu_ops smmu_ops =3D { .init =3D smmu_init, + .host_stage2_idmap =3D smmu_host_stage2_idmap, }; diff --git a/drivers/iommu/arm/arm-smmu-v3/pkvm/arm_smmu_v3.h b/drivers/iom= mu/arm/arm-smmu-v3/pkvm/arm_smmu_v3.h index d188537545b1..5c2f121837ad 100644 --- a/drivers/iommu/arm/arm-smmu-v3/pkvm/arm_smmu_v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/pkvm/arm_smmu_v3.h @@ -14,6 +14,9 @@ * @features SMMUv3 features as defined in arm-smmu-v3-common.h * @cmdq CMDQ queue struct * @strtab_cfg stream table config, strtab_cfg.l2.l2ptrs is not used + * @ias IAS of the SMMUv3 + * @oas OAS of the SMMUv3 + * @pgsize_bitmap Pages sizes supported by the SMMUv3 * Other members are filled and used at runtime by the SMMU driver. */ struct hyp_arm_smmu_v3_device { @@ -23,6 +26,9 @@ struct hyp_arm_smmu_v3_device { unsigned long features; struct arm_smmu_queue cmdq; struct arm_smmu_strtab_cfg strtab_cfg; + unsigned int ias; + unsigned int oas; + size_t pgsize_bitmap; }; =20 extern size_t kvm_nvhe_sym(kvm_hyp_arm_smmu_v3_count); --=20 2.50.1.552.g942d659e1b-goog