From nobody Sun Oct 5 23:42:37 2025 Received: from layka.disroot.org (layka.disroot.org [178.21.23.139]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A086B1F55F8; Mon, 28 Jul 2025 10:30:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=178.21.23.139 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753698640; cv=none; b=gQLscSooMDmYJAE1vYrMCaUpEXvUCKQMzZ78bqP4Tyaso/f9cTnZpeDqauRo/BH5gpmm5/2G8zFXfvSwqsulQJec65ftlfpA/UtOYdtTb8Y3vlmFpf1ZfGbaUK+FT74w61eYFNzLP75BxLEmvnuxTvFV4CLSfnBUPYBmGkjibBU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753698640; c=relaxed/simple; bh=Jfm+a3MgKlJehkc71YMruhRwgQp6YcyxJyDDAsg6U9c=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Yb0hchAK2yUd5DTVPju+xJgDevkUgfDfl83SOzmnNHvRZhW1Ul3vxhyZAW74rmJ2/Xd/D9W4ah9EPp9ClUg+aSOapYioMnOPslq/UQ2gHUVbaIrQeeGISF37hayt+hC5p6FkhoY293efg6mmTu1ki2t9zCbSGmql+1+Yhs19yiU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org; spf=pass smtp.mailfrom=disroot.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b=dj1ravgx; arc=none smtp.client-ip=178.21.23.139 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=disroot.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b="dj1ravgx" Received: from mail01.disroot.lan (localhost [127.0.0.1]) by disroot.org (Postfix) with ESMTP id CD7D022B59; Mon, 28 Jul 2025 12:30:36 +0200 (CEST) X-Virus-Scanned: SPAM Filter at disroot.org Received: from layka.disroot.org ([127.0.0.1]) by localhost (disroot.org [127.0.0.1]) (amavis, port 10024) with ESMTP id Pu-hSX5CNDgp; Mon, 28 Jul 2025 12:30:36 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=disroot.org; s=mail; t=1753698636; bh=Jfm+a3MgKlJehkc71YMruhRwgQp6YcyxJyDDAsg6U9c=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=dj1ravgxkuRYsKVGCSW3SvyFQIM0EK24lPgw+PyZ7UsFuqc1uTmMPVrXup/mrHAkg H6xokRarAW7zexhG8HzfKX+MqNobF8K88y1jZawn3FHl9Sh4wc+ssyZdMMWoBDmF+Z Gw6vAWe4LRlINp8Jdh/hIZbI0ip4MGez/0IUNFumDyeXoXJQx01IKvdWVCtjXaJW+Q 2ytRew78fOB1OlugCfvqX59yxJhKwo3UPMCeG6TyyWoFPJv6+XmWRJgjxaMvCU3thV noK/3IEodeyb6y06JxK+L/b56M1W5hNxIfE47wOOu6RgDP6pVCBgcJOTsuqh1JK6mP KMYiBf5SNfcig== From: Yao Zi To: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Yao Zi , Frank Wang , Andy Yan , Cristian Ciocaltea , Detlev Casanova , Shresth Prasad , Chukun Pan , Jonas Karlman Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Conor Dooley Subject: [PATCH v5 1/6] dt-bindings: soc: rockchip: Add RK3528 pipe-phy GRF syscon Date: Mon, 28 Jul 2025 10:29:43 +0000 Message-ID: <20250728102947.38984-3-ziyao@disroot.org> In-Reply-To: <20250728102947.38984-2-ziyao@disroot.org> References: <20250728102947.38984-2-ziyao@disroot.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add compatible string for pipe-phy GRF found on RK3528 SoC, which controls misc settings for the integrated naneng-combphy. Signed-off-by: Yao Zi Acked-by: Conor Dooley --- Documentation/devicetree/bindings/soc/rockchip/grf.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml b/Docu= mentation/devicetree/bindings/soc/rockchip/grf.yaml index 1ab0b092e2a5..fe5361713167 100644 --- a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml +++ b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml @@ -16,6 +16,7 @@ properties: - enum: - rockchip,rk3288-sgrf - rockchip,rk3528-ioc-grf + - rockchip,rk3528-pipe-phy-grf - rockchip,rk3528-vo-grf - rockchip,rk3528-vpu-grf - rockchip,rk3562-ioc-grf --=20 2.50.1 From nobody Sun Oct 5 23:42:37 2025 Received: from layka.disroot.org (layka.disroot.org [178.21.23.139]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2BE0D1CAA79; Mon, 28 Jul 2025 10:30:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=178.21.23.139 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753698647; cv=none; b=P7ALPxGKyB+a7hzU9F3WsB6aoD4acyXIq/3Sf/rajtuEGaaR1/YWJ4AMS4vEHGtcMLh921TrnSkABXXjk2sl2DI6BiNK+tvsVNFUKxIqkbXkhtKqLjeHQSVy+CqEiOOsZu2NMoHzsHiYyE4hj9Cm1tq513ddUEananwPxD/kuDw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753698647; c=relaxed/simple; bh=qBq1mAbqPGcYbgpJSKXM1JGiaWrzbRbM/TI0PBE0xY0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=c2CAYVlnHj3Z9l++jSekO8zqrrXk14duUUrU9axikvizujTeqJqboMjoF3Qhwc2SAS8jgOE4k2pKFItS9s19jM4MEOtJlEZR3uCcsn07Btgd1BY3QM5QCcVv/SM0P+j2bvzBd0OlSrEISomJvcmUB+nWVLpzmARdPsuOS7fZ3As= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org; spf=pass smtp.mailfrom=disroot.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b=TUchOU/S; arc=none smtp.client-ip=178.21.23.139 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=disroot.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b="TUchOU/S" Received: from mail01.disroot.lan (localhost [127.0.0.1]) by disroot.org (Postfix) with ESMTP id 7F4A420543; Mon, 28 Jul 2025 12:30:44 +0200 (CEST) X-Virus-Scanned: SPAM Filter at disroot.org Received: from layka.disroot.org ([127.0.0.1]) by localhost (disroot.org [127.0.0.1]) (amavis, port 10024) with ESMTP id Gwt0ajRAJT6O; Mon, 28 Jul 2025 12:30:43 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=disroot.org; s=mail; t=1753698643; bh=qBq1mAbqPGcYbgpJSKXM1JGiaWrzbRbM/TI0PBE0xY0=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=TUchOU/SQEB9L4HSGKdfTXHX2uvc99PVC0fxVj0a+JJIdSxcTldtffVCTJCs9RrDR mIajvxVZ9IRcn0Lwwle3hMQP0Vtc4Oo+Dpe4nAnunD8BKTV3Ekc6d6/Wl7uEwSdc0L Hzq9xapTQwd3XnVaHLtFWoPaW/dfVkaF5QZh4RDbkCVyJmssQCHpSzK2lzBBTWnR3w xMVTIFSmV3t3s+OXhASb1HDuEu1uI7bja8wX5Quq4nuqjcIwUF5x8zl9qPPxg4AnLQ /6eFhhX5rRbJgKsjtJkbvnQ6KuTjOlHb/4IiJvg5r1K9d0hRF5tutOWzWoMYKBjDOQ NWeh9mz4Rlw1A== From: Yao Zi To: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Yao Zi , Frank Wang , Andy Yan , Cristian Ciocaltea , Detlev Casanova , Shresth Prasad , Chukun Pan , Jonas Karlman Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski Subject: [PATCH v5 2/6] dt-bindings: phy: rockchip: naneng-combphy: Add power-domains property Date: Mon, 28 Jul 2025 10:29:44 +0000 Message-ID: <20250728102947.38984-4-ziyao@disroot.org> In-Reply-To: <20250728102947.38984-2-ziyao@disroot.org> References: <20250728102947.38984-2-ziyao@disroot.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Though isn't described in existing devicetrees, most Rockchip combphys belong to a specific power-domain of the SoC. Taking RK3588 as example, combphy 0 and combphy 2 belong to the PD_BUS domain. Document the power-domains property to allow describing the information correctly in devicetree. Signed-off-by: Yao Zi Acked-by: Krzysztof Kozlowski --- .../devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-comb= phy.yaml b/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combph= y.yaml index 3e101c3c5ea9..db293d2fbf1a 100644 --- a/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml +++ b/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml @@ -45,6 +45,9 @@ properties: phy-supply: description: Single PHY regulator =20 + power-domains: + maxItems: 1 + rockchip,enable-ssc: type: boolean description: --=20 2.50.1 From nobody Sun Oct 5 23:42:37 2025 Received: from layka.disroot.org (layka.disroot.org [178.21.23.139]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0B8A028FD; Mon, 28 Jul 2025 10:31:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=178.21.23.139 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753698697; cv=none; b=WPcuQKSUSqye7lHBtmOh2zzqpFwEVWmVJLdutOX1cHFnd+ttUCoHsHCe/c64sOdGhJi7KqzUka283FGt28qdOC9DS2oDoSsXpGr7ZY1a1I81+pELLh1L5vMmfdiD8wM6L2WRRK7i13VGk/MCXmLRmMsLAdGYP9MM0YNdmNiAfk0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753698697; c=relaxed/simple; bh=71Nflu6ZSpSla06ibWGymwe/vOoXdf0KH4ceGapV22M=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=oaOWJEMzidHlZQlNZVY1K9g4XQXjKmkpcSz5h5gZYLOA8FBhrMEXT3MKDczVTm7Kjs1QMmw/hslYkZvxB1WThHrLI2R9QPnPHIVOaCrjlvZe9GMWWCwBHLnW5rosv9pMM8UIo6NfXV9hpZU+loDYXC6U2J0cyhRHul17fUdVMiA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org; spf=pass smtp.mailfrom=disroot.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b=AN3F9qHU; arc=none smtp.client-ip=178.21.23.139 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=disroot.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b="AN3F9qHU" Received: from mail01.disroot.lan (localhost [127.0.0.1]) by disroot.org (Postfix) with ESMTP id 94C6B20937; Mon, 28 Jul 2025 12:31:34 +0200 (CEST) X-Virus-Scanned: SPAM Filter at disroot.org Received: from layka.disroot.org ([127.0.0.1]) by localhost (disroot.org [127.0.0.1]) (amavis, port 10024) with ESMTP id oeKHiVJoWaZv; Mon, 28 Jul 2025 12:31:31 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=disroot.org; s=mail; t=1753698691; bh=71Nflu6ZSpSla06ibWGymwe/vOoXdf0KH4ceGapV22M=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=AN3F9qHU7kxzi0BCj8fvL5CbV0+7N/rLjp0497l7VSsSd1BUNN3/98Dd8nuCqww+K U3y4k5eW6XPqw9/yQfmuE0/Ql+eh1jvDm/DdbNMFruRn6bQvOU/yDLjFQHd+x0fsdO gTKkuop+/qpc2+aKlG3RZgxPwk85eoVcLwO4lZI48YnJyX71w1ijgkxfmRqP+hMUJI eWpK3DogH+Mi8dREBvX/z8VRt2IQsex1634ZRBKarCIW9O6ssmVlqP4w6z1cRM6kT0 zBNof9+S1JJPJWpLLBrXrinAVDUAbZ2sE9QW1VSON28D4Yws4l+kDMfanZN7bLmLxh SuqvoEOEREcgQ== From: Yao Zi To: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Yao Zi , Frank Wang , Andy Yan , Cristian Ciocaltea , Detlev Casanova , Shresth Prasad , Chukun Pan , Jonas Karlman Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Conor Dooley Subject: [PATCH v5 3/6] dt-bindings: phy: rockchip: naneng-combphy: Add RK3528 variant Date: Mon, 28 Jul 2025 10:29:45 +0000 Message-ID: <20250728102947.38984-5-ziyao@disroot.org> In-Reply-To: <20250728102947.38984-2-ziyao@disroot.org> References: <20250728102947.38984-2-ziyao@disroot.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Rockchip RK3528 ships one naneng-combphy which operates in either PCIe or USB 3 mode. Document its compatible string. Signed-off-by: Yao Zi Acked-by: Conor Dooley --- .../devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-comb= phy.yaml b/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combph= y.yaml index db293d2fbf1a..379b08bd9e97 100644 --- a/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml +++ b/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml @@ -12,6 +12,7 @@ maintainers: properties: compatible: enum: + - rockchip,rk3528-naneng-combphy - rockchip,rk3562-naneng-combphy - rockchip,rk3568-naneng-combphy - rockchip,rk3576-naneng-combphy @@ -108,7 +109,9 @@ allOf: properties: compatible: contains: - const: rockchip,rk3588-naneng-combphy + enum: + - rockchip,rk3528-naneng-combphy + - rockchip,rk3588-naneng-combphy then: properties: resets: --=20 2.50.1 From nobody Sun Oct 5 23:42:37 2025 Received: from layka.disroot.org (layka.disroot.org [178.21.23.139]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B366120125F; Mon, 28 Jul 2025 10:31:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=178.21.23.139 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753698708; cv=none; b=py/00DNouasm0hh5ObJm2atbRvtIW3EPcubIm0R5y3PfnRO6mKfD855QTdqp6jSpJxQpMG0wY6UEbdaZhM7I1/R6PNAML1++ymOa8baEDvsgJ3AkeMsepttLkyAl0i3KJI1wf8NtlQyoIhpI4kF0ORE/bCSFS2gdjk7wFZ7UmIA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753698708; c=relaxed/simple; bh=ZtOV4IYs3bEs6SzNiKxxh8GuJNwLXHCTefRw/zC2Rzs=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=CuRb3sNhcRRBsKCj3C2e8C1zH3bqbOrfCxPHUtiFWCUXTovQGi+2HxTOM2A10xLaXzR71OZFtpV4TqKa2+ixVADZMZhzd3f6JfboFDWyEZjyKDq/tXCtMHyg7G6iCkXbFZ9+nd4y1E6nCl5fyNaLr+mk5IWpiD1Hqp3iC2sXwvs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org; spf=pass smtp.mailfrom=disroot.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b=QYdYEPqW; arc=none smtp.client-ip=178.21.23.139 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=disroot.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b="QYdYEPqW" Received: from mail01.disroot.lan (localhost [127.0.0.1]) by disroot.org (Postfix) with ESMTP id 658A720830; Mon, 28 Jul 2025 12:31:44 +0200 (CEST) X-Virus-Scanned: SPAM Filter at disroot.org Received: from layka.disroot.org ([127.0.0.1]) by localhost (disroot.org [127.0.0.1]) (amavis, port 10024) with ESMTP id phgxSNFa55pI; Mon, 28 Jul 2025 12:31:38 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=disroot.org; s=mail; t=1753698698; bh=ZtOV4IYs3bEs6SzNiKxxh8GuJNwLXHCTefRw/zC2Rzs=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=QYdYEPqWpotsI0XmdQioIQ4ZqSosGJQ/20rPtT2b1nVcqVbxAyW05rLYlrhpEOapp 8uMKhaMdVMjFXpm0fvEhSp4RyyP/zDuAjuK/2nXWxOlB+Qo74F8zvWV25ljeH3FKHH LKemO23Dfmggvpxt2AfiBiWcHl0JvbUwCF7qAW/ow5MpZjYHdSmjW4QrSPGG6rB72z XTe+/q5NdF87F2tfYv4YMt5zR5aTVFmTN5f7Fx3jgXV481CnEn8je7QGtplLpyQO0P kgfSIk6bnTGDnCqoeQwPJpl/JF7kMKQYCmoU/wONoeRing3oWua4liSrlfK9f4WNPr d3DiUBZSmDgCQ== From: Yao Zi To: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Yao Zi , Frank Wang , Andy Yan , Cristian Ciocaltea , Detlev Casanova , Shresth Prasad , Chukun Pan , Jonas Karlman Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Neil Armstrong Subject: [PATCH v5 4/6] phy: rockchip: naneng-combphy: Add SoC prefix to register definitions Date: Mon, 28 Jul 2025 10:29:46 +0000 Message-ID: <20250728102947.38984-6-ziyao@disroot.org> In-Reply-To: <20250728102947.38984-2-ziyao@disroot.org> References: <20250728102947.38984-2-ziyao@disroot.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" All supported variants of naneng-combphy follow a register layout similar to the RK3568 variant with some exceptions of SoC-specific registers. Add RK3568 prefix for the common set of registers and the corresponding SoC prefix for SoC-specific registers, making usage of definitions clear and preparing for future COMBPHY variants with a different register layout. Signed-off-by: Yao Zi Reviewed-by: Heiko Stuebner Reviewed-by: Neil Armstrong --- .../rockchip/phy-rockchip-naneng-combphy.c | 560 +++++++++--------- 1 file changed, 288 insertions(+), 272 deletions(-) diff --git a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c b/drivers/p= hy/rockchip/phy-rockchip-naneng-combphy.c index 17c6310f4b54..ce84166cd772 100644 --- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c +++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c @@ -21,78 +21,80 @@ #define REF_CLOCK_100MHz (100 * HZ_PER_MHZ) =20 /* COMBO PHY REG */ -#define PHYREG6 0x14 -#define PHYREG6_PLL_DIV_MASK GENMASK(7, 6) -#define PHYREG6_PLL_DIV_SHIFT 6 -#define PHYREG6_PLL_DIV_2 1 - -#define PHYREG7 0x18 -#define PHYREG7_TX_RTERM_MASK GENMASK(7, 4) -#define PHYREG7_TX_RTERM_SHIFT 4 -#define PHYREG7_TX_RTERM_50OHM 8 -#define PHYREG7_RX_RTERM_MASK GENMASK(3, 0) -#define PHYREG7_RX_RTERM_SHIFT 0 -#define PHYREG7_RX_RTERM_44OHM 15 - -#define PHYREG8 0x1C -#define PHYREG8_SSC_EN BIT(4) - -#define PHYREG10 0x24 -#define PHYREG10_SSC_PCM_MASK GENMASK(3, 0) -#define PHYREG10_SSC_PCM_3500PPM 7 - -#define PHYREG11 0x28 -#define PHYREG11_SU_TRIM_0_7 0xF0 - -#define PHYREG12 0x2C -#define PHYREG12_PLL_LPF_ADJ_VALUE 4 - -#define PHYREG13 0x30 -#define PHYREG13_RESISTER_MASK GENMASK(5, 4) -#define PHYREG13_RESISTER_SHIFT 0x4 -#define PHYREG13_RESISTER_HIGH_Z 3 -#define PHYREG13_CKRCV_AMP0 BIT(7) - -#define PHYREG14 0x34 -#define PHYREG14_CKRCV_AMP1 BIT(0) - -#define PHYREG15 0x38 -#define PHYREG15_CTLE_EN BIT(0) -#define PHYREG15_SSC_CNT_MASK GENMASK(7, 6) -#define PHYREG15_SSC_CNT_SHIFT 6 -#define PHYREG15_SSC_CNT_VALUE 1 - -#define PHYREG16 0x3C -#define PHYREG16_SSC_CNT_VALUE 0x5f - -#define PHYREG17 0x40 - -#define PHYREG18 0x44 -#define PHYREG18_PLL_LOOP 0x32 - -#define PHYREG21 0x50 -#define PHYREG21_RX_SQUELCH_VAL 0x0D - -#define PHYREG27 0x6C -#define PHYREG27_RX_TRIM_RK3588 0x4C - -#define PHYREG30 0x74 - -#define PHYREG32 0x7C -#define PHYREG32_SSC_MASK GENMASK(7, 4) -#define PHYREG32_SSC_DIR_MASK GENMASK(5, 4) -#define PHYREG32_SSC_DIR_SHIFT 4 -#define PHYREG32_SSC_UPWARD 0 -#define PHYREG32_SSC_DOWNWARD 1 -#define PHYREG32_SSC_OFFSET_MASK GENMASK(7, 6) -#define PHYREG32_SSC_OFFSET_SHIFT 6 -#define PHYREG32_SSC_OFFSET_500PPM 1 - -#define PHYREG33 0x80 -#define PHYREG33_PLL_KVCO_MASK GENMASK(4, 2) -#define PHYREG33_PLL_KVCO_SHIFT 2 -#define PHYREG33_PLL_KVCO_VALUE 2 -#define PHYREG33_PLL_KVCO_VALUE_RK3576 4 +#define RK3568_PHYREG6 0x14 +#define RK3568_PHYREG6_PLL_DIV_MASK GENMASK(7, 6) +#define RK3568_PHYREG6_PLL_DIV_SHIFT 6 +#define RK3568_PHYREG6_PLL_DIV_2 1 + +#define RK3568_PHYREG7 0x18 +#define RK3568_PHYREG7_TX_RTERM_MASK GENMASK(7, 4) +#define RK3568_PHYREG7_TX_RTERM_SHIFT 4 +#define RK3568_PHYREG7_TX_RTERM_50OHM 8 +#define RK3568_PHYREG7_RX_RTERM_MASK GENMASK(3, 0) +#define RK3568_PHYREG7_RX_RTERM_SHIFT 0 +#define RK3568_PHYREG7_RX_RTERM_44OHM 15 + +#define RK3568_PHYREG8 0x1C +#define RK3568_PHYREG8_SSC_EN BIT(4) + +#define RK3568_PHYREG11 0x28 +#define RK3568_PHYREG11_SU_TRIM_0_7 0xF0 + +#define RK3568_PHYREG12 0x2C +#define RK3568_PHYREG12_PLL_LPF_ADJ_VALUE 4 + +#define RK3568_PHYREG13 0x30 +#define RK3568_PHYREG13_RESISTER_MASK GENMASK(5, 4) +#define RK3568_PHYREG13_RESISTER_SHIFT 0x4 +#define RK3568_PHYREG13_RESISTER_HIGH_Z 3 +#define RK3568_PHYREG13_CKRCV_AMP0 BIT(7) + +#define RK3568_PHYREG14 0x34 +#define RK3568_PHYREG14_CKRCV_AMP1 BIT(0) + +#define RK3568_PHYREG15 0x38 +#define RK3568_PHYREG15_CTLE_EN BIT(0) +#define RK3568_PHYREG15_SSC_CNT_MASK GENMASK(7, 6) +#define RK3568_PHYREG15_SSC_CNT_SHIFT 6 +#define RK3568_PHYREG15_SSC_CNT_VALUE 1 + +#define RK3568_PHYREG16 0x3C +#define RK3568_PHYREG16_SSC_CNT_VALUE 0x5f + +#define RK3568_PHYREG18 0x44 +#define RK3568_PHYREG18_PLL_LOOP 0x32 + +#define RK3568_PHYREG32 0x7C +#define RK3568_PHYREG32_SSC_MASK GENMASK(7, 4) +#define RK3568_PHYREG32_SSC_DIR_MASK GENMASK(5, 4) +#define RK3568_PHYREG32_SSC_DIR_SHIFT 4 +#define RK3568_PHYREG32_SSC_UPWARD 0 +#define RK3568_PHYREG32_SSC_DOWNWARD 1 +#define RK3568_PHYREG32_SSC_OFFSET_MASK GENMASK(7, 6) +#define RK3568_PHYREG32_SSC_OFFSET_SHIFT 6 +#define RK3568_PHYREG32_SSC_OFFSET_500PPM 1 + +#define RK3568_PHYREG33 0x80 +#define RK3568_PHYREG33_PLL_KVCO_MASK GENMASK(4, 2) +#define RK3568_PHYREG33_PLL_KVCO_SHIFT 2 +#define RK3568_PHYREG33_PLL_KVCO_VALUE 2 +#define RK3576_PHYREG33_PLL_KVCO_VALUE 4 + +/* RK3588 COMBO PHY registers */ +#define RK3588_PHYREG27 0x6C +#define RK3588_PHYREG27_RX_TRIM 0x4C + +/* RK3576 COMBO PHY registers */ +#define RK3576_PHYREG10 0x24 +#define RK3576_PHYREG10_SSC_PCM_MASK GENMASK(3, 0) +#define RK3576_PHYREG10_SSC_PCM_3500PPM 7 + +#define RK3576_PHYREG17 0x40 + +#define RK3576_PHYREG21 0x50 +#define RK3576_PHYREG21_RX_SQUELCH_VAL 0x0D + +#define RK3576_PHYREG30 0x74 =20 struct rockchip_combphy_priv; =20 @@ -407,9 +409,8 @@ static int rk3562_combphy_cfg(struct rockchip_combphy_p= riv *priv) switch (priv->type) { case PHY_TYPE_PCIE: /* Set SSC downward spread spectrum */ - rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK, - PHYREG32_SSC_DOWNWARD << PHYREG32_SSC_DIR_SHIFT, - PHYREG32); + val =3D RK3568_PHYREG32_SSC_DOWNWARD << RK3568_PHYREG32_SSC_DIR_SHIFT; + rockchip_combphy_updatel(priv, RK3568_PHYREG32_SSC_MASK, val, RK3568_PHY= REG32); =20 rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_pcie, true); rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_pcie, true); @@ -418,29 +419,30 @@ static int rk3562_combphy_cfg(struct rockchip_combphy= _priv *priv) break; case PHY_TYPE_USB3: /* Set SSC downward spread spectrum */ - rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK, - PHYREG32_SSC_DOWNWARD << PHYREG32_SSC_DIR_SHIFT, - PHYREG32); + val =3D RK3568_PHYREG32_SSC_DOWNWARD << RK3568_PHYREG32_SSC_DIR_SHIFT; + rockchip_combphy_updatel(priv, RK3568_PHYREG32_SSC_MASK, val, + RK3568_PHYREG32); =20 /* Enable adaptive CTLE for USB3.0 Rx */ - rockchip_combphy_updatel(priv, PHYREG15_CTLE_EN, - PHYREG15_CTLE_EN, PHYREG15); + rockchip_combphy_updatel(priv, RK3568_PHYREG15_CTLE_EN, + RK3568_PHYREG15_CTLE_EN, RK3568_PHYREG15); =20 /* Set PLL KVCO fine tuning signals */ - rockchip_combphy_updatel(priv, PHYREG33_PLL_KVCO_MASK, BIT(3), PHYREG33); + rockchip_combphy_updatel(priv, RK3568_PHYREG33_PLL_KVCO_MASK, + BIT(3), RK3568_PHYREG33); =20 /* Set PLL LPF R1 to su_trim[10:7]=3D1001 */ - writel(PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + PHYREG12); + writel(RK3568_PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + RK3568_PHYREG12); =20 /* Set PLL input clock divider 1/2 */ - val =3D FIELD_PREP(PHYREG6_PLL_DIV_MASK, PHYREG6_PLL_DIV_2); - rockchip_combphy_updatel(priv, PHYREG6_PLL_DIV_MASK, val, PHYREG6); + val =3D FIELD_PREP(RK3568_PHYREG6_PLL_DIV_MASK, RK3568_PHYREG6_PLL_DIV_2= ); + rockchip_combphy_updatel(priv, RK3568_PHYREG6_PLL_DIV_MASK, val, RK3568_= PHYREG6); =20 /* Set PLL loop divider */ - writel(PHYREG18_PLL_LOOP, priv->mmio + PHYREG18); + writel(RK3568_PHYREG18_PLL_LOOP, priv->mmio + RK3568_PHYREG18); =20 /* Set PLL KVCO to min and set PLL charge pump current to max */ - writel(PHYREG11_SU_TRIM_0_7, priv->mmio + PHYREG11); + writel(RK3568_PHYREG11_SU_TRIM_0_7, priv->mmio + RK3568_PHYREG11); =20 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_sel_usb, true); rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false= ); @@ -458,11 +460,12 @@ static int rk3562_combphy_cfg(struct rockchip_combphy= _priv *priv) case REF_CLOCK_24MHz: if (priv->type =3D=3D PHY_TYPE_USB3) { /* Set ssc_cnt[9:0]=3D0101111101 & 31.5KHz */ - val =3D FIELD_PREP(PHYREG15_SSC_CNT_MASK, PHYREG15_SSC_CNT_VALUE); - rockchip_combphy_updatel(priv, PHYREG15_SSC_CNT_MASK, - val, PHYREG15); + val =3D FIELD_PREP(RK3568_PHYREG15_SSC_CNT_MASK, + RK3568_PHYREG15_SSC_CNT_VALUE); + rockchip_combphy_updatel(priv, RK3568_PHYREG15_SSC_CNT_MASK, + val, RK3568_PHYREG15); =20 - writel(PHYREG16_SSC_CNT_VALUE, priv->mmio + PHYREG16); + writel(RK3568_PHYREG16_SSC_CNT_VALUE, priv->mmio + RK3568_PHYREG16); } break; case REF_CLOCK_25MHz: @@ -472,19 +475,20 @@ static int rk3562_combphy_cfg(struct rockchip_combphy= _priv *priv) rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_100m, true); if (priv->type =3D=3D PHY_TYPE_PCIE) { /* PLL KVCO tuning fine */ - val =3D FIELD_PREP(PHYREG33_PLL_KVCO_MASK, PHYREG33_PLL_KVCO_VALUE); - rockchip_combphy_updatel(priv, PHYREG33_PLL_KVCO_MASK, - val, PHYREG33); + val =3D FIELD_PREP(RK3568_PHYREG33_PLL_KVCO_MASK, + RK3568_PHYREG33_PLL_KVCO_VALUE); + rockchip_combphy_updatel(priv, RK3568_PHYREG33_PLL_KVCO_MASK, + val, RK3568_PHYREG33); =20 /* Enable controlling random jitter, aka RMJ */ - writel(0x4, priv->mmio + PHYREG12); + writel(0x4, priv->mmio + RK3568_PHYREG12); =20 - val =3D PHYREG6_PLL_DIV_2 << PHYREG6_PLL_DIV_SHIFT; - rockchip_combphy_updatel(priv, PHYREG6_PLL_DIV_MASK, - val, PHYREG6); + val =3D RK3568_PHYREG6_PLL_DIV_2 << RK3568_PHYREG6_PLL_DIV_SHIFT; + rockchip_combphy_updatel(priv, RK3568_PHYREG6_PLL_DIV_MASK, + val, RK3568_PHYREG6); =20 - writel(0x32, priv->mmio + PHYREG18); - writel(0xf0, priv->mmio + PHYREG11); + writel(0x32, priv->mmio + RK3568_PHYREG18); + writel(0xf0, priv->mmio + RK3568_PHYREG11); } break; default: @@ -495,20 +499,21 @@ static int rk3562_combphy_cfg(struct rockchip_combphy= _priv *priv) if (priv->ext_refclk) { rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_ext, true); if (priv->type =3D=3D PHY_TYPE_PCIE && rate =3D=3D REF_CLOCK_100MHz) { - val =3D PHYREG13_RESISTER_HIGH_Z << PHYREG13_RESISTER_SHIFT; - val |=3D PHYREG13_CKRCV_AMP0; - rockchip_combphy_updatel(priv, PHYREG13_RESISTER_MASK, val, PHYREG13); - - val =3D readl(priv->mmio + PHYREG14); - val |=3D PHYREG14_CKRCV_AMP1; - writel(val, priv->mmio + PHYREG14); + val =3D RK3568_PHYREG13_RESISTER_HIGH_Z << RK3568_PHYREG13_RESISTER_SHI= FT; + val |=3D RK3568_PHYREG13_CKRCV_AMP0; + rockchip_combphy_updatel(priv, RK3568_PHYREG13_RESISTER_MASK, val, + RK3568_PHYREG13); + + val =3D readl(priv->mmio + RK3568_PHYREG14); + val |=3D RK3568_PHYREG14_CKRCV_AMP1; + writel(val, priv->mmio + RK3568_PHYREG14); } } =20 if (priv->enable_ssc) { - val =3D readl(priv->mmio + PHYREG8); - val |=3D PHYREG8_SSC_EN; - writel(val, priv->mmio + PHYREG8); + val =3D readl(priv->mmio + RK3568_PHYREG8); + val |=3D RK3568_PHYREG8_SSC_EN; + writel(val, priv->mmio + RK3568_PHYREG8); } =20 return 0; @@ -555,9 +560,9 @@ static int rk3568_combphy_cfg(struct rockchip_combphy_p= riv *priv) switch (priv->type) { case PHY_TYPE_PCIE: /* Set SSC downward spread spectrum. */ - rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK, - PHYREG32_SSC_DOWNWARD << PHYREG32_SSC_DIR_SHIFT, - PHYREG32); + val =3D RK3568_PHYREG32_SSC_DOWNWARD << RK3568_PHYREG32_SSC_DIR_SHIFT; + + rockchip_combphy_updatel(priv, RK3568_PHYREG32_SSC_MASK, val, RK3568_PHY= REG32); =20 rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_pcie, true); rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_pcie, true); @@ -567,30 +572,28 @@ static int rk3568_combphy_cfg(struct rockchip_combphy= _priv *priv) =20 case PHY_TYPE_USB3: /* Set SSC downward spread spectrum. */ - rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK, - PHYREG32_SSC_DOWNWARD << PHYREG32_SSC_DIR_SHIFT, - PHYREG32); + val =3D RK3568_PHYREG32_SSC_DOWNWARD << RK3568_PHYREG32_SSC_DIR_SHIFT, + rockchip_combphy_updatel(priv, RK3568_PHYREG32_SSC_MASK, val, RK3568_PHY= REG32); =20 /* Enable adaptive CTLE for USB3.0 Rx. */ - val =3D readl(priv->mmio + PHYREG15); - val |=3D PHYREG15_CTLE_EN; - writel(val, priv->mmio + PHYREG15); + val =3D readl(priv->mmio + RK3568_PHYREG15); + val |=3D RK3568_PHYREG15_CTLE_EN; + writel(val, priv->mmio + RK3568_PHYREG15); =20 /* Set PLL KVCO fine tuning signals. */ - rockchip_combphy_updatel(priv, PHYREG33_PLL_KVCO_MASK, - PHYREG33_PLL_KVCO_VALUE << PHYREG33_PLL_KVCO_SHIFT, - PHYREG33); + val =3D RK3568_PHYREG33_PLL_KVCO_VALUE << RK3568_PHYREG33_PLL_KVCO_SHIFT; + rockchip_combphy_updatel(priv, RK3568_PHYREG33_PLL_KVCO_MASK, val, RK356= 8_PHYREG33); =20 /* Enable controlling random jitter. */ - writel(PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + PHYREG12); + writel(RK3568_PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + RK3568_PHYREG12); =20 /* Set PLL input clock divider 1/2. */ - rockchip_combphy_updatel(priv, PHYREG6_PLL_DIV_MASK, - PHYREG6_PLL_DIV_2 << PHYREG6_PLL_DIV_SHIFT, - PHYREG6); + rockchip_combphy_updatel(priv, RK3568_PHYREG6_PLL_DIV_MASK, + RK3568_PHYREG6_PLL_DIV_2 << RK3568_PHYREG6_PLL_DIV_SHIFT, + RK3568_PHYREG6); =20 - writel(PHYREG18_PLL_LOOP, priv->mmio + PHYREG18); - writel(PHYREG11_SU_TRIM_0_7, priv->mmio + PHYREG11); + writel(RK3568_PHYREG18_PLL_LOOP, priv->mmio + RK3568_PHYREG18); + writel(RK3568_PHYREG11_SU_TRIM_0_7, priv->mmio + RK3568_PHYREG11); =20 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_sel_usb, true); rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false= ); @@ -608,16 +611,16 @@ static int rk3568_combphy_cfg(struct rockchip_combphy= _priv *priv) =20 case PHY_TYPE_SATA: /* Enable adaptive CTLE for SATA Rx. */ - val =3D readl(priv->mmio + PHYREG15); - val |=3D PHYREG15_CTLE_EN; - writel(val, priv->mmio + PHYREG15); + val =3D readl(priv->mmio + RK3568_PHYREG15); + val |=3D RK3568_PHYREG15_CTLE_EN; + writel(val, priv->mmio + RK3568_PHYREG15); /* * Set tx_rterm=3D50ohm and rx_rterm=3D44ohm for SATA. * 0: 60ohm, 8: 50ohm 15: 44ohm (by step abort 1ohm) */ - val =3D PHYREG7_TX_RTERM_50OHM << PHYREG7_TX_RTERM_SHIFT; - val |=3D PHYREG7_RX_RTERM_44OHM << PHYREG7_RX_RTERM_SHIFT; - writel(val, priv->mmio + PHYREG7); + val =3D RK3568_PHYREG7_TX_RTERM_50OHM << RK3568_PHYREG7_TX_RTERM_SHIFT; + val |=3D RK3568_PHYREG7_RX_RTERM_44OHM << RK3568_PHYREG7_RX_RTERM_SHIFT; + writel(val, priv->mmio + RK3568_PHYREG7); =20 rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_sata, true); rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_sata, true); @@ -652,11 +655,11 @@ static int rk3568_combphy_cfg(struct rockchip_combphy= _priv *priv) case REF_CLOCK_24MHz: if (priv->type =3D=3D PHY_TYPE_USB3 || priv->type =3D=3D PHY_TYPE_SATA) { /* Set ssc_cnt[9:0]=3D0101111101 & 31.5KHz. */ - val =3D PHYREG15_SSC_CNT_VALUE << PHYREG15_SSC_CNT_SHIFT; - rockchip_combphy_updatel(priv, PHYREG15_SSC_CNT_MASK, - val, PHYREG15); + val =3D RK3568_PHYREG15_SSC_CNT_VALUE << RK3568_PHYREG15_SSC_CNT_SHIFT; + rockchip_combphy_updatel(priv, RK3568_PHYREG15_SSC_CNT_MASK, + val, RK3568_PHYREG15); =20 - writel(PHYREG16_SSC_CNT_VALUE, priv->mmio + PHYREG16); + writel(RK3568_PHYREG16_SSC_CNT_VALUE, priv->mmio + RK3568_PHYREG16); } break; =20 @@ -668,24 +671,26 @@ static int rk3568_combphy_cfg(struct rockchip_combphy= _priv *priv) rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_100m, true); if (priv->type =3D=3D PHY_TYPE_PCIE) { /* PLL KVCO fine tuning. */ - val =3D PHYREG33_PLL_KVCO_VALUE << PHYREG33_PLL_KVCO_SHIFT; - rockchip_combphy_updatel(priv, PHYREG33_PLL_KVCO_MASK, - val, PHYREG33); + val =3D RK3568_PHYREG33_PLL_KVCO_VALUE << RK3568_PHYREG33_PLL_KVCO_SHIF= T; + rockchip_combphy_updatel(priv, RK3568_PHYREG33_PLL_KVCO_MASK, + val, RK3568_PHYREG33); =20 /* Enable controlling random jitter. */ - writel(PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + PHYREG12); + writel(RK3568_PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + RK3568_PHYREG12); =20 - val =3D PHYREG6_PLL_DIV_2 << PHYREG6_PLL_DIV_SHIFT; - rockchip_combphy_updatel(priv, PHYREG6_PLL_DIV_MASK, - val, PHYREG6); + val =3D RK3568_PHYREG6_PLL_DIV_2 << RK3568_PHYREG6_PLL_DIV_SHIFT; + rockchip_combphy_updatel(priv, RK3568_PHYREG6_PLL_DIV_MASK, + val, RK3568_PHYREG6); =20 - writel(PHYREG18_PLL_LOOP, priv->mmio + PHYREG18); - writel(PHYREG11_SU_TRIM_0_7, priv->mmio + PHYREG11); + writel(RK3568_PHYREG18_PLL_LOOP, priv->mmio + RK3568_PHYREG18); + writel(RK3568_PHYREG11_SU_TRIM_0_7, priv->mmio + RK3568_PHYREG11); } else if (priv->type =3D=3D PHY_TYPE_SATA) { /* downward spread spectrum +500ppm */ - val =3D PHYREG32_SSC_DOWNWARD << PHYREG32_SSC_DIR_SHIFT; - val |=3D PHYREG32_SSC_OFFSET_500PPM << PHYREG32_SSC_OFFSET_SHIFT; - rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK, val, PHYREG32); + val =3D RK3568_PHYREG32_SSC_DOWNWARD << RK3568_PHYREG32_SSC_DIR_SHIFT; + val |=3D RK3568_PHYREG32_SSC_OFFSET_500PPM << + RK3568_PHYREG32_SSC_OFFSET_SHIFT; + rockchip_combphy_updatel(priv, RK3568_PHYREG32_SSC_MASK, val, + RK3568_PHYREG32); } break; =20 @@ -697,20 +702,21 @@ static int rk3568_combphy_cfg(struct rockchip_combphy= _priv *priv) if (priv->ext_refclk) { rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_ext, true); if (priv->type =3D=3D PHY_TYPE_PCIE && rate =3D=3D REF_CLOCK_100MHz) { - val =3D PHYREG13_RESISTER_HIGH_Z << PHYREG13_RESISTER_SHIFT; - val |=3D PHYREG13_CKRCV_AMP0; - rockchip_combphy_updatel(priv, PHYREG13_RESISTER_MASK, val, PHYREG13); - - val =3D readl(priv->mmio + PHYREG14); - val |=3D PHYREG14_CKRCV_AMP1; - writel(val, priv->mmio + PHYREG14); + val =3D RK3568_PHYREG13_RESISTER_HIGH_Z << RK3568_PHYREG13_RESISTER_SHI= FT; + val |=3D RK3568_PHYREG13_CKRCV_AMP0; + rockchip_combphy_updatel(priv, RK3568_PHYREG13_RESISTER_MASK, val, + RK3568_PHYREG13); + + val =3D readl(priv->mmio + RK3568_PHYREG14); + val |=3D RK3568_PHYREG14_CKRCV_AMP1; + writel(val, priv->mmio + RK3568_PHYREG14); } } =20 if (priv->enable_ssc) { - val =3D readl(priv->mmio + PHYREG8); - val |=3D PHYREG8_SSC_EN; - writel(val, priv->mmio + PHYREG8); + val =3D readl(priv->mmio + RK3568_PHYREG8); + val |=3D RK3568_PHYREG8_SSC_EN; + writel(val, priv->mmio + RK3568_PHYREG8); } =20 return 0; @@ -771,8 +777,8 @@ static int rk3576_combphy_cfg(struct rockchip_combphy_p= riv *priv) switch (priv->type) { case PHY_TYPE_PCIE: /* Set SSC downward spread spectrum */ - val =3D FIELD_PREP(PHYREG32_SSC_MASK, PHYREG32_SSC_DOWNWARD); - rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK, val, PHYREG32); + val =3D FIELD_PREP(RK3568_PHYREG32_SSC_MASK, RK3568_PHYREG32_SSC_DOWNWAR= D); + rockchip_combphy_updatel(priv, RK3568_PHYREG32_SSC_MASK, val, RK3568_PHY= REG32); =20 rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_pcie, true); rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_pcie, true); @@ -782,32 +788,33 @@ static int rk3576_combphy_cfg(struct rockchip_combphy= _priv *priv) =20 case PHY_TYPE_USB3: /* Set SSC downward spread spectrum */ - val =3D FIELD_PREP(PHYREG32_SSC_MASK, PHYREG32_SSC_DOWNWARD); - rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK, val, PHYREG32); + val =3D FIELD_PREP(RK3568_PHYREG32_SSC_MASK, RK3568_PHYREG32_SSC_DOWNWAR= D); + rockchip_combphy_updatel(priv, RK3568_PHYREG32_SSC_MASK, val, RK3568_PHY= REG32); =20 /* Enable adaptive CTLE for USB3.0 Rx */ - val =3D readl(priv->mmio + PHYREG15); - val |=3D PHYREG15_CTLE_EN; - writel(val, priv->mmio + PHYREG15); + val =3D readl(priv->mmio + RK3568_PHYREG15); + val |=3D RK3568_PHYREG15_CTLE_EN; + writel(val, priv->mmio + RK3568_PHYREG15); =20 /* Set PLL KVCO fine tuning signals */ - rockchip_combphy_updatel(priv, PHYREG33_PLL_KVCO_MASK, BIT(3), PHYREG33); + rockchip_combphy_updatel(priv, RK3568_PHYREG33_PLL_KVCO_MASK, BIT(3), + RK3568_PHYREG33); =20 /* Set PLL LPF R1 to su_trim[10:7]=3D1001 */ - writel(PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + PHYREG12); + writel(RK3568_PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + RK3568_PHYREG12); =20 /* Set PLL input clock divider 1/2 */ - val =3D FIELD_PREP(PHYREG6_PLL_DIV_MASK, PHYREG6_PLL_DIV_2); - rockchip_combphy_updatel(priv, PHYREG6_PLL_DIV_MASK, val, PHYREG6); + val =3D FIELD_PREP(RK3568_PHYREG6_PLL_DIV_MASK, RK3568_PHYREG6_PLL_DIV_2= ); + rockchip_combphy_updatel(priv, RK3568_PHYREG6_PLL_DIV_MASK, val, RK3568_= PHYREG6); =20 /* Set PLL loop divider */ - writel(PHYREG18_PLL_LOOP, priv->mmio + PHYREG18); + writel(RK3568_PHYREG18_PLL_LOOP, priv->mmio + RK3568_PHYREG18); =20 /* Set PLL KVCO to min and set PLL charge pump current to max */ - writel(PHYREG11_SU_TRIM_0_7, priv->mmio + PHYREG11); + writel(RK3568_PHYREG11_SU_TRIM_0_7, priv->mmio + RK3568_PHYREG11); =20 /* Set Rx squelch input filler bandwidth */ - writel(PHYREG21_RX_SQUELCH_VAL, priv->mmio + PHYREG21); + writel(RK3576_PHYREG21_RX_SQUELCH_VAL, priv->mmio + RK3576_PHYREG21); =20 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false= ); rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false= ); @@ -816,14 +823,14 @@ static int rk3576_combphy_cfg(struct rockchip_combphy= _priv *priv) =20 case PHY_TYPE_SATA: /* Enable adaptive CTLE for SATA Rx */ - val =3D readl(priv->mmio + PHYREG15); - val |=3D PHYREG15_CTLE_EN; - writel(val, priv->mmio + PHYREG15); + val =3D readl(priv->mmio + RK3568_PHYREG15); + val |=3D RK3568_PHYREG15_CTLE_EN; + writel(val, priv->mmio + RK3568_PHYREG15); =20 /* Set tx_rterm =3D 50 ohm and rx_rterm =3D 43.5 ohm */ - val =3D PHYREG7_TX_RTERM_50OHM << PHYREG7_TX_RTERM_SHIFT; - val |=3D PHYREG7_RX_RTERM_44OHM << PHYREG7_RX_RTERM_SHIFT; - writel(val, priv->mmio + PHYREG7); + val =3D RK3568_PHYREG7_TX_RTERM_50OHM << RK3568_PHYREG7_TX_RTERM_SHIFT; + val |=3D RK3568_PHYREG7_RX_RTERM_44OHM << RK3568_PHYREG7_RX_RTERM_SHIFT; + writel(val, priv->mmio + RK3568_PHYREG7); =20 rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_sata, true); rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_sata, true); @@ -845,19 +852,21 @@ static int rk3576_combphy_cfg(struct rockchip_combphy= _priv *priv) rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_24m, true); if (priv->type =3D=3D PHY_TYPE_USB3 || priv->type =3D=3D PHY_TYPE_SATA) { /* Set ssc_cnt[9:0]=3D0101111101 & 31.5KHz */ - val =3D FIELD_PREP(PHYREG15_SSC_CNT_MASK, PHYREG15_SSC_CNT_VALUE); - rockchip_combphy_updatel(priv, PHYREG15_SSC_CNT_MASK, - val, PHYREG15); + val =3D FIELD_PREP(RK3568_PHYREG15_SSC_CNT_MASK, + RK3568_PHYREG15_SSC_CNT_VALUE); + rockchip_combphy_updatel(priv, RK3568_PHYREG15_SSC_CNT_MASK, + val, RK3568_PHYREG15); =20 - writel(PHYREG16_SSC_CNT_VALUE, priv->mmio + PHYREG16); + writel(RK3568_PHYREG16_SSC_CNT_VALUE, priv->mmio + RK3568_PHYREG16); } else if (priv->type =3D=3D PHY_TYPE_PCIE) { /* PLL KVCO tuning fine */ - val =3D FIELD_PREP(PHYREG33_PLL_KVCO_MASK, PHYREG33_PLL_KVCO_VALUE_RK35= 76); - rockchip_combphy_updatel(priv, PHYREG33_PLL_KVCO_MASK, - val, PHYREG33); + val =3D FIELD_PREP(RK3568_PHYREG33_PLL_KVCO_MASK, + RK3576_PHYREG33_PLL_KVCO_VALUE); + rockchip_combphy_updatel(priv, RK3568_PHYREG33_PLL_KVCO_MASK, + val, RK3568_PHYREG33); =20 /* Set up rx_pck invert and rx msb to disable */ - writel(0x00, priv->mmio + PHYREG27); + writel(0x00, priv->mmio + RK3588_PHYREG27); =20 /* * Set up SU adjust signal: @@ -865,11 +874,11 @@ static int rk3576_combphy_cfg(struct rockchip_combphy= _priv *priv) * su_trim[15:8], PLL LPF R1 adujst bits[9:7]=3D3'b011 * su_trim[31:24], CKDRV adjust */ - writel(0x90, priv->mmio + PHYREG11); - writel(0x02, priv->mmio + PHYREG12); - writel(0x57, priv->mmio + PHYREG14); + writel(0x90, priv->mmio + RK3568_PHYREG11); + writel(0x02, priv->mmio + RK3568_PHYREG12); + writel(0x57, priv->mmio + RK3568_PHYREG14); =20 - writel(PHYREG16_SSC_CNT_VALUE, priv->mmio + PHYREG16); + writel(RK3568_PHYREG16_SSC_CNT_VALUE, priv->mmio + RK3568_PHYREG16); } break; =20 @@ -881,15 +890,16 @@ static int rk3576_combphy_cfg(struct rockchip_combphy= _priv *priv) rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_100m, true); if (priv->type =3D=3D PHY_TYPE_PCIE) { /* gate_tx_pck_sel length select work for L1SS */ - writel(0xc0, priv->mmio + PHYREG30); + writel(0xc0, priv->mmio + RK3576_PHYREG30); =20 /* PLL KVCO tuning fine */ - val =3D FIELD_PREP(PHYREG33_PLL_KVCO_MASK, PHYREG33_PLL_KVCO_VALUE_RK35= 76); - rockchip_combphy_updatel(priv, PHYREG33_PLL_KVCO_MASK, - val, PHYREG33); + val =3D FIELD_PREP(RK3568_PHYREG33_PLL_KVCO_MASK, + RK3576_PHYREG33_PLL_KVCO_VALUE); + rockchip_combphy_updatel(priv, RK3568_PHYREG33_PLL_KVCO_MASK, + val, RK3568_PHYREG33); =20 /* Set up rx_trim: PLL LPF C1 85pf R1 1.25kohm */ - writel(0x4c, priv->mmio + PHYREG27); + writel(0x4c, priv->mmio + RK3588_PHYREG27); =20 /* * Set up SU adjust signal: @@ -899,20 +909,23 @@ static int rk3576_combphy_cfg(struct rockchip_combphy= _priv *priv) * su_trim[23:16], CKRCV adjust * su_trim[31:24], CKDRV adjust */ - writel(0x90, priv->mmio + PHYREG11); - writel(0x43, priv->mmio + PHYREG12); - writel(0x88, priv->mmio + PHYREG13); - writel(0x56, priv->mmio + PHYREG14); + writel(0x90, priv->mmio + RK3568_PHYREG11); + writel(0x43, priv->mmio + RK3568_PHYREG12); + writel(0x88, priv->mmio + RK3568_PHYREG13); + writel(0x56, priv->mmio + RK3568_PHYREG14); } else if (priv->type =3D=3D PHY_TYPE_SATA) { /* downward spread spectrum +500ppm */ - val =3D FIELD_PREP(PHYREG32_SSC_DIR_MASK, PHYREG32_SSC_DOWNWARD); - val |=3D FIELD_PREP(PHYREG32_SSC_OFFSET_MASK, PHYREG32_SSC_OFFSET_500PP= M); - rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK, val, PHYREG32); + val =3D FIELD_PREP(RK3568_PHYREG32_SSC_DIR_MASK, + RK3568_PHYREG32_SSC_DOWNWARD); + val |=3D FIELD_PREP(RK3568_PHYREG32_SSC_OFFSET_MASK, + RK3568_PHYREG32_SSC_OFFSET_500PPM); + rockchip_combphy_updatel(priv, RK3568_PHYREG32_SSC_MASK, val, + RK3568_PHYREG32); =20 /* ssc ppm adjust to 3500ppm */ - rockchip_combphy_updatel(priv, PHYREG10_SSC_PCM_MASK, - PHYREG10_SSC_PCM_3500PPM, - PHYREG10); + rockchip_combphy_updatel(priv, RK3576_PHYREG10_SSC_PCM_MASK, + RK3576_PHYREG10_SSC_PCM_3500PPM, + RK3576_PHYREG10); } break; =20 @@ -924,12 +937,13 @@ static int rk3576_combphy_cfg(struct rockchip_combphy= _priv *priv) if (priv->ext_refclk) { rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_ext, true); if (priv->type =3D=3D PHY_TYPE_PCIE && rate =3D=3D REF_CLOCK_100MHz) { - val =3D FIELD_PREP(PHYREG33_PLL_KVCO_MASK, PHYREG33_PLL_KVCO_VALUE_RK35= 76); - rockchip_combphy_updatel(priv, PHYREG33_PLL_KVCO_MASK, - val, PHYREG33); + val =3D FIELD_PREP(RK3568_PHYREG33_PLL_KVCO_MASK, + RK3576_PHYREG33_PLL_KVCO_VALUE); + rockchip_combphy_updatel(priv, RK3568_PHYREG33_PLL_KVCO_MASK, + val, RK3568_PHYREG33); =20 /* Set up rx_trim: PLL LPF C1 85pf R1 2.5kohm */ - writel(0x0c, priv->mmio + PHYREG27); + writel(0x0c, priv->mmio + RK3588_PHYREG27); =20 /* * Set up SU adjust signal: @@ -939,25 +953,25 @@ static int rk3576_combphy_cfg(struct rockchip_combphy= _priv *priv) * su_trim[23:16], CKRCV adjust * su_trim[31:24], CKDRV adjust */ - writel(0x90, priv->mmio + PHYREG11); - writel(0x43, priv->mmio + PHYREG12); - writel(0x88, priv->mmio + PHYREG13); - writel(0x56, priv->mmio + PHYREG14); + writel(0x90, priv->mmio + RK3568_PHYREG11); + writel(0x43, priv->mmio + RK3568_PHYREG12); + writel(0x88, priv->mmio + RK3568_PHYREG13); + writel(0x56, priv->mmio + RK3568_PHYREG14); } } =20 if (priv->enable_ssc) { - val =3D readl(priv->mmio + PHYREG8); - val |=3D PHYREG8_SSC_EN; - writel(val, priv->mmio + PHYREG8); + val =3D readl(priv->mmio + RK3568_PHYREG8); + val |=3D RK3568_PHYREG8_SSC_EN; + writel(val, priv->mmio + RK3568_PHYREG8); =20 if (priv->type =3D=3D PHY_TYPE_PCIE && rate =3D=3D REF_CLOCK_24MHz) { /* Set PLL loop divider */ - writel(0x00, priv->mmio + PHYREG17); - writel(PHYREG18_PLL_LOOP, priv->mmio + PHYREG18); + writel(0x00, priv->mmio + RK3576_PHYREG17); + writel(RK3568_PHYREG18_PLL_LOOP, priv->mmio + RK3568_PHYREG18); =20 /* Set up rx_pck invert and rx msb to disable */ - writel(0x00, priv->mmio + PHYREG27); + writel(0x00, priv->mmio + RK3588_PHYREG27); =20 /* * Set up SU adjust signal: @@ -966,16 +980,17 @@ static int rk3576_combphy_cfg(struct rockchip_combphy= _priv *priv) * su_trim[23:16], CKRCV adjust * su_trim[31:24], CKDRV adjust */ - writel(0x90, priv->mmio + PHYREG11); - writel(0x02, priv->mmio + PHYREG12); - writel(0x08, priv->mmio + PHYREG13); - writel(0x57, priv->mmio + PHYREG14); - writel(0x40, priv->mmio + PHYREG15); + writel(0x90, priv->mmio + RK3568_PHYREG11); + writel(0x02, priv->mmio + RK3568_PHYREG12); + writel(0x08, priv->mmio + RK3568_PHYREG13); + writel(0x57, priv->mmio + RK3568_PHYREG14); + writel(0x40, priv->mmio + RK3568_PHYREG15); =20 - writel(PHYREG16_SSC_CNT_VALUE, priv->mmio + PHYREG16); + writel(RK3568_PHYREG16_SSC_CNT_VALUE, priv->mmio + RK3568_PHYREG16); =20 - val =3D FIELD_PREP(PHYREG33_PLL_KVCO_MASK, PHYREG33_PLL_KVCO_VALUE_RK35= 76); - writel(val, priv->mmio + PHYREG33); + val =3D FIELD_PREP(RK3568_PHYREG33_PLL_KVCO_MASK, + RK3576_PHYREG33_PLL_KVCO_VALUE); + writel(val, priv->mmio + RK3568_PHYREG33); } } =20 @@ -1045,30 +1060,28 @@ static int rk3588_combphy_cfg(struct rockchip_combp= hy_priv *priv) break; case PHY_TYPE_USB3: /* Set SSC downward spread spectrum */ - rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK, - PHYREG32_SSC_DOWNWARD << PHYREG32_SSC_DIR_SHIFT, - PHYREG32); + val =3D RK3568_PHYREG32_SSC_DOWNWARD << RK3568_PHYREG32_SSC_DIR_SHIFT; + rockchip_combphy_updatel(priv, RK3568_PHYREG32_SSC_MASK, val, RK3568_PHY= REG32); =20 /* Enable adaptive CTLE for USB3.0 Rx. */ - val =3D readl(priv->mmio + PHYREG15); - val |=3D PHYREG15_CTLE_EN; - writel(val, priv->mmio + PHYREG15); + val =3D readl(priv->mmio + RK3568_PHYREG15); + val |=3D RK3568_PHYREG15_CTLE_EN; + writel(val, priv->mmio + RK3568_PHYREG15); =20 /* Set PLL KVCO fine tuning signals. */ - rockchip_combphy_updatel(priv, PHYREG33_PLL_KVCO_MASK, - PHYREG33_PLL_KVCO_VALUE << PHYREG33_PLL_KVCO_SHIFT, - PHYREG33); + val =3D RK3568_PHYREG33_PLL_KVCO_VALUE << RK3568_PHYREG33_PLL_KVCO_SHIFT, + rockchip_combphy_updatel(priv, RK3568_PHYREG33_PLL_KVCO_MASK, val, RK356= 8_PHYREG33); =20 /* Enable controlling random jitter. */ - writel(PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + PHYREG12); + writel(RK3568_PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + RK3568_PHYREG12); =20 /* Set PLL input clock divider 1/2. */ - rockchip_combphy_updatel(priv, PHYREG6_PLL_DIV_MASK, - PHYREG6_PLL_DIV_2 << PHYREG6_PLL_DIV_SHIFT, - PHYREG6); + rockchip_combphy_updatel(priv, RK3568_PHYREG6_PLL_DIV_MASK, + RK3568_PHYREG6_PLL_DIV_2 << RK3568_PHYREG6_PLL_DIV_SHIFT, + RK3568_PHYREG6); =20 - writel(PHYREG18_PLL_LOOP, priv->mmio + PHYREG18); - writel(PHYREG11_SU_TRIM_0_7, priv->mmio + PHYREG11); + writel(RK3568_PHYREG18_PLL_LOOP, priv->mmio + RK3568_PHYREG18); + writel(RK3568_PHYREG11_SU_TRIM_0_7, priv->mmio + RK3568_PHYREG11); =20 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false= ); rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false= ); @@ -1076,16 +1089,16 @@ static int rk3588_combphy_cfg(struct rockchip_combp= hy_priv *priv) break; case PHY_TYPE_SATA: /* Enable adaptive CTLE for SATA Rx. */ - val =3D readl(priv->mmio + PHYREG15); - val |=3D PHYREG15_CTLE_EN; - writel(val, priv->mmio + PHYREG15); + val =3D readl(priv->mmio + RK3568_PHYREG15); + val |=3D RK3568_PHYREG15_CTLE_EN; + writel(val, priv->mmio + RK3568_PHYREG15); /* * Set tx_rterm=3D50ohm and rx_rterm=3D44ohm for SATA. * 0: 60ohm, 8: 50ohm 15: 44ohm (by step abort 1ohm) */ - val =3D PHYREG7_TX_RTERM_50OHM << PHYREG7_TX_RTERM_SHIFT; - val |=3D PHYREG7_RX_RTERM_44OHM << PHYREG7_RX_RTERM_SHIFT; - writel(val, priv->mmio + PHYREG7); + val =3D RK3568_PHYREG7_TX_RTERM_50OHM << RK3568_PHYREG7_TX_RTERM_SHIFT; + val |=3D RK3568_PHYREG7_RX_RTERM_44OHM << RK3568_PHYREG7_RX_RTERM_SHIFT; + writel(val, priv->mmio + RK3568_PHYREG7); =20 rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_sata, true); rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_sata, true); @@ -1107,11 +1120,11 @@ static int rk3588_combphy_cfg(struct rockchip_combp= hy_priv *priv) case REF_CLOCK_24MHz: if (priv->type =3D=3D PHY_TYPE_USB3 || priv->type =3D=3D PHY_TYPE_SATA) { /* Set ssc_cnt[9:0]=3D0101111101 & 31.5KHz. */ - val =3D PHYREG15_SSC_CNT_VALUE << PHYREG15_SSC_CNT_SHIFT; - rockchip_combphy_updatel(priv, PHYREG15_SSC_CNT_MASK, - val, PHYREG15); + val =3D RK3568_PHYREG15_SSC_CNT_VALUE << RK3568_PHYREG15_SSC_CNT_SHIFT; + rockchip_combphy_updatel(priv, RK3568_PHYREG15_SSC_CNT_MASK, + val, RK3568_PHYREG15); =20 - writel(PHYREG16_SSC_CNT_VALUE, priv->mmio + PHYREG16); + writel(RK3568_PHYREG16_SSC_CNT_VALUE, priv->mmio + RK3568_PHYREG16); } break; =20 @@ -1122,23 +1135,25 @@ static int rk3588_combphy_cfg(struct rockchip_combp= hy_priv *priv) rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_100m, true); if (priv->type =3D=3D PHY_TYPE_PCIE) { /* PLL KVCO fine tuning. */ - val =3D 4 << PHYREG33_PLL_KVCO_SHIFT; - rockchip_combphy_updatel(priv, PHYREG33_PLL_KVCO_MASK, - val, PHYREG33); + val =3D 4 << RK3568_PHYREG33_PLL_KVCO_SHIFT; + rockchip_combphy_updatel(priv, RK3568_PHYREG33_PLL_KVCO_MASK, + val, RK3568_PHYREG33); =20 /* Enable controlling random jitter. */ - writel(PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + PHYREG12); + writel(RK3568_PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + RK3568_PHYREG12); =20 /* Set up rx_trim: PLL LPF C1 85pf R1 1.25kohm */ - writel(PHYREG27_RX_TRIM_RK3588, priv->mmio + PHYREG27); + writel(RK3588_PHYREG27_RX_TRIM, priv->mmio + RK3588_PHYREG27); =20 /* Set up su_trim: */ - writel(PHYREG11_SU_TRIM_0_7, priv->mmio + PHYREG11); + writel(RK3568_PHYREG11_SU_TRIM_0_7, priv->mmio + RK3568_PHYREG11); } else if (priv->type =3D=3D PHY_TYPE_SATA) { /* downward spread spectrum +500ppm */ - val =3D PHYREG32_SSC_DOWNWARD << PHYREG32_SSC_DIR_SHIFT; - val |=3D PHYREG32_SSC_OFFSET_500PPM << PHYREG32_SSC_OFFSET_SHIFT; - rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK, val, PHYREG32); + val =3D RK3568_PHYREG32_SSC_DOWNWARD << RK3568_PHYREG32_SSC_DIR_SHIFT; + val |=3D RK3568_PHYREG32_SSC_OFFSET_500PPM << + RK3568_PHYREG32_SSC_OFFSET_SHIFT; + rockchip_combphy_updatel(priv, RK3568_PHYREG32_SSC_MASK, val, + RK3568_PHYREG32); } break; default: @@ -1149,20 +1164,21 @@ static int rk3588_combphy_cfg(struct rockchip_combp= hy_priv *priv) if (priv->ext_refclk) { rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_ext, true); if (priv->type =3D=3D PHY_TYPE_PCIE && rate =3D=3D REF_CLOCK_100MHz) { - val =3D PHYREG13_RESISTER_HIGH_Z << PHYREG13_RESISTER_SHIFT; - val |=3D PHYREG13_CKRCV_AMP0; - rockchip_combphy_updatel(priv, PHYREG13_RESISTER_MASK, val, PHYREG13); - - val =3D readl(priv->mmio + PHYREG14); - val |=3D PHYREG14_CKRCV_AMP1; - writel(val, priv->mmio + PHYREG14); + val =3D RK3568_PHYREG13_RESISTER_HIGH_Z << RK3568_PHYREG13_RESISTER_SHI= FT; + val |=3D RK3568_PHYREG13_CKRCV_AMP0; + rockchip_combphy_updatel(priv, RK3568_PHYREG13_RESISTER_MASK, val, + RK3568_PHYREG13); + + val =3D readl(priv->mmio + RK3568_PHYREG14); + val |=3D RK3568_PHYREG14_CKRCV_AMP1; + writel(val, priv->mmio + RK3568_PHYREG14); } } =20 if (priv->enable_ssc) { - val =3D readl(priv->mmio + PHYREG8); - val |=3D PHYREG8_SSC_EN; - writel(val, priv->mmio + PHYREG8); + val =3D readl(priv->mmio + RK3568_PHYREG8); + val |=3D RK3568_PHYREG8_SSC_EN; + writel(val, priv->mmio + RK3568_PHYREG8); } =20 return 0; --=20 2.50.1 From nobody Sun Oct 5 23:42:37 2025 Received: from layka.disroot.org (layka.disroot.org [178.21.23.139]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4C8C124676A; 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charset="utf-8" Rockchip RK3528 integrates one naneng-combphy that is able to operate in PCIe and USB3 mode. The control logic is similar to previous variants of naneng-combphy but the register layout is apperantly different from the RK3568 one. Signed-off-by: Yao Zi Reviewed-by: Heiko Stuebner Reviewed-by: Neil Armstrong --- .../rockchip/phy-rockchip-naneng-combphy.c | 189 +++++++++++++++++- 1 file changed, 188 insertions(+), 1 deletion(-) diff --git a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c b/drivers/p= hy/rockchip/phy-rockchip-naneng-combphy.c index ce84166cd772..0d25872e6712 100644 --- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c +++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c @@ -20,7 +20,46 @@ #define REF_CLOCK_25MHz (25 * HZ_PER_MHZ) #define REF_CLOCK_100MHz (100 * HZ_PER_MHZ) =20 -/* COMBO PHY REG */ +/* RK3528 COMBO PHY REG */ +#define RK3528_PHYREG6 0x18 +#define RK3528_PHYREG6_PLL_KVCO GENMASK(12, 10) +#define RK3528_PHYREG6_PLL_KVCO_VALUE 0x2 +#define RK3528_PHYREG6_SSC_DIR GENMASK(5, 4) +#define RK3528_PHYREG6_SSC_UPWARD 0 +#define RK3528_PHYREG6_SSC_DOWNWARD 1 + +#define RK3528_PHYREG40 0x100 +#define RK3528_PHYREG40_SSC_EN BIT(20) +#define RK3528_PHYREG40_SSC_CNT GENMASK(10, 0) +#define RK3528_PHYREG40_SSC_CNT_VALUE 0x17d + +#define RK3528_PHYREG42 0x108 +#define RK3528_PHYREG42_CKDRV_CLK_SEL BIT(29) +#define RK3528_PHYREG42_CKDRV_CLK_PLL 0 +#define RK3528_PHYREG42_CKDRV_CLK_CKRCV 1 +#define RK3528_PHYREG42_PLL_LPF_R1_ADJ GENMASK(10, 7) +#define RK3528_PHYREG42_PLL_LPF_R1_ADJ_VALUE 0x9 +#define RK3528_PHYREG42_PLL_CHGPUMP_CUR_ADJ GENMASK(6, 4) +#define RK3528_PHYREG42_PLL_CHGPUMP_CUR_ADJ_VALUE 0x7 +#define RK3528_PHYREG42_PLL_KVCO_ADJ GENMASK(2, 0) +#define RK3528_PHYREG42_PLL_KVCO_ADJ_VALUE 0x0 + +#define RK3528_PHYREG80 0x200 +#define RK3528_PHYREG80_CTLE_EN BIT(17) + +#define RK3528_PHYREG81 0x204 +#define RK3528_PHYREG81_CDR_PHASE_PATH_GAIN_2X BIT(5) +#define RK3528_PHYREG81_SLEW_RATE_CTRL GENMASK(2, 0) +#define RK3528_PHYREG81_SLEW_RATE_CTRL_SLOW 0x7 + +#define RK3528_PHYREG83 0x20c +#define RK3528_PHYREG83_RX_SQUELCH GENMASK(2, 0) +#define RK3528_PHYREG83_RX_SQUELCH_VALUE 0x6 + +#define RK3528_PHYREG86 0x218 +#define RK3528_PHYREG86_RTERM_DET_CLK_EN BIT(14) + +/* RK3568 COMBO PHY REG */ #define RK3568_PHYREG6 0x14 #define RK3568_PHYREG6_PLL_DIV_MASK GENMASK(7, 6) #define RK3568_PHYREG6_PLL_DIV_SHIFT 6 @@ -400,6 +439,150 @@ static int rockchip_combphy_probe(struct platform_dev= ice *pdev) return PTR_ERR_OR_ZERO(phy_provider); } =20 +static int rk3528_combphy_cfg(struct rockchip_combphy_priv *priv) +{ + const struct rockchip_combphy_grfcfg *cfg =3D priv->cfg->grfcfg; + unsigned long rate; + u32 val; + + /* Set SSC downward spread spectrum */ + val =3D FIELD_PREP(RK3528_PHYREG6_SSC_DIR, RK3528_PHYREG6_SSC_DOWNWARD); + rockchip_combphy_updatel(priv, RK3528_PHYREG6_SSC_DIR, val, RK3528_PHYREG= 6); + + switch (priv->type) { + case PHY_TYPE_PCIE: + rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_pcie, true); + rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_pcie, true); + rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_pcie, true); + rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_pcie, true); + break; + case PHY_TYPE_USB3: + /* Enable adaptive CTLE for USB3.0 Rx */ + rockchip_combphy_updatel(priv, RK3528_PHYREG80_CTLE_EN, RK3528_PHYREG80_= CTLE_EN, + RK3528_PHYREG80); + + /* Set slow slew rate control for PI */ + val =3D FIELD_PREP(RK3528_PHYREG81_SLEW_RATE_CTRL, + RK3528_PHYREG81_SLEW_RATE_CTRL_SLOW); + rockchip_combphy_updatel(priv, RK3528_PHYREG81_SLEW_RATE_CTRL, val, + RK3528_PHYREG81); + + /* Set CDR phase path with 2x gain */ + rockchip_combphy_updatel(priv, RK3528_PHYREG81_CDR_PHASE_PATH_GAIN_2X, + RK3528_PHYREG81_CDR_PHASE_PATH_GAIN_2X, RK3528_PHYREG81); + + /* Set Rx squelch input filler bandwidth */ + val =3D FIELD_PREP(RK3528_PHYREG83_RX_SQUELCH, RK3528_PHYREG83_RX_SQUELC= H_VALUE); + rockchip_combphy_updatel(priv, RK3528_PHYREG83_RX_SQUELCH, val, RK3528_P= HYREG83); + + rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false= ); + rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false= ); + rockchip_combphy_param_write(priv->phy_grf, &cfg->usb_mode_set, true); + rockchip_combphy_param_write(priv->pipe_grf, &cfg->u3otg0_port_en, true); + break; + default: + dev_err(priv->dev, "incompatible PHY type\n"); + return -EINVAL; + } + + rate =3D clk_get_rate(priv->refclk); + + switch (rate) { + case REF_CLOCK_24MHz: + rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_24m, true); + if (priv->type =3D=3D PHY_TYPE_USB3) { + /* Set ssc_cnt[10:0]=3D00101111101 & 31.5KHz */ + val =3D FIELD_PREP(RK3528_PHYREG40_SSC_CNT, RK3528_PHYREG40_SSC_CNT_VAL= UE); + rockchip_combphy_updatel(priv, RK3528_PHYREG40_SSC_CNT, val, + RK3528_PHYREG40); + } else if (priv->type =3D=3D PHY_TYPE_PCIE) { + /* tx_trim[14]=3D1, Enable the counting clock of the rterm detect */ + rockchip_combphy_updatel(priv, RK3528_PHYREG86_RTERM_DET_CLK_EN, + RK3528_PHYREG86_RTERM_DET_CLK_EN, RK3528_PHYREG86); + } + break; + case REF_CLOCK_100MHz: + rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_100m, true); + if (priv->type =3D=3D PHY_TYPE_PCIE) { + /* PLL KVCO tuning fine */ + val =3D FIELD_PREP(RK3528_PHYREG6_PLL_KVCO, RK3528_PHYREG6_PLL_KVCO_VAL= UE); + rockchip_combphy_updatel(priv, RK3528_PHYREG6_PLL_KVCO, val, + RK3528_PHYREG6); + + /* su_trim[6:4]=3D111, [10:7]=3D1001, [2:0]=3D000, swing 650mv */ + writel(0x570804f0, priv->mmio + RK3528_PHYREG42); + } + break; + default: + dev_err(priv->dev, "Unsupported rate: %lu\n", rate); + return -EINVAL; + } + + if (device_property_read_bool(priv->dev, "rockchip,ext-refclk")) { + rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_ext, true); + + if (priv->type =3D=3D PHY_TYPE_PCIE && rate =3D=3D REF_CLOCK_100MHz) { + val =3D FIELD_PREP(RK3528_PHYREG42_CKDRV_CLK_SEL, + RK3528_PHYREG42_CKDRV_CLK_CKRCV); + val |=3D FIELD_PREP(RK3528_PHYREG42_PLL_LPF_R1_ADJ, + RK3528_PHYREG42_PLL_LPF_R1_ADJ_VALUE); + val |=3D FIELD_PREP(RK3528_PHYREG42_PLL_CHGPUMP_CUR_ADJ, + RK3528_PHYREG42_PLL_CHGPUMP_CUR_ADJ_VALUE); + val |=3D FIELD_PREP(RK3528_PHYREG42_PLL_KVCO_ADJ, + RK3528_PHYREG42_PLL_KVCO_ADJ_VALUE); + rockchip_combphy_updatel(priv, + RK3528_PHYREG42_CKDRV_CLK_SEL | + RK3528_PHYREG42_PLL_LPF_R1_ADJ | + RK3528_PHYREG42_PLL_CHGPUMP_CUR_ADJ | + RK3528_PHYREG42_PLL_KVCO_ADJ, + val, RK3528_PHYREG42); + + val =3D FIELD_PREP(RK3528_PHYREG6_PLL_KVCO, RK3528_PHYREG6_PLL_KVCO_VAL= UE); + rockchip_combphy_updatel(priv, RK3528_PHYREG6_PLL_KVCO, val, + RK3528_PHYREG6); + } + } + + if (priv->type =3D=3D PHY_TYPE_PCIE) { + if (device_property_read_bool(priv->dev, "rockchip,enable-ssc")) + rockchip_combphy_updatel(priv, RK3528_PHYREG40_SSC_EN, + RK3528_PHYREG40_SSC_EN, RK3528_PHYREG40); + } + + return 0; +} + +static const struct rockchip_combphy_grfcfg rk3528_combphy_grfcfgs =3D { + /* pipe-phy-grf */ + .pcie_mode_set =3D { 0x0000, 5, 0, 0x00, 0x11 }, + .usb_mode_set =3D { 0x0000, 5, 0, 0x00, 0x04 }, + .pipe_rxterm_set =3D { 0x0000, 12, 12, 0x00, 0x01 }, + .pipe_txelec_set =3D { 0x0004, 1, 1, 0x00, 0x01 }, + .pipe_txcomp_set =3D { 0x0004, 4, 4, 0x00, 0x01 }, + .pipe_clk_24m =3D { 0x0004, 14, 13, 0x00, 0x00 }, + .pipe_clk_100m =3D { 0x0004, 14, 13, 0x00, 0x02 }, + .pipe_rxterm_sel =3D { 0x0008, 8, 8, 0x00, 0x01 }, + .pipe_txelec_sel =3D { 0x0008, 12, 12, 0x00, 0x01 }, + .pipe_txcomp_sel =3D { 0x0008, 15, 15, 0x00, 0x01 }, + .pipe_clk_ext =3D { 0x000c, 9, 8, 0x02, 0x01 }, + .pipe_phy_status =3D { 0x0034, 6, 6, 0x01, 0x00 }, + .con0_for_pcie =3D { 0x0000, 15, 0, 0x00, 0x110 }, + .con1_for_pcie =3D { 0x0004, 15, 0, 0x00, 0x00 }, + .con2_for_pcie =3D { 0x0008, 15, 0, 0x00, 0x101 }, + .con3_for_pcie =3D { 0x000c, 15, 0, 0x00, 0x0200 }, + /* pipe-grf */ + .u3otg0_port_en =3D { 0x0044, 15, 0, 0x0181, 0x1100 }, +}; + +static const struct rockchip_combphy_cfg rk3528_combphy_cfgs =3D { + .num_phys =3D 1, + .phy_ids =3D { + 0xffdc0000, + }, + .grfcfg =3D &rk3528_combphy_grfcfgs, + .combphy_cfg =3D rk3528_combphy_cfg, +}; + static int rk3562_combphy_cfg(struct rockchip_combphy_priv *priv) { const struct rockchip_combphy_grfcfg *cfg =3D priv->cfg->grfcfg; @@ -1225,6 +1408,10 @@ static const struct rockchip_combphy_cfg rk3588_comb= phy_cfgs =3D { }; =20 static const struct of_device_id rockchip_combphy_of_match[] =3D { + { + .compatible =3D "rockchip,rk3528-naneng-combphy", + .data =3D &rk3528_combphy_cfgs, + }, { .compatible =3D "rockchip,rk3562-naneng-combphy", .data =3D &rk3562_combphy_cfgs, --=20 2.50.1 From nobody Sun Oct 5 23:42:37 2025 Received: from layka.disroot.org (layka.disroot.org [178.21.23.139]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D27DB213E89; Mon, 28 Jul 2025 10:32:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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dmarc=pass (p=reject dis=none) header.from=disroot.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=disroot.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b="P16oc+Lf" Received: from mail01.disroot.lan (localhost [127.0.0.1]) by disroot.org (Postfix) with ESMTP id 5337820E30; Mon, 28 Jul 2025 12:32:38 +0200 (CEST) X-Virus-Scanned: SPAM Filter at disroot.org Received: from layka.disroot.org ([127.0.0.1]) by localhost (disroot.org [127.0.0.1]) (amavis, port 10024) with ESMTP id wAhAAW0WYRYv; Mon, 28 Jul 2025 12:32:37 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=disroot.org; s=mail; t=1753698757; bh=y5vVdmQ4dC2wsUn0JtuEjMgsKW9qhleLEj6ifOgi1pk=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=P16oc+LfQNN+AmGnexdHMN9iGdC5bg5sWr5nbmaxSLEND69x5Th9IABXmJs9YUsNf 8rDETyRWThLtV+l8dS+0beo0trTlTS4awAnFgSgloPRsHFlVY+b1W5pHZgXd+D90jB Hwga1K1yef2QWIqvkEc+XE1Q4bDrAceyjl3wlRSi5slQwIDAGgEHmvDwzw6n4vLH0+ 06l+mtPyHY8qG/r+KatUsh/Z91zqAsJCpqXTLNruqMTx0xdSz7+76JVgP6jey9FcOX kJbQKSv8IfcDiVzTl06mFn+ugV4Fn22n6wKlaeAg+DKpbbyS9YGyaEUVZMx5/ZEY6w bxgNxUBc3l3gQ== From: Yao Zi To: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Yao Zi , Frank Wang , Andy Yan , Cristian Ciocaltea , Detlev Casanova , Shresth Prasad , Chukun Pan , Jonas Karlman Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 6/6] arm64: dts: rockchip: Add naneng-combphy for RK3528 Date: Mon, 28 Jul 2025 10:29:48 +0000 Message-ID: <20250728102947.38984-8-ziyao@disroot.org> In-Reply-To: <20250728102947.38984-2-ziyao@disroot.org> References: <20250728102947.38984-2-ziyao@disroot.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Rockchip RK3528 ships a naneng-combphy that is shared by PCIe and USB 3.0 controllers. Describe it and the pipe-phy grf which it depends on. Signed-off-by: Yao Zi --- arch/arm64/boot/dts/rockchip/rk3528.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3528.dtsi b/arch/arm64/boot/dts= /rockchip/rk3528.dtsi index 54fa8089c4d3..58c8977249be 100644 --- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi @@ -417,6 +417,11 @@ vpu_grf: syscon@ff340000 { reg =3D <0x0 0xff340000 0x0 0x8000>; }; =20 + pipe_phy_grf: syscon@ff348000 { + compatible =3D "rockchip,rk3528-pipe-phy-grf", "syscon"; + reg =3D <0x0 0xff348000 0x0 0x8000>; + }; + vo_grf: syscon@ff360000 { compatible =3D "rockchip,rk3528-vo-grf", "syscon"; reg =3D <0x0 0xff360000 0x0 0x10000>; @@ -1085,6 +1090,25 @@ dmac: dma-controller@ffd60000 { #dma-cells =3D <1>; arm,pl330-periph-burst; }; + + combphy: phy@ffdc0000 { + compatible =3D "rockchip,rk3528-naneng-combphy"; + reg =3D <0x0 0xffdc0000 0x0 0x10000>; + assigned-clocks =3D <&cru CLK_REF_PCIE_INNER_PHY>; + assigned-clock-rates =3D <100000000>; + clocks =3D <&cru CLK_REF_PCIE_INNER_PHY>, + <&cru PCLK_PCIE_PHY>, + <&cru PCLK_PIPE_GRF>; + clock-names =3D "ref", "apb", "pipe"; + power-domains =3D <&power RK3528_PD_VPU>; + resets =3D <&cru SRST_PCIE_PIPE_PHY>, + <&cru SRST_P_PCIE_PHY>; + reset-names =3D "phy", "apb"; + #phy-cells =3D <1>; + rockchip,pipe-grf =3D <&vpu_grf>; + rockchip,pipe-phy-grf =3D <&pipe_phy_grf>; + status =3D "disabled"; + }; }; }; =20 --=20 2.50.1