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Wysocki" , Mika Westerberg , Andy Shevchenko , Linus Walleij , Bartosz Golaszewski , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Cc: Palmer Dabbelt , Paul Walmsley , Alexandre Ghiti , Len Brown , Sunil V L , Rahul Pathak , Leyfoon Tan , Atish Patra , Andrew Jones , Samuel Holland , Anup Patel , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-acpi@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel Subject: [PATCH v9 10/24] clk: Add clock driver for the RISC-V RPMI clock service group Date: Mon, 28 Jul 2025 15:10:18 +0530 Message-ID: <20250728094032.63545-11-apatel@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250728094032.63545-1-apatel@ventanamicro.com> References: <20250728094032.63545-1-apatel@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Rahul Pathak The RPMI specification defines a clock service group which can be accessed via SBI MPXY extension or dedicated S-mode RPMI transport. Add mailbox client based clock driver for the RISC-V RPMI clock service group. Reviewed-by: Stephen Boyd Reviewed-by: Andy Shevchenko Co-developed-by: Anup Patel Signed-off-by: Anup Patel Signed-off-by: Rahul Pathak --- drivers/clk/Kconfig | 8 + drivers/clk/Makefile | 1 + drivers/clk/clk-rpmi.c | 616 +++++++++++++++++++++ include/linux/mailbox/riscv-rpmi-message.h | 16 + include/linux/wordpart.h | 8 + 5 files changed, 649 insertions(+) create mode 100644 drivers/clk/clk-rpmi.c diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index 19c1ed280fd7..2e385b146f8b 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -493,6 +493,14 @@ config COMMON_CLK_SP7021 Not all features of the PLL are currently supported by the driver. =20 +config COMMON_CLK_RPMI + tristate "Clock driver based on RISC-V RPMI" + depends on MAILBOX + default RISCV + help + Support for clocks based on the clock service group defined by + the RISC-V platform management interface (RPMI) specification. + source "drivers/clk/actions/Kconfig" source "drivers/clk/analogbits/Kconfig" source "drivers/clk/baikal-t1/Kconfig" diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 42867cd37c33..48866e429a40 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -84,6 +84,7 @@ obj-$(CONFIG_CLK_LS1028A_PLLDIG) +=3D clk-plldig.o obj-$(CONFIG_COMMON_CLK_PWM) +=3D clk-pwm.o obj-$(CONFIG_CLK_QORIQ) +=3D clk-qoriq.o obj-$(CONFIG_COMMON_CLK_RK808) +=3D clk-rk808.o +obj-$(CONFIG_COMMON_CLK_RPMI) +=3D clk-rpmi.o obj-$(CONFIG_COMMON_CLK_HI655X) +=3D clk-hi655x.o obj-$(CONFIG_COMMON_CLK_S2MPS11) +=3D clk-s2mps11.o obj-$(CONFIG_COMMON_CLK_SCMI) +=3D clk-scmi.o diff --git a/drivers/clk/clk-rpmi.c b/drivers/clk/clk-rpmi.c new file mode 100644 index 000000000000..e0a371586695 --- /dev/null +++ b/drivers/clk/clk-rpmi.c @@ -0,0 +1,616 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * RISC-V MPXY Based Clock Driver + * + * Copyright (C) 2025 Ventana Micro Systems Ltd. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define RPMI_CLK_DISCRETE_MAX_NUM_RATES 16 +#define RPMI_CLK_NAME_LEN 16 + +#define to_rpmi_clk(clk) container_of(clk, struct rpmi_clk, hw) + +#define rpmi_clkrate_u64(hi, lo) make_u64_from_two_u32(hi, lo) + +enum rpmi_clk_config { + RPMI_CLK_DISABLE =3D 0, + RPMI_CLK_ENABLE =3D 1, + RPMI_CLK_CONFIG_MAX_IDX +}; + +enum rpmi_clk_type { + RPMI_CLK_DISCRETE =3D 0, + RPMI_CLK_LINEAR =3D 1, + RPMI_CLK_TYPE_MAX_IDX +}; + +struct rpmi_clk_context { + struct device *dev; + struct mbox_chan *chan; + struct mbox_client client; + u32 max_msg_data_size; +}; + +/* + * rpmi_clk_rates represents the rates format + * as specified by the RPMI specification. + * No other data format (e.g., struct linear_range) + * is required to avoid to and from conversion. + */ +union rpmi_clk_rates { + u64 discrete[RPMI_CLK_DISCRETE_MAX_NUM_RATES]; + struct { + u64 min; + u64 max; + u64 step; + } linear; +}; + +struct rpmi_clk { + struct rpmi_clk_context *context; + u32 id; + u32 num_rates; + u32 transition_latency; + enum rpmi_clk_type type; + union rpmi_clk_rates *rates; + char name[RPMI_CLK_NAME_LEN]; + struct clk_hw hw; +}; + +struct rpmi_clk_rate_discrete { + __le32 lo; + __le32 hi; +}; + +struct rpmi_clk_rate_linear { + __le32 min_lo; + __le32 min_hi; + __le32 max_lo; + __le32 max_hi; + __le32 step_lo; + __le32 step_hi; +}; + +struct rpmi_get_num_clocks_rx { + __le32 status; + __le32 num_clocks; +}; + +struct rpmi_get_attrs_tx { + __le32 clkid; +}; + +struct rpmi_get_attrs_rx { + __le32 status; + __le32 flags; + __le32 num_rates; + __le32 transition_latency; + char name[RPMI_CLK_NAME_LEN]; +}; + +struct rpmi_get_supp_rates_tx { + __le32 clkid; + __le32 clk_rate_idx; +}; + +struct rpmi_get_supp_rates_rx { + __le32 status; + __le32 flags; + __le32 remaining; + __le32 returned; + __le32 rates[]; +}; + +struct rpmi_get_rate_tx { + __le32 clkid; +}; + +struct rpmi_get_rate_rx { + __le32 status; + __le32 lo; + __le32 hi; +}; + +struct rpmi_set_rate_tx { + __le32 clkid; + __le32 flags; + __le32 lo; + __le32 hi; +}; + +struct rpmi_set_rate_rx { + __le32 status; +}; + +struct rpmi_set_config_tx { + __le32 clkid; + __le32 config; +}; + +struct rpmi_set_config_rx { + __le32 status; +}; + +static u32 rpmi_clk_get_num_clocks(struct rpmi_clk_context *context) +{ + struct rpmi_get_num_clocks_rx rx, *resp; + struct rpmi_mbox_message msg; + int ret; + + rpmi_mbox_init_send_with_response(&msg, RPMI_CLK_SRV_GET_NUM_CLOCKS, + NULL, 0, &rx, sizeof(rx)); + + ret =3D rpmi_mbox_send_message(context->chan, &msg); + if (ret) + return 0; + + resp =3D rpmi_mbox_get_msg_response(&msg); + if (!resp || resp->status) + return 0; + + return le32_to_cpu(resp->num_clocks); +} + +static int rpmi_clk_get_attrs(u32 clkid, struct rpmi_clk *rpmi_clk) +{ + struct rpmi_clk_context *context =3D rpmi_clk->context; + struct rpmi_mbox_message msg; + struct rpmi_get_attrs_tx tx; + struct rpmi_get_attrs_rx rx, *resp; + u8 format; + int ret; + + tx.clkid =3D cpu_to_le32(clkid); + rpmi_mbox_init_send_with_response(&msg, RPMI_CLK_SRV_GET_ATTRIBUTES, + &tx, sizeof(tx), &rx, sizeof(rx)); + + ret =3D rpmi_mbox_send_message(context->chan, &msg); + if (ret) + return ret; + + resp =3D rpmi_mbox_get_msg_response(&msg); + if (!resp) + return -EINVAL; + if (resp->status) + return rpmi_to_linux_error(le32_to_cpu(resp->status)); + + rpmi_clk->id =3D clkid; + rpmi_clk->num_rates =3D le32_to_cpu(resp->num_rates); + rpmi_clk->transition_latency =3D le32_to_cpu(resp->transition_latency); + strscpy(rpmi_clk->name, resp->name, RPMI_CLK_NAME_LEN); + + format =3D le32_to_cpu(resp->flags) & 3U; + if (format >=3D RPMI_CLK_TYPE_MAX_IDX) + return -EINVAL; + + rpmi_clk->type =3D format; + + return 0; +} + +static int rpmi_clk_get_supported_rates(u32 clkid, struct rpmi_clk *rpmi_c= lk) +{ + struct rpmi_clk_context *context =3D rpmi_clk->context; + struct rpmi_clk_rate_discrete *rate_discrete; + struct rpmi_clk_rate_linear *rate_linear; + struct rpmi_get_supp_rates_tx tx; + struct rpmi_get_supp_rates_rx *resp; + struct rpmi_mbox_message msg; + size_t clk_rate_idx; + int ret, rateidx, j; + + tx.clkid =3D cpu_to_le32(clkid); + tx.clk_rate_idx =3D 0; + + /* + * Make sure we allocate rx buffer sufficient to be accommodate all + * the rates sent in one RPMI message. + */ + struct rpmi_get_supp_rates_rx *rx __free(kfree) =3D + kzalloc(context->max_msg_data_size, GFP_KERNEL); + if (!rx) + return -ENOMEM; + + rpmi_mbox_init_send_with_response(&msg, RPMI_CLK_SRV_GET_SUPPORTED_RATES, + &tx, sizeof(tx), rx, context->max_msg_data_size); + + ret =3D rpmi_mbox_send_message(context->chan, &msg); + if (ret) + return ret; + + resp =3D rpmi_mbox_get_msg_response(&msg); + if (!resp) + return -EINVAL; + if (resp->status) + return rpmi_to_linux_error(le32_to_cpu(resp->status)); + if (!le32_to_cpu(resp->returned)) + return -EINVAL; + + if (rpmi_clk->type =3D=3D RPMI_CLK_DISCRETE) { + rate_discrete =3D (struct rpmi_clk_rate_discrete *)resp->rates; + + for (rateidx =3D 0; rateidx < le32_to_cpu(resp->returned); rateidx++) { + rpmi_clk->rates->discrete[rateidx] =3D + rpmi_clkrate_u64(le32_to_cpu(rate_discrete[rateidx].hi), + le32_to_cpu(rate_discrete[rateidx].lo)); + } + + /* + * Keep sending the request message until all + * the rates are received. + */ + clk_rate_idx =3D 0; + while (le32_to_cpu(resp->remaining)) { + clk_rate_idx +=3D le32_to_cpu(resp->returned); + tx.clk_rate_idx =3D cpu_to_le32(clk_rate_idx); + + rpmi_mbox_init_send_with_response(&msg, + RPMI_CLK_SRV_GET_SUPPORTED_RATES, + &tx, sizeof(tx), + rx, context->max_msg_data_size); + + ret =3D rpmi_mbox_send_message(context->chan, &msg); + if (ret) + return ret; + + resp =3D rpmi_mbox_get_msg_response(&msg); + if (!resp) + return -EINVAL; + if (resp->status) + return rpmi_to_linux_error(le32_to_cpu(resp->status)); + if (!le32_to_cpu(resp->returned)) + return -EINVAL; + + for (j =3D 0; j < le32_to_cpu(resp->returned); j++) { + if (rateidx >=3D clk_rate_idx + le32_to_cpu(resp->returned)) + break; + rpmi_clk->rates->discrete[rateidx++] =3D + rpmi_clkrate_u64(le32_to_cpu(rate_discrete[j].hi), + le32_to_cpu(rate_discrete[j].lo)); + } + } + } else if (rpmi_clk->type =3D=3D RPMI_CLK_LINEAR) { + rate_linear =3D (struct rpmi_clk_rate_linear *)resp->rates; + + rpmi_clk->rates->linear.min =3D rpmi_clkrate_u64(le32_to_cpu(rate_linear= ->min_hi), + le32_to_cpu(rate_linear->min_lo)); + rpmi_clk->rates->linear.max =3D rpmi_clkrate_u64(le32_to_cpu(rate_linear= ->max_hi), + le32_to_cpu(rate_linear->max_lo)); + rpmi_clk->rates->linear.step =3D rpmi_clkrate_u64(le32_to_cpu(rate_linea= r->step_hi), + le32_to_cpu(rate_linear->step_lo)); + } + + return 0; +} + +static unsigned long rpmi_clk_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct rpmi_clk *rpmi_clk =3D to_rpmi_clk(hw); + struct rpmi_clk_context *context =3D rpmi_clk->context; + struct rpmi_mbox_message msg; + struct rpmi_get_rate_tx tx; + struct rpmi_get_rate_rx rx, *resp; + int ret; + + tx.clkid =3D cpu_to_le32(rpmi_clk->id); + + rpmi_mbox_init_send_with_response(&msg, RPMI_CLK_SRV_GET_RATE, + &tx, sizeof(tx), &rx, sizeof(rx)); + + ret =3D rpmi_mbox_send_message(context->chan, &msg); + if (ret) + return ret; + + resp =3D rpmi_mbox_get_msg_response(&msg); + if (!resp) + return -EINVAL; + if (resp->status) + return rpmi_to_linux_error(le32_to_cpu(resp->status)); + + return rpmi_clkrate_u64(le32_to_cpu(resp->hi), le32_to_cpu(resp->lo)); +} + +static int rpmi_clk_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) +{ + struct rpmi_clk *rpmi_clk =3D to_rpmi_clk(hw); + u64 fmin, fmax, ftmp; + + /* + * Keep the requested rate if the clock format + * is of discrete type. Let the platform which + * is actually controlling the clock handle that. + */ + if (rpmi_clk->type =3D=3D RPMI_CLK_DISCRETE) + return 0; + + fmin =3D rpmi_clk->rates->linear.min; + fmax =3D rpmi_clk->rates->linear.max; + + if (req->rate <=3D fmin) { + req->rate =3D fmin; + return 0; + } else if (req->rate >=3D fmax) { + req->rate =3D fmax; + return 0; + } + + ftmp =3D req->rate - fmin; + ftmp +=3D rpmi_clk->rates->linear.step - 1; + do_div(ftmp, rpmi_clk->rates->linear.step); + + req->rate =3D ftmp * rpmi_clk->rates->linear.step + fmin; + + return 0; +} + +static int rpmi_clk_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct rpmi_clk *rpmi_clk =3D to_rpmi_clk(hw); + struct rpmi_clk_context *context =3D rpmi_clk->context; + struct rpmi_mbox_message msg; + struct rpmi_set_rate_tx tx; + struct rpmi_set_rate_rx rx, *resp; + int ret; + + tx.clkid =3D cpu_to_le32(rpmi_clk->id); + tx.lo =3D cpu_to_le32(lower_32_bits(rate)); + tx.hi =3D cpu_to_le32(upper_32_bits(rate)); + + rpmi_mbox_init_send_with_response(&msg, RPMI_CLK_SRV_SET_RATE, + &tx, sizeof(tx), &rx, sizeof(rx)); + + ret =3D rpmi_mbox_send_message(context->chan, &msg); + if (ret) + return ret; + + resp =3D rpmi_mbox_get_msg_response(&msg); + if (!resp) + return -EINVAL; + if (resp->status) + return rpmi_to_linux_error(le32_to_cpu(resp->status)); + + return 0; +} + +static int rpmi_clk_enable(struct clk_hw *hw) +{ + struct rpmi_clk *rpmi_clk =3D to_rpmi_clk(hw); + struct rpmi_clk_context *context =3D rpmi_clk->context; + struct rpmi_mbox_message msg; + struct rpmi_set_config_tx tx; + struct rpmi_set_config_rx rx, *resp; + int ret; + + tx.config =3D cpu_to_le32(RPMI_CLK_ENABLE); + tx.clkid =3D cpu_to_le32(rpmi_clk->id); + + rpmi_mbox_init_send_with_response(&msg, RPMI_CLK_SRV_SET_CONFIG, + &tx, sizeof(tx), &rx, sizeof(rx)); + + ret =3D rpmi_mbox_send_message(context->chan, &msg); + if (ret) + return ret; + + resp =3D rpmi_mbox_get_msg_response(&msg); + if (!resp) + return -EINVAL; + if (resp->status) + return rpmi_to_linux_error(le32_to_cpu(resp->status)); + + return 0; +} + +static void rpmi_clk_disable(struct clk_hw *hw) +{ + struct rpmi_clk *rpmi_clk =3D to_rpmi_clk(hw); + struct rpmi_clk_context *context =3D rpmi_clk->context; + struct rpmi_mbox_message msg; + struct rpmi_set_config_tx tx; + struct rpmi_set_config_rx rx; + + tx.config =3D cpu_to_le32(RPMI_CLK_DISABLE); + tx.clkid =3D cpu_to_le32(rpmi_clk->id); + + rpmi_mbox_init_send_with_response(&msg, RPMI_CLK_SRV_SET_CONFIG, + &tx, sizeof(tx), &rx, sizeof(rx)); + + rpmi_mbox_send_message(context->chan, &msg); +} + +static const struct clk_ops rpmi_clk_ops =3D { + .recalc_rate =3D rpmi_clk_recalc_rate, + .determine_rate =3D rpmi_clk_determine_rate, + .set_rate =3D rpmi_clk_set_rate, + .prepare =3D rpmi_clk_enable, + .unprepare =3D rpmi_clk_disable, +}; + +static struct clk_hw *rpmi_clk_enumerate(struct rpmi_clk_context *context,= u32 clkid) +{ + struct device *dev =3D context->dev; + unsigned long min_rate, max_rate; + union rpmi_clk_rates *rates; + struct rpmi_clk *rpmi_clk; + struct clk_init_data init =3D {}; + struct clk_hw *clk_hw; + int ret; + + rates =3D devm_kzalloc(dev, sizeof(*rates), GFP_KERNEL); + if (!rates) + return ERR_PTR(-ENOMEM); + + rpmi_clk =3D devm_kzalloc(dev, sizeof(*rpmi_clk), GFP_KERNEL); + if (!rpmi_clk) + return ERR_PTR(-ENOMEM); + + rpmi_clk->context =3D context; + rpmi_clk->rates =3D rates; + + ret =3D rpmi_clk_get_attrs(clkid, rpmi_clk); + if (ret) + return dev_err_ptr_probe(dev, ret, + "Failed to get clk-%u attributes\n", + clkid); + + ret =3D rpmi_clk_get_supported_rates(clkid, rpmi_clk); + if (ret) + return dev_err_ptr_probe(dev, ret, + "Get supported rates failed for clk-%u\n", + clkid); + + init.flags =3D CLK_GET_RATE_NOCACHE; + init.num_parents =3D 0; + init.ops =3D &rpmi_clk_ops; + init.name =3D rpmi_clk->name; + clk_hw =3D &rpmi_clk->hw; + clk_hw->init =3D &init; + + ret =3D devm_clk_hw_register(dev, clk_hw); + if (ret) + return dev_err_ptr_probe(dev, ret, + "Unable to register clk-%u\n", + clkid); + + if (rpmi_clk->type =3D=3D RPMI_CLK_DISCRETE) { + min_rate =3D rpmi_clk->rates->discrete[0]; + max_rate =3D rpmi_clk->rates->discrete[rpmi_clk->num_rates - 1]; + } else { + min_rate =3D rpmi_clk->rates->linear.min; + max_rate =3D rpmi_clk->rates->linear.max; + } + + clk_hw_set_rate_range(clk_hw, min_rate, max_rate); + + return clk_hw; +} + +static void rpmi_clk_mbox_chan_release(void *data) +{ + struct mbox_chan *chan =3D data; + + mbox_free_channel(chan); +} + +static int rpmi_clk_probe(struct platform_device *pdev) +{ + int ret; + unsigned int num_clocks, i; + struct clk_hw_onecell_data *clk_data; + struct rpmi_clk_context *context; + struct rpmi_mbox_message msg; + struct clk_hw *hw_ptr; + struct device *dev =3D &pdev->dev; + + context =3D devm_kzalloc(dev, sizeof(*context), GFP_KERNEL); + if (!context) + return -ENOMEM; + context->dev =3D dev; + platform_set_drvdata(pdev, context); + + context->client.dev =3D context->dev; + context->client.rx_callback =3D NULL; + context->client.tx_block =3D false; + context->client.knows_txdone =3D true; + context->client.tx_tout =3D 0; + + context->chan =3D mbox_request_channel(&context->client, 0); + if (IS_ERR(context->chan)) + return PTR_ERR(context->chan); + + ret =3D devm_add_action_or_reset(dev, rpmi_clk_mbox_chan_release, context= ->chan); + if (ret) + return dev_err_probe(dev, ret, "Failed to add rpmi mbox channel cleanup\= n"); + + rpmi_mbox_init_get_attribute(&msg, RPMI_MBOX_ATTR_SPEC_VERSION); + ret =3D rpmi_mbox_send_message(context->chan, &msg); + if (ret) + return dev_err_probe(dev, ret, "Failed to get spec version\n"); + if (msg.attr.value < RPMI_MKVER(1, 0)) { + return dev_err_probe(dev, -EINVAL, + "msg protocol version mismatch, expected 0x%x, found 0x%x\n", + RPMI_MKVER(1, 0), msg.attr.value); + } + + rpmi_mbox_init_get_attribute(&msg, RPMI_MBOX_ATTR_SERVICEGROUP_ID); + ret =3D rpmi_mbox_send_message(context->chan, &msg); + if (ret) + return dev_err_probe(dev, ret, "Failed to get service group ID\n"); + if (msg.attr.value !=3D RPMI_SRVGRP_CLOCK) { + return dev_err_probe(dev, -EINVAL, + "service group match failed, expected 0x%x, found 0x%x\n", + RPMI_SRVGRP_CLOCK, msg.attr.value); + } + + rpmi_mbox_init_get_attribute(&msg, RPMI_MBOX_ATTR_SERVICEGROUP_VERSION); + ret =3D rpmi_mbox_send_message(context->chan, &msg); + if (ret) + return dev_err_probe(dev, ret, "Failed to get service group version\n"); + if (msg.attr.value < RPMI_MKVER(1, 0)) { + return dev_err_probe(dev, -EINVAL, + "service group version failed, expected 0x%x, found 0x%x\n", + RPMI_MKVER(1, 0), msg.attr.value); + } + + rpmi_mbox_init_get_attribute(&msg, RPMI_MBOX_ATTR_MAX_MSG_DATA_SIZE); + ret =3D rpmi_mbox_send_message(context->chan, &msg); + if (ret) + return dev_err_probe(dev, ret, "Failed to get max message data size\n"); + + context->max_msg_data_size =3D msg.attr.value; + num_clocks =3D rpmi_clk_get_num_clocks(context); + if (!num_clocks) + return dev_err_probe(dev, -ENODEV, "No clocks found\n"); + + clk_data =3D devm_kzalloc(dev, struct_size(clk_data, hws, num_clocks), + GFP_KERNEL); + if (!clk_data) + return dev_err_probe(dev, -ENOMEM, "No memory for clock data\n"); + clk_data->num =3D num_clocks; + + for (i =3D 0; i < clk_data->num; i++) { + hw_ptr =3D rpmi_clk_enumerate(context, i); + if (IS_ERR(hw_ptr)) { + return dev_err_probe(dev, PTR_ERR(hw_ptr), + "Failed to register clk-%d\n", i); + } + clk_data->hws[i] =3D hw_ptr; + } + + ret =3D devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, clk_data); + if (ret) + return dev_err_probe(dev, ret, "Failed to register clock HW provider\n"); + + return 0; +} + +static const struct of_device_id rpmi_clk_of_match[] =3D { + { .compatible =3D "riscv,rpmi-clock" }, + { } +}; +MODULE_DEVICE_TABLE(of, rpmi_clk_of_match); + +static struct platform_driver rpmi_clk_driver =3D { + .driver =3D { + .name =3D "riscv-rpmi-clock", + .of_match_table =3D rpmi_clk_of_match, + }, + .probe =3D rpmi_clk_probe, +}; +module_platform_driver(rpmi_clk_driver); + +MODULE_AUTHOR("Rahul Pathak "); +MODULE_DESCRIPTION("Clock Driver based on RPMI message protocol"); +MODULE_LICENSE("GPL"); diff --git a/include/linux/mailbox/riscv-rpmi-message.h b/include/linux/mai= lbox/riscv-rpmi-message.h index 3f4c73529aa5..c90918dca367 100644 --- a/include/linux/mailbox/riscv-rpmi-message.h +++ b/include/linux/mailbox/riscv-rpmi-message.h @@ -90,6 +90,22 @@ static inline int rpmi_to_linux_error(int rpmi_error) } } =20 +/* RPMI service group IDs */ +#define RPMI_SRVGRP_CLOCK 0x00008 + +/* RPMI clock service IDs */ +enum rpmi_clock_service_id { + RPMI_CLK_SRV_ENABLE_NOTIFICATION =3D 0x01, + RPMI_CLK_SRV_GET_NUM_CLOCKS =3D 0x02, + RPMI_CLK_SRV_GET_ATTRIBUTES =3D 0x03, + RPMI_CLK_SRV_GET_SUPPORTED_RATES =3D 0x04, + RPMI_CLK_SRV_SET_CONFIG =3D 0x05, + RPMI_CLK_SRV_GET_CONFIG =3D 0x06, + RPMI_CLK_SRV_SET_RATE =3D 0x07, + RPMI_CLK_SRV_GET_RATE =3D 0x08, + RPMI_CLK_SRV_ID_MAX_COUNT +}; + /* RPMI Linux mailbox attribute IDs */ enum rpmi_mbox_attribute_id { RPMI_MBOX_ATTR_SPEC_VERSION, diff --git a/include/linux/wordpart.h b/include/linux/wordpart.h index ed8717730037..5cad9c244bf2 100644 --- a/include/linux/wordpart.h +++ b/include/linux/wordpart.h @@ -39,6 +39,14 @@ */ #define make_u32_from_two_u16(hi, lo) (((u32)(hi) << 16) | (u32)(lo)) =20 +/** + * make_u64_from_two_u32 - return u64 number by combining + * two u32 numbers. + * @hi: upper 32 bit number + * @lo: lower 32 bit number + */ +#define make_u64_from_two_u32(hi, lo) (((u64)(hi) << 32) | (u32)(lo)) + /** * REPEAT_BYTE - repeat the value @x multiple times as an unsigned long va= lue * @x: value to repeat --=20 2.43.0