From nobody Sun Oct 5 23:52:02 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6BF642E36E6; Mon, 28 Jul 2025 06:49:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753685394; cv=none; b=GYZpwvHZ1po0+7SQk/ElxWXbRTBvzaG2dExKN1QCANxUCPg7NV2fW41EbGFLEto0x4Csi6PeZV7LR2hZE9UiTmBO6Pd7D4EAX1B3+cv9AwyIN8t2WclKC4VVBtCVnyeDmGM3FeKXzH1V0RGq+ARFKOpozx6t1DaE/UyKYb/zuhY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753685394; c=relaxed/simple; bh=uAX8Lw55ZwWtTrr9I5WDi7Xk2+x+7/0Pib/WIeArjGo=; h=From:To:Cc:Subject:Date:Message-Id:MIME-Version; b=F4AnZXATVRevHRL4vIFIHa8tbVpXjy7tgMW+RcvAWxYwvZvY2CRduEJBJ0o6OkZTiDv4P3MHqLv78BWBC/eXn9eepJrsB5Fz5/BYsVJXm+1evdRCO1fJmmZLEbaag6MYGNByAkNudtFAfjXgfmakPDSiOusQNb6RIIR3HhzhQgU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Cswc0eCx; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Cswc0eCx" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 89D7CC4CEF4; Mon, 28 Jul 2025 06:49:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1753685394; bh=uAX8Lw55ZwWtTrr9I5WDi7Xk2+x+7/0Pib/WIeArjGo=; h=From:To:Cc:Subject:Date:From; b=Cswc0eCxHw1vURagW9/hdGAAnuyRjWdY3lhAkgmuux42zuC/AS17NnWWm8/CHofHo ctK8sb7isfaklNC3QIHUbEr+A1jEpdD8fc8uowMEtyE9Wr+bQnxuyOvLpiO+h5z6eh LzANJ4JpEXLRbZB6CLhyO9J2j3uAybugxRTDbjmX5IWc/7DUTygKpEQ7wDSA1hbMA+ dbrGdhf3R7N+TKc2Xtfw6I0g/ZowQoZ+VcMyoeS76KP34r1zIWk/6KD1M+JEuB/5dD V4BRyB09mdWRgSeiie9Kt1jiLxW+2IS9AV9MTdAFyMjldP0meSwTHIFLzvKBVCRKTu nEMCwRXkULOew== From: Michael Walle To: Andrew Lunn , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni Cc: Roger Quadros , Simon Horman , Siddharth Vadapalli , Matthias Schiffer , Maxime Chevallier , netdev@vger.kernel.org, linux-kernel@vger.kernel.org, Michael Walle Subject: [PATCH net-next] Revert "net: ethernet: ti: am65-cpsw: fixup PHY mode for fixed RGMII TX delay" Date: Mon, 28 Jul 2025 08:49:38 +0200 Message-Id: <20250728064938.275304-1-mwalle@kernel.org> X-Mailer: git-send-email 2.39.5 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This reverts commit ca13b249f291f4920466638d1adbfb3f9c8db6e9. This patch breaks the transmit path on an AM67A/J722S. This SoC has an (undocumented) configurable delay (CTRL_MMR0_CFG0_ENET1_CTRL, bit 4). The u-boot driver (net/ti/am65-cpsw-nuss.c) will configure the delay in am65_cpsw_gmii_sel_k3(). If the u-boot device tree uses rgmii-id this patch will break the transmit path because it will disable the PHY delay on the transmit path, but the bootloader has already disabled the MAC delay, hence there will be no delay at all. Although the datasheet reads the delay is fixed, that is at least wrong for the J722S/AM67A and apparently for at least the AM65x (which was the original target of the u-boot driver). Fixes: ca13b249f291 ("net: ethernet: ti: am65-cpsw: fixup PHY mode for fixe= d RGMII TX delay") Signed-off-by: Michael Walle --- This is targeted as net-next although the merge window is open, because the original patch is just in net-next. --- drivers/net/ethernet/ti/am65-cpsw-nuss.c | 27 ++---------------------- 1 file changed, 2 insertions(+), 25 deletions(-) diff --git a/drivers/net/ethernet/ti/am65-cpsw-nuss.c b/drivers/net/etherne= t/ti/am65-cpsw-nuss.c index ecd6ecac87bb..231ca141331f 100644 --- a/drivers/net/ethernet/ti/am65-cpsw-nuss.c +++ b/drivers/net/ethernet/ti/am65-cpsw-nuss.c @@ -2600,7 +2600,6 @@ static int am65_cpsw_nuss_init_slave_ports(struct am6= 5_cpsw_common *common) return -ENOENT; =20 for_each_child_of_node(node, port_np) { - phy_interface_t phy_if; struct am65_cpsw_port *port; u32 port_id; =20 @@ -2666,36 +2665,14 @@ static int am65_cpsw_nuss_init_slave_ports(struct a= m65_cpsw_common *common) =20 /* get phy/link info */ port->slave.port_np =3D of_node_get(port_np); - ret =3D of_get_phy_mode(port_np, &phy_if); + ret =3D of_get_phy_mode(port_np, &port->slave.phy_if); if (ret) { dev_err(dev, "%pOF read phy-mode err %d\n", port_np, ret); goto of_node_put; } =20 - /* CPSW controllers supported by this driver have a fixed - * internal TX delay in RGMII mode. Fix up PHY mode to account - * for this and warn about Device Trees that claim to have a TX - * delay on the PCB. - */ - switch (phy_if) { - case PHY_INTERFACE_MODE_RGMII_ID: - phy_if =3D PHY_INTERFACE_MODE_RGMII_RXID; - break; - case PHY_INTERFACE_MODE_RGMII_TXID: - phy_if =3D PHY_INTERFACE_MODE_RGMII; - break; - case PHY_INTERFACE_MODE_RGMII: - case PHY_INTERFACE_MODE_RGMII_RXID: - dev_warn(dev, - "RGMII mode without internal TX delay unsupported; please fix your De= vice Tree\n"); - break; - default: - break; - } - - port->slave.phy_if =3D phy_if; - ret =3D phy_set_mode_ext(port->slave.ifphy, PHY_MODE_ETHERNET, phy_if); + ret =3D phy_set_mode_ext(port->slave.ifphy, PHY_MODE_ETHERNET, port->sla= ve.phy_if); if (ret) goto of_node_put; =20 --=20 2.39.5