From nobody Sun Oct 5 23:37:45 2025 Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B1FC11FF7C8; Mon, 28 Jul 2025 15:33:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.132.182.106 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753716783; cv=none; b=Irk7wlfJn5TYZKHTVbpB36vuhYCfaktE2nH1inrLkSIvzltlVKIUZnXEV8f0fg56a22LXVxj1wghj+vFhT94YRPN/5WzZzd26peKJiLU8r/1KfQR1/32Dcz/dyLqnFaJW44SG7GoqFGDD+d3DzjAgQavdLLGrGZR/Ly8fr3Jue0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753716783; c=relaxed/simple; bh=Dq2ykfq63wn8VObJtf2Dtv3Y1KpLFKfxnczqmYre38w=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=NwnEZN1kZvXjJ/m05i0wge+DvXGV9F5308rBLmaLxaz7GZmF1k6McVZ474YBbcOsWBnkznSit/KU6mbsS0onIz432F5yrtDlKbZ/2fDH+83LyMe+QSIQkslWqnYZonxrAvhNez/iLiCc3DDwZnonv4kyege6EMzBZPL9nUHQOUg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com; spf=pass smtp.mailfrom=foss.st.com; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b=QWQne/m3; arc=none smtp.client-ip=185.132.182.106 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=foss.st.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b="QWQne/m3" Received: from pps.filterd (m0241204.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 56SFWM3m003733; Mon, 28 Jul 2025 17:32:41 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=selector1; bh= 1S+/fxjBGM9OThOsnlJiBdnI+RCOnybmlz6yPJOrPUQ=; b=QWQne/m3XfCBehhG wu7fz9Ssqb3Z1wtPXL8wioGHUBX9kCbn7ML4vf5BUXMa9XsdT8Ds9NdP+2/oiiT+ y6mE8aPjHP7+Slc0w4qgf0v5zLtTDU4q+j1Xq9TekXI5GSuLr8WgfKgc4Uum7XdF 9zAszF15vaMJdCMZ/ouO/k9SI2DcRZsqCM5pCfwg4EFj4zh4ixkf0IkcLxgWBrBo 1zLME0JIiqOHpSQu4fjQ9TQAXlilcp+KZKNRZ+ICCB3cWEXLOOFVekjsgU61VgS/ cy34ovwxQXWO0XCUuAXflnPp8coea90uKeQ1t+TOt6ZUNFHEwghVhw0XHuTbUfbx Yvy74g== Received: from beta.dmz-ap.st.com (beta.dmz-ap.st.com [138.198.100.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 484pc28w28-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 28 Jul 2025 17:32:40 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 450A24002D; Mon, 28 Jul 2025 17:31:10 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 68E70787C37; Mon, 28 Jul 2025 17:29:50 +0200 (CEST) Received: from localhost (10.252.23.100) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Mon, 28 Jul 2025 17:29:50 +0200 From: =?utf-8?q?Cl=C3=A9ment_Le_Goffic?= Date: Mon, 28 Jul 2025 17:29:32 +0200 Subject: [PATCH v5 01/20] bus: firewall: move stm32_firewall header file in include folder Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250728-ddrperfm-upstream-v5-1-03f1be8ad396@foss.st.com> References: <20250728-ddrperfm-upstream-v5-0-03f1be8ad396@foss.st.com> In-Reply-To: <20250728-ddrperfm-upstream-v5-0-03f1be8ad396@foss.st.com> To: Will Deacon , Mark Rutland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Philipp Zabel , Jonathan Corbet , Gatien Chevallier , Michael Turquette , Stephen Boyd , Gabriel Fernandez , Krzysztof Kozlowski , Le Goffic , Julius Werner CC: , , , , , , , =?utf-8?q?Cl=C3=A9ment_Le_Goffic?= X-Mailer: b4 0.15-dev-8018a X-ClientProxiedBy: SHFCAS1NODE2.st.com (10.75.129.73) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-28_03,2025-07-28_01,2025-03-28_01 Other driver than rifsc and etzpc can implement firewall ops, such as rcc. In order for them to have access to the ops and type of this framework, we need to get the `stm32_firewall.h` file in the include/ folder. Signed-off-by: Cl=C3=A9ment Le Goffic --- drivers/bus/stm32_etzpc.c | 3 +-- drivers/bus/stm32_firewall.c | 3 +-- drivers/bus/stm32_rifsc.c | 3 +-- {drivers =3D> include/linux}/bus/stm32_firewall.h | 0 4 files changed, 3 insertions(+), 6 deletions(-) diff --git a/drivers/bus/stm32_etzpc.c b/drivers/bus/stm32_etzpc.c index 7fc0f16960be..4918a14e507e 100644 --- a/drivers/bus/stm32_etzpc.c +++ b/drivers/bus/stm32_etzpc.c @@ -5,6 +5,7 @@ =20 #include #include +#include #include #include #include @@ -16,8 +17,6 @@ #include #include =20 -#include "stm32_firewall.h" - /* * ETZPC registers */ diff --git a/drivers/bus/stm32_firewall.c b/drivers/bus/stm32_firewall.c index 2fc9761dadec..ef4988054b44 100644 --- a/drivers/bus/stm32_firewall.c +++ b/drivers/bus/stm32_firewall.c @@ -5,6 +5,7 @@ =20 #include #include +#include #include #include #include @@ -18,8 +19,6 @@ #include #include =20 -#include "stm32_firewall.h" - /* Corresponds to STM32_FIREWALL_MAX_EXTRA_ARGS + firewall ID */ #define STM32_FIREWALL_MAX_ARGS (STM32_FIREWALL_MAX_EXTRA_ARGS + 1) =20 diff --git a/drivers/bus/stm32_rifsc.c b/drivers/bus/stm32_rifsc.c index 4cf1b60014b7..643ddd0a5f54 100644 --- a/drivers/bus/stm32_rifsc.c +++ b/drivers/bus/stm32_rifsc.c @@ -5,6 +5,7 @@ =20 #include #include +#include #include #include #include @@ -16,8 +17,6 @@ #include #include =20 -#include "stm32_firewall.h" - /* * RIFSC offset register */ diff --git a/drivers/bus/stm32_firewall.h b/include/linux/bus/stm32_firewal= l.h similarity index 100% rename from drivers/bus/stm32_firewall.h rename to include/linux/bus/stm32_firewall.h --=20 2.43.0 From nobody Sun Oct 5 23:37:45 2025 Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AF77A8F6E; Mon, 28 Jul 2025 15:33:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.132.182.106 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753716782; cv=none; b=CzCL9KVwMWS01WfJRrmTSSE5RNqxeSmn98yVPiR/KOz1EE+xM2PXbAChmN1g7Ly3YJxbRBAbptm3vs2pNr4VWtZbJ6hD7tqiLWVgs9RmTuGQXTMK1OCSkt0y4je9v35n9uhyyiFPLkrhOD08DhqH0USPAKnHOjooYvX6LIyFEtQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753716782; c=relaxed/simple; bh=2PIpfN3dZvXiQ9iIBgbBu5gRJSTkbuCQSySSFGDtB9c=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=grAFQ7WCnh9B7YaVSOZxOwi4FezTcYsOTp3iyhZa0RNOSLnWsasKNMIWhDuwxCkLSQANwJ8wbv7KyMZR1pC9YbKQMMYpvdeWoCYarEmzjcIZQSLxRfqVT8xsfQ/QzKV1EqruRsknFidAffh0VNEa11i2VQyd3Ek9gLKCOyEGRko= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com; spf=pass smtp.mailfrom=foss.st.com; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b=BKjbs/xs; arc=none smtp.client-ip=185.132.182.106 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=foss.st.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b="BKjbs/xs" Received: from pps.filterd (m0241204.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 56SDmqUL025850; Mon, 28 Jul 2025 17:32:40 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=selector1; bh= L5U4iOIMzTLQcNGAWLcYUHl7amMuMgZWgZO8MaFVrQk=; b=BKjbs/xs31c7FSK6 R7Hw18HQ/9sqBmYKB0lJ24Om3mySIoCQUhNKsOM9eaxfgWKe1vxufD07ZCSE7a6b VI4iAG0DRoeerDPWNPUUAi2++vS0oGTT4mUMNZAfmehmY1mc+7Tpj5T4zT/lDW0A Wy5v6lI01wD/63+TaMivxAbpjZ1OhYmWdJKZMODqtgFu/hyPWd4IUQRQRIPfSO6g UQGOmuWcLg1r4nJ6QmCdriRfKje71aZ5yhK7foBX+WP0P1rhiDvF+W6FPRdYF1Oc N8/5Tak5VIaC4pC8FAAbc2rCxOee3BauQ4G1SvwemaxM0OgZpU+V6sruODTUrMeo 6M4rPA== Received: from beta.dmz-ap.st.com (beta.dmz-ap.st.com [138.198.100.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 484pc28w27-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 28 Jul 2025 17:32:40 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 4637940045; Mon, 28 Jul 2025 17:31:10 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 5F84776DC2C; Mon, 28 Jul 2025 17:29:51 +0200 (CEST) Received: from localhost (10.252.23.100) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Mon, 28 Jul 2025 17:29:51 +0200 From: =?utf-8?q?Cl=C3=A9ment_Le_Goffic?= Date: Mon, 28 Jul 2025 17:29:33 +0200 Subject: [PATCH v5 02/20] dt-bindings: stm32: stm32mp25: add `#access-controller-cells` property Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250728-ddrperfm-upstream-v5-2-03f1be8ad396@foss.st.com> References: <20250728-ddrperfm-upstream-v5-0-03f1be8ad396@foss.st.com> In-Reply-To: <20250728-ddrperfm-upstream-v5-0-03f1be8ad396@foss.st.com> To: Will Deacon , Mark Rutland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Philipp Zabel , Jonathan Corbet , Gatien Chevallier , Michael Turquette , Stephen Boyd , Gabriel Fernandez , Krzysztof Kozlowski , Le Goffic , Julius Werner CC: , , , , , , , =?utf-8?q?Cl=C3=A9ment_Le_Goffic?= X-Mailer: b4 0.15-dev-8018a X-ClientProxiedBy: SHFCAS1NODE2.st.com (10.75.129.73) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-28_03,2025-07-28_01,2025-03-28_01 RCC is able to check the availability of a clock. Allow to query the RCC with a firewall ID. Signed-off-by: Cl=C3=A9ment Le Goffic Acked-by: Rob Herring (Arm) --- Documentation/devicetree/bindings/clock/st,stm32mp25-rcc.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/st,stm32mp25-rcc.yaml = b/Documentation/devicetree/bindings/clock/st,stm32mp25-rcc.yaml index 88e52f10d1ec..4d471e3d89bc 100644 --- a/Documentation/devicetree/bindings/clock/st,stm32mp25-rcc.yaml +++ b/Documentation/devicetree/bindings/clock/st,stm32mp25-rcc.yaml @@ -31,6 +31,11 @@ properties: '#reset-cells': const: 1 =20 + '#access-controller-cells': + const: 1 + description: + Contains the firewall ID associated to the peripheral. + clocks: items: - description: CK_SCMI_HSE High Speed External oscillator (8 to 48 M= Hz) @@ -123,6 +128,7 @@ required: - reg - '#clock-cells' - '#reset-cells' + - '#access-controller-cells' - clocks =20 additionalProperties: false @@ -136,6 +142,7 @@ examples: reg =3D <0x44200000 0x10000>; #clock-cells =3D <1>; #reset-cells =3D <1>; + #access-controller-cells =3D <1>; clocks =3D <&scmi_clk CK_SCMI_HSE>, <&scmi_clk CK_SCMI_HSI>, <&scmi_clk CK_SCMI_MSI>, --=20 2.43.0 From nobody Sun Oct 5 23:37:45 2025 Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D20752737F9; Mon, 28 Jul 2025 15:33:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.132.182.106 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753716804; cv=none; b=C6qXEbO6MTJc05xcfZz0w17yweNhdnD5pEwnayWj+x0EHAb/uEB1FnxGoRqNyUbv+xDORNGOUynJKDdTP8UGlencFOfN7/sx+oktYdZDzOS1Kzgtavh448GzvWIjQtHM+GPT+yXOAbm9IcJj6WRNlwHGm11jRljqdGyxu2+LavU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753716804; c=relaxed/simple; bh=zHL0/JrntZk6f9z9OaKUCRl5Ve/+xb8bifr4gesVLAc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=M3cIpvIGdz8jCEywgN3Xj5VGhtERJ+1ugXTmIbR6+7rQ/RIGA0M2kpt/fUG7x5+DK5//+pJEppT2HQSquEqo9hTqWf4/KgjchgvT17xIRruHE6Pl9OyQxcaP9setB+b8onD1PqI3w375JN1LuevWuAzflQpF6EvLaEdE2AaJ7IE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com; spf=pass smtp.mailfrom=foss.st.com; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b=nmLUHOJS; arc=none smtp.client-ip=185.132.182.106 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=foss.st.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b="nmLUHOJS" Received: from pps.filterd (m0241204.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 56SEjk2u023740; Mon, 28 Jul 2025 17:33:04 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=selector1; bh= c84xGmzk0WDtYO8pxiXJLl1Oz2OVFtl3JU/pJXFAfdc=; b=nmLUHOJSOmejT17L CtsYu3DcFX6tN0GuzXqA7q1AfhjywxAlhtqkMd565axWcuuSzbeFx9G48Do300iK 5Wkae9PHKDlA9iIGcDI6JJf0Kjw9FxF/EDoHc/jQa5bKXlXEN7dwgOZPZnhUJ8ei qOaA1DmOJCwHNmvHuIrADfzDzO3mACPbbj08V/7PDwv21ynUFS62wabb1hC5lsp6 wuRKdLBeALeuE2GJkXwdC6Q4BTakPv+72DX4P5Gy/OnVq4leLXR2MyFePhS42G32 qMhC0KZK50s39CjwWyp6RxDVsvtQMvrPHhbNHGL5ztcr0GxZdfg/c5jYiTEgmRXN k3aG/Q== Received: from beta.dmz-ap.st.com (beta.dmz-ap.st.com [138.198.100.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 484pc28w3d-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 28 Jul 2025 17:33:04 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 3F45A40046; Mon, 28 Jul 2025 17:31:14 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 6B80F787C2C; Mon, 28 Jul 2025 17:29:52 +0200 (CEST) Received: from localhost (10.252.23.100) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Mon, 28 Jul 2025 17:29:52 +0200 From: =?utf-8?q?Cl=C3=A9ment_Le_Goffic?= Date: Mon, 28 Jul 2025 17:29:34 +0200 Subject: [PATCH v5 03/20] clk: stm32mp25: add firewall grant_access ops Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250728-ddrperfm-upstream-v5-3-03f1be8ad396@foss.st.com> References: <20250728-ddrperfm-upstream-v5-0-03f1be8ad396@foss.st.com> In-Reply-To: <20250728-ddrperfm-upstream-v5-0-03f1be8ad396@foss.st.com> To: Will Deacon , Mark Rutland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Philipp Zabel , Jonathan Corbet , Gatien Chevallier , Michael Turquette , Stephen Boyd , Gabriel Fernandez , Krzysztof Kozlowski , Le Goffic , Julius Werner CC: , , , , , , , =?utf-8?q?Cl=C3=A9ment_Le_Goffic?= X-Mailer: b4 0.15-dev-8018a X-ClientProxiedBy: SHFCAS1NODE2.st.com (10.75.129.73) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-28_03,2025-07-28_01,2025-03-28_01 On STM32MP25, the RCC peripheral manages the secure level of resources that are used by other devices such as clocks. Declare this peripheral as a firewall controller. Signed-off-by: Cl=C3=A9ment Le Goffic --- drivers/clk/stm32/clk-stm32mp25.c | 40 +++++++++++++++++++++++++++++++++++= +++- 1 file changed, 39 insertions(+), 1 deletion(-) diff --git a/drivers/clk/stm32/clk-stm32mp25.c b/drivers/clk/stm32/clk-stm3= 2mp25.c index 52f0e8a12926..af4bc06d703a 100644 --- a/drivers/clk/stm32/clk-stm32mp25.c +++ b/drivers/clk/stm32/clk-stm32mp25.c @@ -4,8 +4,10 @@ * Author: Gabriel Fernandez for STMicroel= ectronics. */ =20 +#include #include #include +#include #include #include =20 @@ -1602,6 +1604,11 @@ static int stm32_rcc_get_access(void __iomem *base, = u32 index) return 0; } =20 +static int stm32mp25_rcc_grant_access(struct stm32_firewall_controller *ct= rl, u32 firewall_id) +{ + return stm32_rcc_get_access(ctrl->mmio, firewall_id); +} + static int stm32mp25_check_security(struct device_node *np, void __iomem *= base, const struct clock_config *cfg) { @@ -1970,6 +1977,7 @@ MODULE_DEVICE_TABLE(of, stm32mp25_match_data); =20 static int stm32mp25_rcc_clocks_probe(struct platform_device *pdev) { + struct stm32_firewall_controller *rcc_controller; struct device *dev =3D &pdev->dev; void __iomem *base; int ret; @@ -1982,7 +1990,36 @@ static int stm32mp25_rcc_clocks_probe(struct platfor= m_device *pdev) if (ret) return ret; =20 - return stm32_rcc_init(dev, stm32mp25_match_data, base); + ret =3D stm32_rcc_init(dev, stm32mp25_match_data, base); + if (ret) + return ret; + + rcc_controller =3D devm_kzalloc(&pdev->dev, sizeof(*rcc_controller), GFP_= KERNEL); + if (!rcc_controller) + return -ENOMEM; + + rcc_controller->dev =3D dev; + rcc_controller->mmio =3D base; + rcc_controller->name =3D dev_driver_string(dev); + rcc_controller->type =3D STM32_PERIPHERAL_FIREWALL; + rcc_controller->grant_access =3D stm32mp25_rcc_grant_access; + + platform_set_drvdata(pdev, rcc_controller); + + ret =3D stm32_firewall_controller_register(rcc_controller); + if (ret) { + dev_err(dev, "Couldn't register as a firewall controller: %d\n", ret); + return ret; + } + + return 0; +} + +static void stm32mp25_rcc_clocks_remove(struct platform_device *pdev) +{ + struct stm32_firewall_controller *rcc_controller =3D platform_get_drvdata= (pdev); + + stm32_firewall_controller_unregister(rcc_controller); } =20 static struct platform_driver stm32mp25_rcc_clocks_driver =3D { @@ -1991,6 +2028,7 @@ static struct platform_driver stm32mp25_rcc_clocks_dr= iver =3D { .of_match_table =3D stm32mp25_match_data, }, .probe =3D stm32mp25_rcc_clocks_probe, + .remove =3D stm32mp25_rcc_clocks_remove, }; =20 static int __init stm32mp25_clocks_init(void) --=20 2.43.0 From nobody Sun Oct 5 23:37:45 2025 Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B1D4226F47D; Mon, 28 Jul 2025 15:33:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.132.182.106 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753716793; cv=none; b=VHt/NVR4vU4V/OajvKwL7UCD104JAPix5yyTq0x5LClsu42VudvHF1p4Sug8GD6Aka9oamnLXLxrUsCet1gA0QJh9fZ0lvwD+iBYyEW2GBpO1FQjIV9LZ8YvonrISloAdUf2K/tLeP0CXSzGthLWYW4xzTyAQzcKX6psr9C6Jec= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753716793; c=relaxed/simple; bh=d5iWwZQBtscc9/XYMe8rkBSJD76rq7wf56xNPUB+T6Q=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=rTESiwDVps2k5rRFBKDdzoVNzfkVAadzQ1UkM10LgssjeDkn94/qUS8MSYc1RqSXyDAq2tWYeq5UCETtdR4GvorO5YIx2LsX7U7hyD4Es4Fpt6gVYFw/mBiwFJ3r+zlIQ7fmcQ6gpBddLIR/oElA5FnGIU93wJMncS+SIk0OT44= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com; spf=pass smtp.mailfrom=foss.st.com; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b=5njpOx0c; arc=none smtp.client-ip=185.132.182.106 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=foss.st.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b="5njpOx0c" Received: from pps.filterd (m0369458.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 56SEiew9019399; Mon, 28 Jul 2025 17:32:52 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=selector1; bh= /Ngm9p3NQD6arEx7d73G9n3PIlBqe76QEjiMrucBWPs=; b=5njpOx0cBMLpESJh M6RZkbEey0kVvyqDeDGcf+YNYHNBKGvYgS/KUSM9WIAxGIFUcRJ3rz73Iyolgdqw m0a3hW3PzMEVVogaixOiIyopiAOhswj4MzjRld47Q4955oMDE8P5rl2CN9FennO4 L4OqyfYHugPA4OHgR3eyu/IKhTc/43JBJmgE/Zw/22ECJo5scNxOyL4AwEMqX/24 RezpTT55A9vO3Sd58wcnH4naZ9wD0zOOJ4TGihRKAF8s1hTidq3rSnugurMsCraT +uR+xH7xFQWsw19zfQpeS8/UC2pLVtRYm9CC9STFkDXaY+oGeDgVG0jao9DNVk1m Tj6CnA== Received: from beta.dmz-ap.st.com (beta.dmz-ap.st.com [138.198.100.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 4858k4x9ct-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 28 Jul 2025 17:32:52 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 43F2F40047; Mon, 28 Jul 2025 17:31:14 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 701B6787C38; Mon, 28 Jul 2025 17:29:53 +0200 (CEST) Received: from localhost (10.252.23.100) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Mon, 28 Jul 2025 17:29:53 +0200 From: =?utf-8?q?Cl=C3=A9ment_Le_Goffic?= Date: Mon, 28 Jul 2025 17:29:35 +0200 Subject: [PATCH v5 04/20] arm64: dts: st: set rcc as an access-controller Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250728-ddrperfm-upstream-v5-4-03f1be8ad396@foss.st.com> References: <20250728-ddrperfm-upstream-v5-0-03f1be8ad396@foss.st.com> In-Reply-To: <20250728-ddrperfm-upstream-v5-0-03f1be8ad396@foss.st.com> To: Will Deacon , Mark Rutland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Philipp Zabel , Jonathan Corbet , Gatien Chevallier , Michael Turquette , Stephen Boyd , Gabriel Fernandez , Krzysztof Kozlowski , Le Goffic , Julius Werner CC: , , , , , , , =?utf-8?q?Cl=C3=A9ment_Le_Goffic?= X-Mailer: b4 0.15-dev-8018a X-ClientProxiedBy: SHFCAS1NODE2.st.com (10.75.129.73) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-28_03,2025-07-28_01,2025-03-28_01 RCC now implements firewall access ops to check the access to resources. Allow client nodes to query the RCC with one firewall ID. Signed-off-by: Cl=C3=A9ment Le Goffic --- arch/arm64/boot/dts/st/stm32mp251.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/s= t/stm32mp251.dtsi index 8d87865850a7..0683c2d5cb6f 100644 --- a/arch/arm64/boot/dts/st/stm32mp251.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi @@ -1153,6 +1153,7 @@ rcc: clock-controller@44200000 { reg =3D <0x44200000 0x10000>; #clock-cells =3D <1>; #reset-cells =3D <1>; + #access-controller-cells =3D <1>; clocks =3D <&scmi_clk CK_SCMI_HSE>, <&scmi_clk CK_SCMI_HSI>, <&scmi_clk CK_SCMI_MSI>, --=20 2.43.0 From nobody Sun Oct 5 23:37:45 2025 Received: from mx07-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E19C72737E3; Mon, 28 Jul 2025 15:33:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=91.207.212.93 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753716805; cv=none; b=feRmSGkBsCBGhDuG5QxsU8KRcOt39LMMTJXk6ILjFFLr65Era85jIAR4N3WAJXqCgrB35xvK/XBb26jv4IxUj9wGMHzfDih13gFy4amMr3ZuHLIfjWQOj2Yz3jOiQA2mgiAp7ecGGgCvA60N46Sv/FTA4Ek1fIT4MDYC4YY4iMU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753716805; c=relaxed/simple; bh=jGHdlPDPgRl3zHHXOBwPecdX4WGrpsFr1LIBkIRGRH8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=pSjm0bYPaZdt6CPbiBsagkZY2XwYffMDq/QRDsnCRVMuK6VwdvLPDyzhQMuad3QbLkPFmpzULlrQHc8Rw0JywGYbRYPn3m4RmxgKm4jWUOQWdKzkUZA2+bCHk+eyl/FZkIBrUv7OuDWZQ3jn+80Xs8CwE3QDCD5CcHNm6OhZRrw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com; spf=pass smtp.mailfrom=foss.st.com; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b=BebP7Q8i; arc=none smtp.client-ip=91.207.212.93 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=foss.st.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b="BebP7Q8i" Received: from pps.filterd (m0046661.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 56SFJYC7002038; Mon, 28 Jul 2025 17:33:04 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=selector1; bh= sFO58SReFVuxEFbzJCY7/99Yb/ix2l4hLRcgY20Xn6I=; b=BebP7Q8i/aAPFB7e V2mKBy1SCIloCcfnxkOvmf0R/DiX+mqfDOC7YqZiqjOQG3e04YIjS8x2GshgpEjy oygXML7k5d5Bk4PF2MfjUVeZUANiCOw7Trdz2hIY7JatmdM1fvpatIUXXP/jU8Q1 m9h50oqL9tNaAbxu2QFyvBkh0ezl3j96emOXaQM4UUV5yN81UWfqySZaQ8ZCiBBo OJFxoTm7ZabW9sDeCtZki1BeFgXS6jaPRXBeZG18dX7Hdlhyqq/Q1RCV2T44quKE 5hgPURngFGQqMi9SXRjMPjs1vPckqx9f6LIHr62/sXAdEHM73x9aYbwpwRi4yo6a GR6tEA== Received: from beta.dmz-ap.st.com (beta.dmz-ap.st.com [138.198.100.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 484nwggdvh-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 28 Jul 2025 17:33:04 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 5C0FA40049; Mon, 28 Jul 2025 17:31:14 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 78256787C22; Mon, 28 Jul 2025 17:29:54 +0200 (CEST) Received: from localhost (10.252.23.100) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Mon, 28 Jul 2025 17:29:54 +0200 From: =?utf-8?q?Cl=C3=A9ment_Le_Goffic?= Date: Mon, 28 Jul 2025 17:29:36 +0200 Subject: [PATCH v5 05/20] dt-bindings: memory: factorise LPDDR props into SDRAM props Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250728-ddrperfm-upstream-v5-5-03f1be8ad396@foss.st.com> References: <20250728-ddrperfm-upstream-v5-0-03f1be8ad396@foss.st.com> In-Reply-To: <20250728-ddrperfm-upstream-v5-0-03f1be8ad396@foss.st.com> To: Will Deacon , Mark Rutland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Philipp Zabel , Jonathan Corbet , Gatien Chevallier , Michael Turquette , Stephen Boyd , Gabriel Fernandez , Krzysztof Kozlowski , Le Goffic , Julius Werner CC: , , , , , , , =?utf-8?q?Cl=C3=A9ment_Le_Goffic?= X-Mailer: b4 0.15-dev-8018a X-ClientProxiedBy: SHFCAS1NODE2.st.com (10.75.129.73) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-28_03,2025-07-28_01,2025-03-28_01 LPDDR and DDR bindings are SDRAM types and are likely to share the same properties (at least for density, io-width and reg). To avoid bindings duplication, factorise the properties. The compatible description has been updated because the MR (Mode registers) used to get manufacturer ID and revision ID are not present in case of DDR. Those information should be in a SPD (Serial Presence Detect) EEPROM in case of DIMM module or are known in case of soldered memory chips as they are in the datasheet of the memory chips. Signed-off-by: Cl=C3=A9ment Le Goffic --- .../memory-controllers/ddr/jedec,lpddr-props.yaml | 74 ------------------ .../memory-controllers/ddr/jedec,lpddr2.yaml | 2 +- .../memory-controllers/ddr/jedec,lpddr3.yaml | 2 +- .../memory-controllers/ddr/jedec,lpddr4.yaml | 2 +- .../memory-controllers/ddr/jedec,lpddr5.yaml | 2 +- .../memory-controllers/ddr/jedec,sdram-props.yaml | 91 ++++++++++++++++++= ++++ 6 files changed, 95 insertions(+), 78 deletions(-) diff --git a/Documentation/devicetree/bindings/memory-controllers/ddr/jedec= ,lpddr-props.yaml b/Documentation/devicetree/bindings/memory-controllers/dd= r/jedec,lpddr-props.yaml deleted file mode 100644 index 30267ce70124..000000000000 --- a/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr-= props.yaml +++ /dev/null @@ -1,74 +0,0 @@ -# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr-prop= s.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: Common properties for LPDDR types - -description: - Different LPDDR types generally use the same properties and only differ = in the - range of legal values for each. This file defines the common parts that = can be - reused for each type. Nodes using this schema should generally be nested= under - an LPDDR channel node. - -maintainers: - - Krzysztof Kozlowski - -properties: - compatible: - description: - Compatible strings can be either explicit vendor names and part numb= ers - (e.g. elpida,ECB240ABACN), or generated strings of the form - lpddrX-YY,ZZZZ where X is the LPDDR version, YY is the manufacturer = ID - (from MR5) and ZZZZ is the revision ID (from MR6 and MR7). Both IDs = are - formatted in lower case hexadecimal representation with leading zero= es. - The latter form can be useful when LPDDR nodes are created at runtim= e by - boot firmware that doesn't have access to static part number informa= tion. - - reg: - description: - The rank number of this LPDDR rank when used as a subnode to an LPDDR - channel. - minimum: 0 - maximum: 3 - - revision-id: - $ref: /schemas/types.yaml#/definitions/uint32-array - description: - Revision IDs read from Mode Register 6 and 7. One byte per uint32 ce= ll (i.e. ). - maxItems: 2 - items: - minimum: 0 - maximum: 255 - - density: - $ref: /schemas/types.yaml#/definitions/uint32 - description: - Density in megabits of SDRAM chip. Decoded from Mode Register 8. - enum: - - 64 - - 128 - - 256 - - 512 - - 1024 - - 2048 - - 3072 - - 4096 - - 6144 - - 8192 - - 12288 - - 16384 - - 24576 - - 32768 - - io-width: - $ref: /schemas/types.yaml#/definitions/uint32 - description: - IO bus width in bits of SDRAM chip. Decoded from Mode Register 8. - enum: - - 8 - - 16 - - 32 - -additionalProperties: true diff --git a/Documentation/devicetree/bindings/memory-controllers/ddr/jedec= ,lpddr2.yaml b/Documentation/devicetree/bindings/memory-controllers/ddr/jed= ec,lpddr2.yaml index a237bc259273..704bbc562528 100644 --- a/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr2= .yaml +++ b/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr2= .yaml @@ -10,7 +10,7 @@ maintainers: - Krzysztof Kozlowski =20 allOf: - - $ref: jedec,lpddr-props.yaml# + - $ref: jedec,sdram-props.yaml# =20 properties: compatible: diff --git a/Documentation/devicetree/bindings/memory-controllers/ddr/jedec= ,lpddr3.yaml b/Documentation/devicetree/bindings/memory-controllers/ddr/jed= ec,lpddr3.yaml index e328a1195ba6..0d28df3d2bfa 100644 --- a/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr3= .yaml +++ b/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr3= .yaml @@ -10,7 +10,7 @@ maintainers: - Krzysztof Kozlowski =20 allOf: - - $ref: jedec,lpddr-props.yaml# + - $ref: jedec,sdram-props.yaml# =20 properties: compatible: diff --git a/Documentation/devicetree/bindings/memory-controllers/ddr/jedec= ,lpddr4.yaml b/Documentation/devicetree/bindings/memory-controllers/ddr/jed= ec,lpddr4.yaml index a078892fecee..65aa07861453 100644 --- a/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr4= .yaml +++ b/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr4= .yaml @@ -10,7 +10,7 @@ maintainers: - Krzysztof Kozlowski =20 allOf: - - $ref: jedec,lpddr-props.yaml# + - $ref: jedec,sdram-props.yaml# =20 properties: compatible: diff --git a/Documentation/devicetree/bindings/memory-controllers/ddr/jedec= ,lpddr5.yaml b/Documentation/devicetree/bindings/memory-controllers/ddr/jed= ec,lpddr5.yaml index e441dac5f154..cf5d5a8e94b3 100644 --- a/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr5= .yaml +++ b/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr5= .yaml @@ -10,7 +10,7 @@ maintainers: - Krzysztof Kozlowski =20 allOf: - - $ref: jedec,lpddr-props.yaml# + - $ref: jedec,sdram-props.yaml# =20 properties: compatible: diff --git a/Documentation/devicetree/bindings/memory-controllers/ddr/jedec= ,sdram-props.yaml b/Documentation/devicetree/bindings/memory-controllers/dd= r/jedec,sdram-props.yaml new file mode 100644 index 000000000000..a02b5b41fe6c --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,sdram-= props.yaml @@ -0,0 +1,91 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,sdram-prop= s.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Common properties for SDRAM types + +description: + Different SDRAM types generally use the same properties and only differ = in the + range of legal values for each. This file defines the common parts that = can be + reused for each type. Nodes using this schema should generally be nested= under + a SDRAM channel node. + +maintainers: + - Krzysztof Kozlowski + +properties: + compatible: + description: | + Compatible strings can be either explicit vendor names and part numb= ers + (e.g. elpida,ECB240ABACN), or generated strings of the form + lpddrX,YY,ZZZZ or ddrX-YYYY,AAAA...,ZZZZ where X, Y, A and Z are in = lower + case hexadecimal with leading zeroes. + For LPDDR and DDR SDRAM, X is the SDRAM version (2, 3, 4, etc.). + For LPDDR SDRAM: + - YY is the manufacturer ID (from MR5), 1 byte + - ZZZZ is the revision ID (from MR6 and MR7), 2 bytes + For DDR4 SDRAM with SPD, according to JEDEC SPD4.1.2.L-6 : + - YYYY is the manufacturer ID, 2 bytes, from bytes 320 and 321 + - AAAA... is the part number, 20 bytes, from bytes 329 to 348 + - Z is the revision ID, 1 byte, from byte 349 + The former form is useful when the SDRAM vendor and part number are + known, such as when the SDRAM is soldered on the board. + + reg: + description: + The rank number of this memory rank when used as a subnode to an mem= ory + channel. + minimum: 0 + maximum: 3 + + revision-id: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: | + SDRAM revision ID: + - LPDDR SDRAM, decoded from Mode Register 6 and 7, always 2 bytes. + - DDR4 SDRAM, decoded from the SPD from byte 349 according to + JEDEC SPD4.1.2.L-6. + One byte per uint32 cell (i.e. ). + maxItems: 2 + items: + minimum: 0 + maximum: 255 + + density: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Density of SDRAM chip in megabits: + - LPDDR SDRAM, decoded from Mode Register 8. + - DDR4 SDRAM, decoded from the SPD from bits 3~0 of byte 4 accordi= ng to + JEDEC SPD4.1.2.L-6. + enum: + - 64 + - 128 + - 256 + - 512 + - 1024 + - 2048 + - 3072 + - 4096 + - 6144 + - 8192 + - 12288 + - 16384 + - 24576 + - 32768 + + io-width: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + IO bus width in bits of SDRAM chip: + - LPDDR SDRAM, decoded from Mode Register 8. + - DDR4 SDRAM, decoded from the SPD from bits 2~0 of byte 12 accord= ing to + JEDEC SPD4.1.2.L-6. + enum: + - 8 + - 16 + - 32 + +additionalProperties: true --=20 2.43.0 From nobody Sun Oct 5 23:37:45 2025 Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 42AC370813; Mon, 28 Jul 2025 15:33:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.132.182.106 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753716793; cv=none; b=ssoBsbwkKevteA9yh+uUr4SGgHPO1OAFPstGXoKFceJph6YDv+ys3/W4SjgPx4h+TH/tmUC3qT7dmGvzFHAtuYMti2yvmeoZTamKeIYuieG4a1lbTyKbhzl5JqJIc2qkpaduuiUNyca/GwvouFRumvLhXx3rGyKRQDGer4TLCUM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753716793; c=relaxed/simple; bh=GpUvhJh1CksJc5XwesN3iux5G5ewRDbAuRXtWU52rJo=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=W6VX6q/vJ2wIXJS+mT/uFBwA6muiRXcfTo0JOd2sTSKR0kk/FlxJgxaNwHiiQ2NwD+tIdT1UKt8ZjGjZOpyPL8VT7RgTDI/iaQU+AOH3nSe8mTVzXeuM9AkM34oyMxkU4dd3ii4bIAVFtY+fKWKLNUl6urebW63uHhPYNPOsgsg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com; spf=pass smtp.mailfrom=foss.st.com; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b=BIJYTa99; arc=none smtp.client-ip=185.132.182.106 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=foss.st.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b="BIJYTa99" Received: from pps.filterd (m0288072.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 56SDnfmq008418; Mon, 28 Jul 2025 17:32:52 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=selector1; bh= a7LWlOLtHEVsw7QyER6FfjOKmrZdqB2/hdIwi6Hbs9U=; b=BIJYTa99Mpig0rQc wd+FwDNdRmK1zEh5JSgDPnTn9UH+2V80VAbm09FKd9sUjx1XU9Sfncy0wrTL5KHA r4vzSz0kBwT93R8JDq95SOocQkcJsM4s2CrsX3f8EF0m+JoZgfzoZ1Zy8ObRilei JTeoLfJ4meHaI8vR3KL8G3IZQ+rXmn6MgFriiSJ6LCE5ioYCmhqCK+OvbRMX5B+R HvTYi8on1jPP1fxNHWOB9jSEqHN3WhhLE8PkhqiUQTTz/rMAc3tTBOUQCnVCoMyh I9wB2++t/tELyOfJ2Av5cDFVr1AtofHCuvud/O7DPuxFQ3J5GppxcldBYU45sDkp Kbb9Cw== Received: from beta.dmz-ap.st.com (beta.dmz-ap.st.com [138.198.100.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 484memha9y-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 28 Jul 2025 17:32:52 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id F3E114004B; Mon, 28 Jul 2025 17:31:17 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 8C6F8787C26; Mon, 28 Jul 2025 17:29:55 +0200 (CEST) Received: from localhost (10.252.23.100) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Mon, 28 Jul 2025 17:29:55 +0200 From: =?utf-8?q?Cl=C3=A9ment_Le_Goffic?= Date: Mon, 28 Jul 2025 17:29:37 +0200 Subject: [PATCH v5 06/20] dt-bindings: memory: introduce DDR4 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250728-ddrperfm-upstream-v5-6-03f1be8ad396@foss.st.com> References: <20250728-ddrperfm-upstream-v5-0-03f1be8ad396@foss.st.com> In-Reply-To: <20250728-ddrperfm-upstream-v5-0-03f1be8ad396@foss.st.com> To: Will Deacon , Mark Rutland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Philipp Zabel , Jonathan Corbet , Gatien Chevallier , Michael Turquette , Stephen Boyd , Gabriel Fernandez , Krzysztof Kozlowski , Le Goffic , Julius Werner CC: , , , , , , , =?utf-8?q?Cl=C3=A9ment_Le_Goffic?= X-Mailer: b4 0.15-dev-8018a X-ClientProxiedBy: SHFCAS1NODE2.st.com (10.75.129.73) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-28_03,2025-07-28_01,2025-03-28_01 Introduce JEDEC compliant DDR bindings, that use new memory-props binding. Signed-off-by: Cl=C3=A9ment Le Goffic --- .../memory-controllers/ddr/jedec,ddr4.yaml | 34 ++++++++++++++++++= ++++ 1 file changed, 34 insertions(+) diff --git a/Documentation/devicetree/bindings/memory-controllers/ddr/jedec= ,ddr4.yaml b/Documentation/devicetree/bindings/memory-controllers/ddr/jedec= ,ddr4.yaml new file mode 100644 index 000000000000..f457066a2f8b --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,ddr4.y= aml @@ -0,0 +1,34 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,ddr4.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: DDR3 SDRAM compliant to JEDEC JESD79-4D + +maintainers: + - Krzysztof Kozlowski + +allOf: + - $ref: jedec,sdram-props.yaml# + +properties: + compatible: + items: + - pattern: "^ddr4-[0-9a-f]{2},[0-9a-f]{1}$" + - const: jedec,ddr4 + +required: + - compatible + - density + - io-width + +unevaluatedProperties: false + +examples: + - | + ddr { + compatible =3D "ddr4-ff,f", "jedec,ddr4"; + density =3D <8192>; + io-width =3D <8>; + }; --=20 2.43.0 From nobody Sun Oct 5 23:37:45 2025 Received: from mx07-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 60E6C275AFA; Mon, 28 Jul 2025 15:33:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=91.207.212.93 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753716811; cv=none; b=G8XgBuKEN6Ly5j9OvTcBRxHrxPhjGtqNnDhiHuIhUunqendD/ueyeXd6xBYi1IC4VO5cevgOt/I2aODRL8+l6pbHQ2F2XtaOp6SjL/LvjC9xnKjU2iZXDBfjXT5020sdlvApZdYnOSERdrlSRPyT47s6dpsX4bejuRxBG37KmDU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753716811; c=relaxed/simple; bh=Exmo5+oMsMm5kPrXFjurcIOliaVFCgS/LENRBImhl+I=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=TEV6Dd6xLQ22szffP0UUOJgMdhAWYtstkdTb4qd3ewQhUqXAV6Krkxgi8tPxuthc9+ycJLCrt7vxFNKDTRaYwMGx9SJGvi4t5F6WViyYKXMUwSgndReJJ1QoHnhV0CFfCklO3GqVDxyFT1neQGo7ZgdJQKGyX/wZ9zIH6l/lCco= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com; spf=pass smtp.mailfrom=foss.st.com; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b=7dilj+8Z; arc=none smtp.client-ip=91.207.212.93 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=foss.st.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b="7dilj+8Z" Received: from pps.filterd (m0046660.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 56SFO4l8018609; Mon, 28 Jul 2025 17:33:11 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=selector1; bh= akqUQfJc807kCu0sYZi5OCGTzmARlWNMPI99bkotwi0=; b=7dilj+8Zs7ihZIQc Ihp/1PbRvQgIHI3Ca56w6PwxLblrlP4n4TbDU2qFGeATNqJMyZvWn9oBm3AhDkad fR7wH9ht3F330/nw8lw4bq/9kNA+EnhZsh7MD/wsZcSB+bwVHOVftUNxV45sYc4H Ss5exKH0SDg3E8fLIYQw3EUb7ISoKbALn+Jko4bte7QfZuVjqKftNKPKadkXZSnl dTgW/8BFv8sIMlyyQdOB8vLjaXaaeHotLjmTj0Xkv/XFfMsjD3x6UjPKQuRXDz5N Rnbhz4GmzeleQ/jq79uoYL9gtluXC6VmPcUEpFTSIQ5U91aESV3QcikZoRsnBcxV uFSd/w== Received: from beta.dmz-ap.st.com (beta.dmz-ap.st.com [138.198.100.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 484m590qbv-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 28 Jul 2025 17:33:10 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id C251F4004C; Mon, 28 Jul 2025 17:31:26 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id A563478C900; Mon, 28 Jul 2025 17:29:56 +0200 (CEST) Received: from localhost (10.252.23.100) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Mon, 28 Jul 2025 17:29:56 +0200 From: =?utf-8?q?Cl=C3=A9ment_Le_Goffic?= Date: Mon, 28 Jul 2025 17:29:38 +0200 Subject: [PATCH v5 07/20] dt-bindings: memory: factorise LPDDR channel binding into SDRAM channel Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250728-ddrperfm-upstream-v5-7-03f1be8ad396@foss.st.com> References: <20250728-ddrperfm-upstream-v5-0-03f1be8ad396@foss.st.com> In-Reply-To: <20250728-ddrperfm-upstream-v5-0-03f1be8ad396@foss.st.com> To: Will Deacon , Mark Rutland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Philipp Zabel , Jonathan Corbet , Gatien Chevallier , Michael Turquette , Stephen Boyd , Gabriel Fernandez , Krzysztof Kozlowski , Le Goffic , Julius Werner CC: , , , , , , , =?utf-8?q?Cl=C3=A9ment_Le_Goffic?= X-Mailer: b4 0.15-dev-8018a X-ClientProxiedBy: SHFCAS1NODE2.st.com (10.75.129.73) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-28_03,2025-07-28_01,2025-03-28_01 LPDDR, DDR and so SDRAM channels exist and share the same properties, they have a compatible, ranks, and an io-width. Signed-off-by: Cl=C3=A9ment Le Goffic Reviewed-by: Rob Herring (Arm) --- ...lpddr-channel.yaml =3D> jedec,sdram-channel.yaml} | 23 +++++++++++-----= ------ 1 file changed, 12 insertions(+), 11 deletions(-) diff --git a/Documentation/devicetree/bindings/memory-controllers/ddr/jedec= ,lpddr-channel.yaml b/Documentation/devicetree/bindings/memory-controllers/= ddr/jedec,sdram-channel.yaml similarity index 83% rename from Documentation/devicetree/bindings/memory-controllers/ddr/jedec,= lpddr-channel.yaml rename to Documentation/devicetree/bindings/memory-controllers/ddr/jedec,sd= ram-channel.yaml index 34b5bd153f63..9892da520fe4 100644 --- a/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr-= channel.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,sdram-= channel.yaml @@ -1,16 +1,17 @@ # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- -$id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr-chan= nel.yaml# +$id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,sdram-chan= nel.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# =20 -title: LPDDR channel with chip/rank topology description +title: SDRAM channel with chip/rank topology description =20 description: - An LPDDR channel is a completely independent set of LPDDR pins (DQ, CA, = CS, - CK, etc.) that connect one or more LPDDR chips to a host system. The main - purpose of this node is to overall LPDDR topology of the system, includi= ng the - amount of individual LPDDR chips and the ranks per chip. + A memory channel of SDRAM memory like DDR SDRAM or LPDDR SDRAM is a comp= letely + independent set of pins (DQ, CA, CS, CK, etc.) that connect one or more = memory + chips to a host system. The main purpose of this node is to overall memo= ry + topology of the system, including the amount of individual memory chips = and + the ranks per chip. =20 maintainers: - Julius Werner @@ -26,14 +27,14 @@ properties: io-width: description: The number of DQ pins in the channel. If this number is different - from (a multiple of) the io-width of the LPDDR chip, that means that + from (a multiple of) the io-width of the SDRAM chip, that means that multiple instances of that type of chip are wired in parallel on this channel (with the channel's DQ pins split up between the different chips, and the CA, CS, etc. pins of the different chips all shorted together). This means that the total physical memory controlled by a channel is equal to the sum of the densities of each rank on the - connected LPDDR chip, times the io-width of the channel divided by - the io-width of the LPDDR chip. + connected SDRAM chip, times the io-width of the channel divided by + the io-width of the SDRAM chip. enum: - 8 - 16 @@ -51,8 +52,8 @@ patternProperties: "^rank@[0-9]+$": type: object description: - Each physical LPDDR chip may have one or more ranks. Ranks are - internal but fully independent sub-units of the chip. Each LPDDR bus + Each physical SDRAM chip may have one or more ranks. Ranks are + internal but fully independent sub-units of the chip. Each SDRAM bus transaction on the channel targets exactly one rank, based on the state of the CS pins. Different ranks may have different densities a= nd timing requirements. --=20 2.43.0 From nobody Sun Oct 5 23:37:45 2025 Received: from mx08-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 58B3A273D88; Mon, 28 Jul 2025 15:33:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=91.207.212.93 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753716817; cv=none; b=PBSUgLHYbKe0AueRKC6E90tGoUNdA3EcZv8jMNQeihM7vcmzOKKF1FIs+fjHpAtjwDsNWJJUcRc7YuNBeePJtwZuYdkvleDdkFT2NHM8drgoBpg2cZOYJJfrm6/pw7iro8Y6BPvqpBLH9MHfGqAMb/7DcCwl/fiNywfcZ1ng2Qo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753716817; c=relaxed/simple; bh=6eYIqJXGRaSBZCkYLZHJmaTRLPJfmPNxHldsWV4y7u0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=oHRdkUluuCnilxtjCv3AAXajGHHOaO1VwWT0IHMpduXyAp5bpdOoPuK10AqavDdp5AgNba2taISjqpKvqRPiQ2XDetXu5Z/aIVh/JEegfnX5Zyv7fuC2sy+DC0QmaIfHdLFTd+1Se2EL6+F08IWFOsW1bROCVl5eLwjWD4vVeEw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com; spf=pass smtp.mailfrom=foss.st.com; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b=Lf5P0Kj7; arc=none smtp.client-ip=91.207.212.93 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=foss.st.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b="Lf5P0Kj7" Received: from pps.filterd (m0369457.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 56SFWgHD031142; Mon, 28 Jul 2025 17:33:15 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=selector1; bh= JdpWMONuLacNIbyReTtl5COFJvZED0p6KDWBUgWc1mA=; b=Lf5P0Kj7bZi6paux bcMzHfpqPE51NdqS5NHKUG5t4opC3P6o2ww3QZQa+Fp8LJ8bUIbInWoHd9YLEOdf wTjRyIQZ1YOdIdrOlrxfaCtoOgrM66JgMlhh0gYpGGH8bJ+RXNswD/wqEKrfReu7 4m577NZKtUT+zH6RyG2VoavRB74o/wk0rlN0GToThjO/LTCa9nyINP666gvMYGzf GgNJS8lmPhSJ7ODKkeateem2dkGTHCz564+XXXC8MShTveIxo5nanELV8uqSIx/n YH9PIMJ+FB0DJjOiU44zWY+qgWsiSXhILTYZ1uHCZppwT9XAHETdkDwybAKB/7O0 cVm18A== Received: from beta.dmz-ap.st.com (beta.dmz-ap.st.com [138.198.100.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 4859yndymm-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 28 Jul 2025 17:33:15 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id C9EF14004D; Mon, 28 Jul 2025 17:31:26 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id AF54A787C3E; Mon, 28 Jul 2025 17:29:57 +0200 (CEST) Received: from localhost (10.252.23.100) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Mon, 28 Jul 2025 17:29:57 +0200 From: =?utf-8?q?Cl=C3=A9ment_Le_Goffic?= Date: Mon, 28 Jul 2025 17:29:39 +0200 Subject: [PATCH v5 08/20] dt-binding: memory: add DDR4 channel compatible Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250728-ddrperfm-upstream-v5-8-03f1be8ad396@foss.st.com> References: <20250728-ddrperfm-upstream-v5-0-03f1be8ad396@foss.st.com> In-Reply-To: <20250728-ddrperfm-upstream-v5-0-03f1be8ad396@foss.st.com> To: Will Deacon , Mark Rutland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Philipp Zabel , Jonathan Corbet , Gatien Chevallier , Michael Turquette , Stephen Boyd , Gabriel Fernandez , Krzysztof Kozlowski , Le Goffic , Julius Werner CC: , , , , , , , =?utf-8?q?Cl=C3=A9ment_Le_Goffic?= X-Mailer: b4 0.15-dev-8018a X-ClientProxiedBy: SHFCAS1NODE2.st.com (10.75.129.73) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-28_03,2025-07-28_01,2025-03-28_01 Add in the memory channel binding the DDR4 compatible to support DDR4 memory channel. Signed-off-by: Cl=C3=A9ment Le Goffic Reviewed-by: Rob Herring (Arm) --- .../bindings/memory-controllers/ddr/jedec,sdram-channel.yaml | 10 ++++++= ++++ 1 file changed, 10 insertions(+) diff --git a/Documentation/devicetree/bindings/memory-controllers/ddr/jedec= ,sdram-channel.yaml b/Documentation/devicetree/bindings/memory-controllers/= ddr/jedec,sdram-channel.yaml index 9892da520fe4..866af40b654d 100644 --- a/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,sdram-= channel.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,sdram-= channel.yaml @@ -19,6 +19,7 @@ maintainers: properties: compatible: enum: + - jedec,ddr4-channel - jedec,lpddr2-channel - jedec,lpddr3-channel - jedec,lpddr4-channel @@ -61,6 +62,15 @@ patternProperties: - reg =20 allOf: + - if: + properties: + compatible: + contains: + const: jedec,ddr4-channel + then: + patternProperties: + "^rank@[0-9]+$": + $ref: /schemas/memory-controllers/ddr/jedec,ddr4.yaml# - if: properties: compatible: --=20 2.43.0 From nobody Sun Oct 5 23:37:45 2025 Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 39F00274B4C; Mon, 28 Jul 2025 15:33:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.132.182.106 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753716796; cv=none; b=T8CdevDxgbhbsncYbdpo/i2nbSTVFRAmyXg4rS4A+C+SzpWNHivoRwqj2muTbU5faPfo8ebRq1viFCgtR20EoUWUKMLiePz6WKkRT0op9Ir+E4uWr3vYivvmmCAdvXYoaxVzdxuhMec/anC7hi+NFwxn8ls7ZwhIO8K2uI9C6M4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753716796; c=relaxed/simple; bh=p6/kdveeT+plI/0Dtsc/AlwljExz9cpevWGu/BpUGD8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=JlOUNBz5VhTy9zWcyZWTTrNqlwUwYiOEERnYG7EqMY7Hf/U9E5Hsq9sFQI2cZNiQq0xgjflMKnbWtu9YVgwe4qNK4qMIxnESovC/rqQwJ5ojbslR76TpiD1Nf7izVmhQ+dXCmkmgg5SHm6oZhOyCLVggoc/7Ynph1cm3+5zgt7k= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com; spf=pass smtp.mailfrom=foss.st.com; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b=m4Z6PWoz; arc=none smtp.client-ip=185.132.182.106 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=foss.st.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b="m4Z6PWoz" Received: from pps.filterd (m0369458.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 56SEnTOO026846; Mon, 28 Jul 2025 17:32:59 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=selector1; bh= 9SVEF8WXui/rvJlaHwlNLMXiePzshiHlU6XnxEDuFv0=; b=m4Z6PWozFDBx5wz0 q0sxlxg4Hqxyssrn6cFzPhTNXjEc7STfU3eqmGsgEwdd6UycwG4cF3MY3zGDP6HI LnCw4uWJjPEbP/W+NLeT3n6kNqBdlaL9F5R+glx9qFuYwMZE2gb6Fxewi1i1njMc IVDu3SlEZYX/QsBf1MkHyBvYeslBGMU1a+E7xgZ9/a/NBiAp0OKkXqvR/V1L0i+2 umNUwvk/aMls6d6iF7X1Ut7x1+A2G7tqOvrlJkjHAgUDzmZGcPAjQZzx4p8v9z3/ Xi0P6em/UFcpvzSQI/dxbf4iEnvkIhIqfTjz8h56ZfEN0g4rHAX8fw8JRvihR9Jj q4nghw== Received: from beta.dmz-ap.st.com (beta.dmz-ap.st.com [138.198.100.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 4858k4x9d5-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 28 Jul 2025 17:32:59 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 3AD1040050; Mon, 28 Jul 2025 17:31:41 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id B7D4678C902; Mon, 28 Jul 2025 17:29:58 +0200 (CEST) Received: from localhost (10.252.23.100) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Mon, 28 Jul 2025 17:29:58 +0200 From: =?utf-8?q?Cl=C3=A9ment_Le_Goffic?= Date: Mon, 28 Jul 2025 17:29:40 +0200 Subject: [PATCH v5 09/20] dt-bindings: memory: SDRAM channel: standardise node name Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250728-ddrperfm-upstream-v5-9-03f1be8ad396@foss.st.com> References: <20250728-ddrperfm-upstream-v5-0-03f1be8ad396@foss.st.com> In-Reply-To: <20250728-ddrperfm-upstream-v5-0-03f1be8ad396@foss.st.com> To: Will Deacon , Mark Rutland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Philipp Zabel , Jonathan Corbet , Gatien Chevallier , Michael Turquette , Stephen Boyd , Gabriel Fernandez , Krzysztof Kozlowski , Le Goffic , Julius Werner CC: , , , , , , , =?utf-8?q?Cl=C3=A9ment_Le_Goffic?= X-Mailer: b4 0.15-dev-8018a X-ClientProxiedBy: SHFCAS1NODE2.st.com (10.75.129.73) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-28_03,2025-07-28_01,2025-03-28_01 Add a pattern for sdram channel node name. Signed-off-by: Cl=C3=A9ment Le Goffic Reviewed-by: Rob Herring (Arm) --- .../bindings/memory-controllers/ddr/jedec,sdram-channel.yaml | 7 +++= ++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/memory-controllers/ddr/jedec= ,sdram-channel.yaml b/Documentation/devicetree/bindings/memory-controllers/= ddr/jedec,sdram-channel.yaml index 866af40b654d..5cdd8ef45100 100644 --- a/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,sdram-= channel.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,sdram-= channel.yaml @@ -17,6 +17,9 @@ maintainers: - Julius Werner =20 properties: + $nodename: + pattern: "sdram-channel-[0-9]+$" + compatible: enum: - jedec,ddr4-channel @@ -118,7 +121,7 @@ additionalProperties: false =20 examples: - | - lpddr-channel0 { + sdram-channel-0 { #address-cells =3D <1>; #size-cells =3D <0>; compatible =3D "jedec,lpddr3-channel"; @@ -133,7 +136,7 @@ examples: }; }; =20 - lpddr-channel1 { + sdram-channel-1 { #address-cells =3D <1>; #size-cells =3D <0>; compatible =3D "jedec,lpddr4-channel"; --=20 2.43.0 From nobody Sun Oct 5 23:37:45 2025 Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B2561275AF3; Mon, 28 Jul 2025 15:33:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.132.182.106 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753716810; cv=none; b=Q+DpWzgFFRUMA+iaQAHimZAD1ANwzsLpShqwroFfzfBVpHDRIfPg1M3rurcOQOFyvg4bO9Wk2tBkAirlbYh06GAEm+YRVaaCq43fhyHbDHFrvlKSFe7yBn0mSoejNXKapXtM/8LQQsLQCJOF2od0/jH/1Z956BSTr9d95LK+pnE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753716810; c=relaxed/simple; bh=9APzRer2x3mkcrGIpU+a1vSkFmKyOMuhmF+7EsK5nmI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=PmyndM3ocynXZTGFKuIDnJLDvAxybbhlhWOfFGO2rLZ6CCQ5R20cCxoT8ME5jTLFAuBi8xJcDi6pKVwsvXBDheYErBIx6qwRyjlirwKGB5LnyCUeAZQFsHnqyzRCJRxRrTdsipWPn1IrVB183KO35+SMIMOlJvu3TpwPrDbE524= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com; spf=pass smtp.mailfrom=foss.st.com; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b=j4b9ZTH5; arc=none smtp.client-ip=185.132.182.106 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=foss.st.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b="j4b9ZTH5" Received: from pps.filterd (m0369458.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 56SDod5e027633; Mon, 28 Jul 2025 17:33:05 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=selector1; bh= ywyodn+MUU5x5feIY64Qk8PDo7yNWWLhLu4bo6EHBlM=; b=j4b9ZTH5xJdfGrCG +y8IB1l3DncVgkxMhhgI6AgRFYoPlWKOlLbtXSl7vUS1YIahlXZQcBbQV6Bhusej IDBKfxTy+UXP/ucjkHW+I/RzSj2GclOeOUuBsV7R4+Eazq9H7h5J5ojzT81kBXTy 5O5tj2MQIvsuDQzsEa/v5vNUA9PU3D1Wenehy34yYoBoEVPNkaB6xhZqZPRiSsgO jiAzVGHLDvw2/rU3pyshjJumc9tv2SJDsDNvuJMjYXY9F93QvV3AMr6WFpRyX/SJ iZXOkr8+/cRpxe+pBJ76zVMdhA6fKzI2/GmBn+d5z5agSY/CM/Lp7WdnQTkb9fSx RTaocQ== Received: from beta.dmz-ap.st.com (beta.dmz-ap.st.com [138.198.100.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 4858k4x9du-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 28 Jul 2025 17:33:04 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 302564004F; Mon, 28 Jul 2025 17:31:38 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id BBD2E787C3D; Mon, 28 Jul 2025 17:29:59 +0200 (CEST) Received: from localhost (10.252.23.100) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Mon, 28 Jul 2025 17:29:59 +0200 From: =?utf-8?q?Cl=C3=A9ment_Le_Goffic?= Date: Mon, 28 Jul 2025 17:29:41 +0200 Subject: [PATCH v5 10/20] arm64: dts: st: add LPDDR channel to stm32mp257f-dk board Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250728-ddrperfm-upstream-v5-10-03f1be8ad396@foss.st.com> References: <20250728-ddrperfm-upstream-v5-0-03f1be8ad396@foss.st.com> In-Reply-To: <20250728-ddrperfm-upstream-v5-0-03f1be8ad396@foss.st.com> To: Will Deacon , Mark Rutland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Philipp Zabel , Jonathan Corbet , Gatien Chevallier , Michael Turquette , Stephen Boyd , Gabriel Fernandez , Krzysztof Kozlowski , Le Goffic , Julius Werner CC: , , , , , , , =?utf-8?q?Cl=C3=A9ment_Le_Goffic?= X-Mailer: b4 0.15-dev-8018a X-ClientProxiedBy: SHFCAS1NODE2.st.com (10.75.129.73) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-28_03,2025-07-28_01,2025-03-28_01 Add 32bits LPDDR4 channel to the stm32mp257f-dk board. Signed-off-by: Cl=C3=A9ment Le Goffic --- arch/arm64/boot/dts/st/stm32mp257f-dk.dts | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp257f-dk.dts b/arch/arm64/boot/dt= s/st/stm32mp257f-dk.dts index a278a1e3ce03..45ffa358c800 100644 --- a/arch/arm64/boot/dts/st/stm32mp257f-dk.dts +++ b/arch/arm64/boot/dts/st/stm32mp257f-dk.dts @@ -54,6 +54,13 @@ led-blue { }; }; =20 + lpddr_channel: sdram-channel-0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + compatible =3D "jedec,lpddr4-channel"; + io-width =3D <32>; + }; + memory@80000000 { device_type =3D "memory"; reg =3D <0x0 0x80000000 0x1 0x0>; --=20 2.43.0 From nobody Sun Oct 5 23:37:45 2025 Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 59B6A274FFE; Mon, 28 Jul 2025 15:35:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.132.182.106 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753716923; cv=none; b=ZkLVPT2EUeUaHQKsvlKT9vmc2eX4mLRNK9mm83Z+2d0RDKR9vg2E7B3xImUi8XIZfILhSWiJ9z/yqIFliZxx+vPxu00CrCf72Hw9P4QDDQV3M2ZZuqAmfzV9YeyvDIPcMrAPZWQJuv+cxt4pt8TG+6MG5eq1nND2pADu6YNw1ng= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753716923; c=relaxed/simple; bh=kFiMTzRSmHy3s7Z9kytNPzki5AZhpLb5pRQp1P6xpXU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=qfqNZGVBYTbdoBzPSlU8SaATb6r8xBfkdRSFDE7JXn68p9y1BKXlo3njcyx08NblDtNXckgmMJgt+XmrRDCxf5S394dAVbKrS7JbVlMLMY1gc8s1V1QAJS9+sO6QeEaPtyU/q8/Nu4OuwkmsIObnGUvQ9q5ysaci3+Xp+UCi/kE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com; spf=pass smtp.mailfrom=foss.st.com; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b=ESZzwVXB; arc=none smtp.client-ip=185.132.182.106 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=foss.st.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b="ESZzwVXB" Received: from pps.filterd (m0288072.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 56SFGvgr026171; Mon, 28 Jul 2025 17:35:04 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=selector1; bh= /PSRDUQqpavKCK+qf73ZwNuazN17nx7wwyTUKOPPPZQ=; b=ESZzwVXBSWBKFdIi 1FQAJgQuDBI+hzq+GovzGyXq5lFlgsCvTkp80fl93ldbyE8m9naKyIa9n1T/b9Ym L86ReaXNB1Q5nrOSvfy6zDBnyKmteZ7I+0nBPIwbiBvkftPsIb6q/ktgYn39xbdO MXzsA9Cblc/mpPwsjmB8V3XqyrVGxJ1gPUdaMxaI6dzZJfRVLS66umyM2x/ktnc/ Y2UY7QNHmaWCmtdSzfhSihnKP0G2PnYYlsZH5VgLfg5B3vk7URjTLT/zj1g7mTqN 7JP0097uygEfj7zJzZot+aJCzMRsec/QPqVSCavVNNEPUbNknvQ85xo+IYtp4bzR ax4ZBw== Received: from beta.dmz-ap.st.com (beta.dmz-ap.st.com [138.198.100.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 484memhaje-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 28 Jul 2025 17:35:04 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id DC46240046; Mon, 28 Jul 2025 17:33:37 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id C6BDF78C903; Mon, 28 Jul 2025 17:30:00 +0200 (CEST) Received: from localhost (10.252.23.100) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Mon, 28 Jul 2025 17:30:00 +0200 From: =?utf-8?q?Cl=C3=A9ment_Le_Goffic?= Date: Mon, 28 Jul 2025 17:29:42 +0200 Subject: [PATCH v5 11/20] arm64: dts: st: add DDR channel to stm32mp257f-ev1 board Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250728-ddrperfm-upstream-v5-11-03f1be8ad396@foss.st.com> References: <20250728-ddrperfm-upstream-v5-0-03f1be8ad396@foss.st.com> In-Reply-To: <20250728-ddrperfm-upstream-v5-0-03f1be8ad396@foss.st.com> To: Will Deacon , Mark Rutland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Philipp Zabel , Jonathan Corbet , Gatien Chevallier , Michael Turquette , Stephen Boyd , Gabriel Fernandez , Krzysztof Kozlowski , Le Goffic , Julius Werner CC: , , , , , , , =?utf-8?q?Cl=C3=A9ment_Le_Goffic?= X-Mailer: b4 0.15-dev-8018a X-ClientProxiedBy: SHFCAS1NODE2.st.com (10.75.129.73) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-28_03,2025-07-28_01,2025-03-28_01 Add 32bits DDR4 channel to the stm32mp257f-dk board. Signed-off-by: Cl=C3=A9ment Le Goffic --- arch/arm64/boot/dts/st/stm32mp257f-ev1.dts | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts b/arch/arm64/boot/d= ts/st/stm32mp257f-ev1.dts index 2f561ad40665..e11ce66be948 100644 --- a/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts +++ b/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts @@ -41,6 +41,13 @@ pad_clk: pad-clk { }; }; =20 + ddr_channel: sdram-channel-0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + compatible =3D "jedec,ddr4-channel"; + io-width =3D <32>; + }; + imx335_2v9: regulator-2v9 { compatible =3D "regulator-fixed"; regulator-name =3D "imx335-avdd"; --=20 2.43.0 From nobody Sun Oct 5 23:37:45 2025 Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DA32E2750F0; Mon, 28 Jul 2025 15:35:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.132.182.106 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753716923; cv=none; b=m1j9Ic73YHX5vojHYOhN12tO3lt/Q74We0CLGPwjcXMpvQkPdhFmHZo2RvyvDmIWrNFK1RI1A6Z8LkhAYTVPNxp4miyfm4N/RwoBqNTfkwokldQEh9QO/r3oSwwW3uSsY+k+qXFts1V1LHJmIHFoBBIRvjEw8G5u8oZUP0E7sTk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753716923; c=relaxed/simple; bh=R8FUJBQeEnhRP8o3OLE/yDU2CDRIJGKJUpPw+CFl5Uc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=LDUpnCljfqRqf07Bpo19mSlVpo7HRDBNS9PkzGY9zE6AXhFQ1Sl5Kb0IblIfYkxrGwj03pEFrblN62FiAePDGIMegAgGg3iovA4VCwyKZ8jg4m/97aW+VTivXgq/JU1YN+fdVT4iDJogveBRHnTcCoHuTTegcINBJOweQVs9e6w= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com; spf=pass smtp.mailfrom=foss.st.com; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b=Xo8JKen4; arc=none smtp.client-ip=185.132.182.106 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=foss.st.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b="Xo8JKen4" Received: from pps.filterd (m0241204.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 56SDmqUh025850; Mon, 28 Jul 2025 17:35:04 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=selector1; bh= H6V/0Vtel7CGpYiJefJ3wfM3AtMizX6MiI5SBYa0KkU=; b=Xo8JKen4e7R2XUYE 1iMOf9BEougWjV9Egmv+lYSTRMrnRZRWWRg3+S3evLAsXqarZZEB2SNv+Ba8USqZ j9qqlF8pXqWn0Z9KL8/VXe8H0CzotxxCUBdyDN1DtDklYZVW3eY2sL/ED8RUYSWc Fxpomgt2wG1HNvmQVugkB+Cf0/1bhR+RmCu6AXXCOrvhJE+xoXGXb0qTyqMwReYU VKv1FsK00rHiUa+Bt+eojhfykFBW4W5/dQcB/Gu0rmNLu3Fgyynn7aL112tuUOqf dpQGE9b9a22Dwoypg75IvedQXSK36DpC0BpvAigiuBYrzRFcUjJbEMyRvqhG0/Vn uP0OvQ== Received: from beta.dmz-ap.st.com (beta.dmz-ap.st.com [138.198.100.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 484pc28wap-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 28 Jul 2025 17:35:04 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id DC96F40049; Mon, 28 Jul 2025 17:33:37 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id D223A78C908; Mon, 28 Jul 2025 17:30:01 +0200 (CEST) Received: from localhost (10.252.23.100) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Mon, 28 Jul 2025 17:30:01 +0200 From: =?utf-8?q?Cl=C3=A9ment_Le_Goffic?= Date: Mon, 28 Jul 2025 17:29:43 +0200 Subject: [PATCH v5 12/20] dt-bindings: perf: stm32: introduce DDRPERFM dt-bindings Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250728-ddrperfm-upstream-v5-12-03f1be8ad396@foss.st.com> References: <20250728-ddrperfm-upstream-v5-0-03f1be8ad396@foss.st.com> In-Reply-To: <20250728-ddrperfm-upstream-v5-0-03f1be8ad396@foss.st.com> To: Will Deacon , Mark Rutland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Philipp Zabel , Jonathan Corbet , Gatien Chevallier , Michael Turquette , Stephen Boyd , Gabriel Fernandez , Krzysztof Kozlowski , Le Goffic , Julius Werner CC: , , , , , , , =?utf-8?q?Cl=C3=A9ment_Le_Goffic?= X-Mailer: b4 0.15-dev-8018a X-ClientProxiedBy: SHFCAS1NODE2.st.com (10.75.129.73) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-28_03,2025-07-28_01,2025-03-28_01 DDRPERFM is the DDR Performance Monitor embedded in STM32MPU SoC. It allows to monitor DDR events that come from the DDR Controller such as read or write events. Signed-off-by: Cl=C3=A9ment Le Goffic --- .../devicetree/bindings/perf/st,stm32-ddr-pmu.yaml | 94 ++++++++++++++++++= ++++ 1 file changed, 94 insertions(+) diff --git a/Documentation/devicetree/bindings/perf/st,stm32-ddr-pmu.yaml b= /Documentation/devicetree/bindings/perf/st,stm32-ddr-pmu.yaml new file mode 100644 index 000000000000..1d97861e3d44 --- /dev/null +++ b/Documentation/devicetree/bindings/perf/st,stm32-ddr-pmu.yaml @@ -0,0 +1,94 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/perf/st,stm32-ddr-pmu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +maintainers: + - Cl=C3=A9ment Le Goffic + +title: STMicroelectronics STM32 DDR Performance Monitor (DDRPERFM) + +properties: + compatible: + oneOf: + - items: + - const: st,stm32mp131-ddr-pmu + - items: + - enum: + - st,stm32mp151-ddr-pmu + - const: st,stm32mp131-ddr-pmu + - items: + - const: st,stm32mp251-ddr-pmu + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + resets: + maxItems: 1 + + access-controllers: + minItems: 1 + maxItems: 2 + + memory-channel: + description: + The memory channel this DDRPERFM is attached to. + $ref: /schemas/types.yaml#/definitions/phandle + +required: + - compatible + - reg + +allOf: + - if: + properties: + compatible: + contains: + const: st,stm32mp131-ddr-pmu + then: + required: + - clocks + - resets + + - if: + properties: + compatible: + contains: + const: st,stm32mp251-ddr-pmu + then: + required: + - access-controllers + - memory-channel + +additionalProperties: false + +examples: + - | + #include + #include + + perf@5a007000 { + compatible =3D "st,stm32mp151-ddr-pmu", "st,stm32mp131-ddr-pmu"; + reg =3D <0x5a007000 0x400>; + clocks =3D <&rcc DDRPERFM>; + resets =3D <&rcc DDRPERFM_R>; + }; + + - | + ddr_channel: sdram-channel-0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + compatible =3D "jedec,ddr4-channel"; + io-width =3D <16>; + }; + + perf@48041000 { + compatible =3D "st,stm32mp251-ddr-pmu"; + reg =3D <0x48041000 0x400>; + access-controllers =3D <&rcc 104>; + memory-channel =3D <&ddr_channel>; + }; --=20 2.43.0 From nobody Sun Oct 5 23:37:45 2025 Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5DBB12750E2; Mon, 28 Jul 2025 15:35:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.132.182.106 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753716924; cv=none; b=Od0xW+pBdMM8TcdVc5x+ycbJJxmoUyMByOSr8ddI3IEiLNV6YwsQO3YaFKqS612uQa9t4QmdkhBGU2ftOD57ETTRPBXpWNGiUXmRMPXgSoZkIuM9ZeyqQa37NXG6aFThFc+rvQMm31GR9phYeRddsZ9eWBeB3IIyVi8bBvZE/8U= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753716924; c=relaxed/simple; bh=pgdJsHA0a8bFt5Oo+fYuhPYK4rvAnIVbS4PDq7zUK7o=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=r4K34ZdigDSYAUKafP783zsuZnVIeVLc1f9UH73xP3Uc4BxJ2IvfdP6v/79VebvZBTsx5aB3NXd1dhHhP+rrlqW8Wy1Z8ANh6AcT8qXa+HZoMocyVnI9H6ZaLSqPmO5pH3sgQydsGjWe96jcmvnqjbHID+wsot+U9EVtdbPkNZE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com; spf=pass smtp.mailfrom=foss.st.com; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b=SUxUuw96; arc=none smtp.client-ip=185.132.182.106 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=foss.st.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b="SUxUuw96" Received: from pps.filterd (m0241204.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 56SDmqUg025850; Mon, 28 Jul 2025 17:35:01 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=selector1; bh= xVB4qEO85iajsSx3lhjqdXRxta/jpUzhVfh9RXEmgDc=; b=SUxUuw96TSxC5Dmt NOCYp1+PsGVTvZ4JR3Mmf12+T6PZEH4kTgg16R4aIFIwqelXjKjTTIEWoCAzd4xh 1tDLDPqQUzdPtxmyEVAxHtbB5bj6lfTZ03CpAPQC/Arn5Eu2zkRVZ9hMmh4Y6jEQ scOoPFFNBY/E8KMaloqMteAg79JVIpO1zBctoAlGa15YxHn4VFC224oEs617xBjN 3O158YI8z6u8JopCruI34QdzKtSnK1/NJ7UTkjZkk8a8r5Y/fDnP4HJ7eDDlELR0 9iCmr1DgtQcBfQhF3WjBTxqSbVhwQaJV+MByYQiilFEi+xa2/3lC1ia9gwrsPxTK aplAdw== Received: from beta.dmz-ap.st.com (beta.dmz-ap.st.com [138.198.100.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 484pc28wae-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 28 Jul 2025 17:35:01 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 197184004F; Mon, 28 Jul 2025 17:33:38 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 056D078C90C; Mon, 28 Jul 2025 17:30:03 +0200 (CEST) Received: from localhost (10.252.23.100) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Mon, 28 Jul 2025 17:30:02 +0200 From: =?utf-8?q?Cl=C3=A9ment_Le_Goffic?= Date: Mon, 28 Jul 2025 17:29:44 +0200 Subject: [PATCH v5 13/20] perf: stm32: introduce DDRPERFM driver Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250728-ddrperfm-upstream-v5-13-03f1be8ad396@foss.st.com> References: <20250728-ddrperfm-upstream-v5-0-03f1be8ad396@foss.st.com> In-Reply-To: <20250728-ddrperfm-upstream-v5-0-03f1be8ad396@foss.st.com> To: Will Deacon , Mark Rutland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Philipp Zabel , Jonathan Corbet , Gatien Chevallier , Michael Turquette , Stephen Boyd , Gabriel Fernandez , Krzysztof Kozlowski , Le Goffic , Julius Werner CC: , , , , , , , =?utf-8?q?Cl=C3=A9ment_Le_Goffic?= X-Mailer: b4 0.15-dev-8018a X-ClientProxiedBy: SHFCAS1NODE2.st.com (10.75.129.73) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-28_03,2025-07-28_01,2025-03-28_01 Introduce the driver for the DDR Performance Monitor available on STM32MPU SoC. On STM32MP2 platforms, the DDRPERFM allows to monitor up to 8 DDR events that come from the DDR Controller such as read or write events. On STM32MP1 platforms, the DDRPERFM cannot monitor any event on any counter, there is a notion of set of events. Events from different sets cannot be monitored at the same time. The first chosen event selects the set. The set is coded in the first two bytes of the config value which is on 4 bytes. On STM32MP25x series, the DDRPERFM clock is shared with the DDR controller and may be secured by bootloaders. Access controllers allow to check access to a resource. Use the access controller defined in the devicetree to know about the access to the DDRPERFM clock. Signed-off-by: Cl=C3=A9ment Le Goffic --- drivers/perf/Kconfig | 11 + drivers/perf/Makefile | 1 + drivers/perf/stm32_ddr_pmu.c | 896 +++++++++++++++++++++++++++++++++++++++= ++++ 3 files changed, 908 insertions(+) diff --git a/drivers/perf/Kconfig b/drivers/perf/Kconfig index 278c929dc87a..5118535134ee 100644 --- a/drivers/perf/Kconfig +++ b/drivers/perf/Kconfig @@ -198,6 +198,17 @@ config QCOM_L3_PMU Adds the L3 cache PMU into the perf events subsystem for monitoring L3 cache events. =20 +config STM32_DDR_PMU + tristate "STM32 DDR PMU" + depends on ARCH_STM32 || COMPILE_TEST + default m + help + Provides support for the DDR performance monitor on STM32MPU platforms. + The monitor provides counters for memory related events. + It allows developers to analyze and optimize DDR performance. + Enabling this feature is useful for performance tuning and debugging me= mory + subsystem issues on supported hardware. + config THUNDERX2_PMU tristate "Cavium ThunderX2 SoC PMU UNCORE" depends on ARCH_THUNDER2 || COMPILE_TEST diff --git a/drivers/perf/Makefile b/drivers/perf/Makefile index de71d2574857..7f83b50feb71 100644 --- a/drivers/perf/Makefile +++ b/drivers/perf/Makefile @@ -20,6 +20,7 @@ obj-$(CONFIG_RISCV_PMU) +=3D riscv_pmu.o obj-$(CONFIG_RISCV_PMU_LEGACY) +=3D riscv_pmu_legacy.o obj-$(CONFIG_RISCV_PMU_SBI) +=3D riscv_pmu_sbi.o obj-$(CONFIG_STARFIVE_STARLINK_PMU) +=3D starfive_starlink_pmu.o +obj-$(CONFIG_STM32_DDR_PMU) +=3D stm32_ddr_pmu.o obj-$(CONFIG_THUNDERX2_PMU) +=3D thunderx2_pmu.o obj-$(CONFIG_XGENE_PMU) +=3D xgene_pmu.o obj-$(CONFIG_ARM_SPE_PMU) +=3D arm_spe_pmu.o diff --git a/drivers/perf/stm32_ddr_pmu.c b/drivers/perf/stm32_ddr_pmu.c new file mode 100644 index 000000000000..9547e2ae2578 --- /dev/null +++ b/drivers/perf/stm32_ddr_pmu.c @@ -0,0 +1,896 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2025, STMicroelectronics - All Rights Reserved + * Author: Cl=C3=A9ment Le Goffic for STMic= roelectronics. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define DRIVER_NAME "stm32_ddr_pmu" + +/* + * The PMU is able to freeze all counters and generate an interrupt when t= here + * is a counter overflow. But, relying on this means that we lose all the + * events that occur between the freeze and the interrupt handler executio= n. + * So we use a polling mechanism to avoid this lost of information. + * The fastest counter can overflow in ~7s @600MHz (that is the maximum DDR + * frequency supported on STM32MP257), so we poll in 3.5s intervals to ens= ure + * we don't reach this limit. + */ +#define POLL_MS 3500 + +#define DDRPERFM_CTRL 0x000 +#define DDRPERFM_CFG 0x004 +#define DDRPERFM_STATUS 0x008 +#define DDRPERFM_CLR 0x00C +#define DDRPERFM_TCNT 0x020 +#define DDRPERFM_EVCNT(X) (0x030 + 8 * (X)) + +#define DDRPERFM_MP2_CFG0 0x010 +#define DDRPERFM_MP2_CFG1 0x014 +#define DDRPERFM_MP2_CFG5 0x024 +#define DDRPERFM_MP2_DRAMINF 0x028 +#define DDRPERFM_MP2_EVCNT(X) (0x040 + 4 * (X)) +#define DDRPERFM_MP2_TCNT 0x060 +#define DDRPERFM_MP2_STATUS 0x080 + +#define MP1_STATUS_BUSY BIT(16) +#define MP2_STATUS_BUSY BIT(31) + +#define CTRL_START BIT(0) +#define CTRL_STOP BIT(1) + +#define CFG_SEL_MSK GENMASK(17, 16) +#define CFG_SEL_SHIFT 16 +#define CFG_EN_MSK GENMASK(3, 0) + +#define MP1_CLR_CNT GENMASK(3, 0) +#define MP1_CLR_TIME BIT(31) +#define MP2_CLR_CNT GENMASK(7, 0) +#define MP2_CLR_TIME BIT(8) + +/* 4 event counters plus 1 dedicated to time */ +#define MP1_CNT_NB (4 + 1) +/* Index of the time dedicated counter */ +#define MP1_TIME_CNT_IDX 4 + +/* 8 event counters plus 1 dedicated to time */ +#define MP2_CNT_NB (8 + 1) +/* Index of the time dedicated counter */ +#define MP2_TIME_CNT_IDX 8 +/* 4 event counters per register */ +#define MP2_CNT_SEL_PER_REG 4 + +/* Arbitrary value used to identify a time event */ +#define TIME_CNT 64 + +struct stm32_ddr_pmu_reg { + unsigned int reg; + u32 mask; +}; + +struct stm32_ddr_cnt { + int idx; + struct perf_event *evt; + struct list_head cnt_list; +}; + +struct stm32_ddr_pmu_regspec { + const struct stm32_ddr_pmu_reg stop; + const struct stm32_ddr_pmu_reg start; + const struct stm32_ddr_pmu_reg enable; + const struct stm32_ddr_pmu_reg status; + const struct stm32_ddr_pmu_reg clear_cnt; + const struct stm32_ddr_pmu_reg clear_time; + const struct stm32_ddr_pmu_reg cfg; + const struct stm32_ddr_pmu_reg cfg0; + const struct stm32_ddr_pmu_reg cfg1; + const struct stm32_ddr_pmu_reg dram_inf; + const struct stm32_ddr_pmu_reg counter_time; + const struct stm32_ddr_pmu_reg counter_evt[]; +}; + +struct stm32_ddr_pmu { + struct pmu pmu; + void __iomem *membase; + struct device *dev; + struct clk *clk; + const struct stm32_ddr_pmu_cfg *cfg; + struct hrtimer hrtimer; + ktime_t poll_period; + int selected_set; + u32 dram_type; + struct list_head counters[]; +}; + +struct stm32_ddr_pmu_cfg { + const struct stm32_ddr_pmu_regspec *regs; + const struct attribute_group **attribute; + u32 counters_nb; + u32 evt_counters_nb; + u32 time_cnt_idx; + struct stm32_ddr_cnt * (*get_counter)(struct stm32_ddr_pmu *p, struct per= f_event *e); +}; + +#define STM32_DDR_PMU_EVENT_NUMBER(group, index) (((group) << 8) | (index)) +#define STM32_DDR_PMU_GROUP_VALUE(event_number) ((event_number) >> 8) +#define STM32_DDR_PMU_EVENT_INDEX(event_number) ((event_number) & 0xFF) + +/* MP1 ddrperfm events */ +enum stm32_ddr_pmu_events_mp1 { + PERF_OP_IS_RD =3D STM32_DDR_PMU_EVENT_NUMBER(0, 0), + PERF_OP_IS_WR =3D STM32_DDR_PMU_EVENT_NUMBER(0, 1), + PERF_OP_IS_ACTIVATE =3D STM32_DDR_PMU_EVENT_NUMBER(0, 2), + CTL_IDLE =3D STM32_DDR_PMU_EVENT_NUMBER(0, 3), + PERF_HPR_REQ_WITH_NO_CREDIT =3D STM32_DDR_PMU_EVENT_NUMBER(1, 0), + PERF_LPR_REQ_WITH_NO_CREDIT =3D STM32_DDR_PMU_EVENT_NUMBER(1, 1), + CACTIVE_DDRC =3D STM32_DDR_PMU_EVENT_NUMBER(1, 3), + PERF_OP_IS_ENTER_POWERDOWN =3D STM32_DDR_PMU_EVENT_NUMBER(2, 0), + PERF_OP_IS_REFRESH =3D STM32_DDR_PMU_EVENT_NUMBER(2, 1), + PERF_SELFRESH_MODE =3D STM32_DDR_PMU_EVENT_NUMBER(2, 2), + DFI_LP_REQ =3D STM32_DDR_PMU_EVENT_NUMBER(2, 3), + PERF_HPR_XACT_WHEN_CRITICAL =3D STM32_DDR_PMU_EVENT_NUMBER(3, 0), + PERF_LPR_XACT_WHEN_CRITICAL =3D STM32_DDR_PMU_EVENT_NUMBER(3, 1), + PERF_WR_XACT_WHEN_CRITICAL =3D STM32_DDR_PMU_EVENT_NUMBER(3, 2), + DFI_LP_REQ_SCND =3D STM32_DDR_PMU_EVENT_NUMBER(3, 3), +}; + +/* MP2 ddrperfm events */ +enum stm32_ddr_pmu_events_mp2 { + DFI_IS_ACT =3D STM32_DDR_PMU_EVENT_NUMBER(0, 0), + DFI_IS_PREPB =3D STM32_DDR_PMU_EVENT_NUMBER(0, 1), + DFI_IS_PREAB =3D STM32_DDR_PMU_EVENT_NUMBER(0, 2), + DFI_IS_RD =3D STM32_DDR_PMU_EVENT_NUMBER(0, 3), + DFI_IS_RDA =3D STM32_DDR_PMU_EVENT_NUMBER(0, 4), + DFI_IS_WR =3D STM32_DDR_PMU_EVENT_NUMBER(0, 6), + DFI_IS_WRA =3D STM32_DDR_PMU_EVENT_NUMBER(0, 7), + DFI_IS_MWR =3D STM32_DDR_PMU_EVENT_NUMBER(0, 9), + DFI_IS_MWRA =3D STM32_DDR_PMU_EVENT_NUMBER(0, 10), + DFI_IS_MRW =3D STM32_DDR_PMU_EVENT_NUMBER(0, 12), + DFI_IS_MRR =3D STM32_DDR_PMU_EVENT_NUMBER(0, 13), + DFI_IS_REFPB =3D STM32_DDR_PMU_EVENT_NUMBER(0, 14), + DFI_IS_REFAB =3D STM32_DDR_PMU_EVENT_NUMBER(0, 15), + DFI_IS_MPC =3D STM32_DDR_PMU_EVENT_NUMBER(0, 16), + PERF_OP_IS_ACT =3D STM32_DDR_PMU_EVENT_NUMBER(0, 32), + PERF_OP_IS_RD_MP2 =3D STM32_DDR_PMU_EVENT_NUMBER(0, 33), + PERF_OP_IS_WR_MP2 =3D STM32_DDR_PMU_EVENT_NUMBER(0, 34), + PERF_OP_IS_MWR =3D STM32_DDR_PMU_EVENT_NUMBER(0, 35), + PERF_OP_IS_REF =3D STM32_DDR_PMU_EVENT_NUMBER(0, 36), + PERF_OP_IS_CRIT_REF =3D STM32_DDR_PMU_EVENT_NUMBER(0, 37), + PERF_OP_IS_SPEC_REF =3D STM32_DDR_PMU_EVENT_NUMBER(0, 38), + PERF_OP_IS_ZQCAL =3D STM32_DDR_PMU_EVENT_NUMBER(0, 39), + PERF_OP_IS_ENTER_POWDN =3D STM32_DDR_PMU_EVENT_NUMBER(0, 40), + PERF_OP_IS_ENTER_SELFREF =3D STM32_DDR_PMU_EVENT_NUMBER(0, 41), + PERF_OP_IS_PRE =3D STM32_DDR_PMU_EVENT_NUMBER(0, 42), + PERF_OP_IS_PRE_FOR_RDWR =3D STM32_DDR_PMU_EVENT_NUMBER(0, 43), + PERF_OP_IS_PRE_FOR_OTHERS =3D STM32_DDR_PMU_EVENT_NUMBER(0, 44), + PERF_OP_IS_RD_ACTIVATE =3D STM32_DDR_PMU_EVENT_NUMBER(0, 45), + PERF_HPR_REQ_WITH_NOCREDIT =3D STM32_DDR_PMU_EVENT_NUMBER(0, 48), + PERF_LPR_REQ_WITH_NOCREDIT =3D STM32_DDR_PMU_EVENT_NUMBER(0, 49), + PERF_HPR_XACT_WHEN_CRITICAL_MP2 =3D STM32_DDR_PMU_EVENT_NUMBER(0, 50), + PERF_LPR_XACT_WHEN_CRITICAL_MP2 =3D STM32_DDR_PMU_EVENT_NUMBER(0, 51), + PERF_WR_XACT_WHEN_CRITICAL_MP2 =3D STM32_DDR_PMU_EVENT_NUMBER(0, 52), + PERF_RDWR_TRANSITIONS =3D STM32_DDR_PMU_EVENT_NUMBER(0, 53), + PERF_WAR_HAZARD =3D STM32_DDR_PMU_EVENT_NUMBER(0, 54), + PERF_RAW_HAZARD =3D STM32_DDR_PMU_EVENT_NUMBER(0, 55), + PERF_WAW_HAZARD =3D STM32_DDR_PMU_EVENT_NUMBER(0, 56), + PERF_RANK =3D STM32_DDR_PMU_EVENT_NUMBER(0, 58), + PERF_READ_BYPASS =3D STM32_DDR_PMU_EVENT_NUMBER(0, 59), + PERF_ACT_BYPASS =3D STM32_DDR_PMU_EVENT_NUMBER(0, 60), + PERF_WINDOW_LIMIT_REACHED_RD =3D STM32_DDR_PMU_EVENT_NUMBER(0, 61), + PERF_WINDOW_LIMIT_REACHED_WR =3D STM32_DDR_PMU_EVENT_NUMBER(0, 62), + NO_EVENT =3D STM32_DDR_PMU_EVENT_NUMBER(0, 63), +}; + +enum stm32_ddr_pmu_memory_type { + STM32_DDR_PMU_LPDDR4, + STM32_DDR_PMU_LPDDR3, + STM32_DDR_PMU_DDR4, + STM32_DDR_PMU_DDR3, +}; + +static struct stm32_ddr_pmu *to_stm32_ddr_pmu(struct pmu *p) +{ + return container_of(p, struct stm32_ddr_pmu, pmu); +} + +static struct stm32_ddr_pmu *hrtimer_to_stm32_ddr_pmu(struct hrtimer *h) +{ + return container_of(h, struct stm32_ddr_pmu, hrtimer); +} + +static void stm32_ddr_start_counters(struct stm32_ddr_pmu *pmu) +{ + const struct stm32_ddr_pmu_regspec *r =3D pmu->cfg->regs; + + writel_relaxed(r->start.mask, pmu->membase + r->start.reg); +} + +static void stm32_ddr_stop_counters(struct stm32_ddr_pmu *pmu) +{ + const struct stm32_ddr_pmu_regspec *r =3D pmu->cfg->regs; + + writel_relaxed(r->stop.mask, pmu->membase + r->stop.reg); +} + +static void stm32_ddr_clear_time_counter(struct stm32_ddr_pmu *pmu) +{ + const struct stm32_ddr_pmu_regspec *r =3D pmu->cfg->regs; + + writel_relaxed(r->clear_time.mask, pmu->membase + r->clear_time.reg); +} + +static void stm32_ddr_clear_event_counter(struct stm32_ddr_pmu *pmu, struc= t stm32_ddr_cnt *counter) +{ + const struct stm32_ddr_pmu_regspec *r =3D pmu->cfg->regs; + + writel_relaxed(r->clear_cnt.mask & BIT(counter->idx), pmu->membase + r->c= lear_cnt.reg); +} + +static void stm32_ddr_clear_counter(struct stm32_ddr_pmu *pmu, struct stm3= 2_ddr_cnt *counter) +{ + const struct stm32_ddr_pmu_regspec *r =3D pmu->cfg->regs; + u32 status =3D readl_relaxed(pmu->membase + r->status.reg); + + if (counter->idx =3D=3D pmu->cfg->time_cnt_idx) + stm32_ddr_clear_time_counter(pmu); + else + stm32_ddr_clear_event_counter(pmu, counter); + + if (status & r->status.mask) + dev_err(pmu->dev, "Failed to clear counter %i because the PMU is busy\n", + counter->idx); +} + +static void stm32_ddr_counter_enable(struct stm32_ddr_pmu *pmu, struct stm= 32_ddr_cnt *counter) +{ + const struct stm32_ddr_pmu_regspec *r =3D pmu->cfg->regs; + u32 val =3D readl_relaxed(pmu->membase + r->enable.reg); + + val |=3D BIT(counter->idx); + writel_relaxed(val, pmu->membase + r->enable.reg); +} + +static void stm32_ddr_counter_disable(struct stm32_ddr_pmu *pmu, struct st= m32_ddr_cnt *counter) +{ + const struct stm32_ddr_pmu_regspec *r =3D pmu->cfg->regs; + u32 val =3D readl_relaxed(pmu->membase + r->enable.reg); + + val &=3D ~BIT(counter->idx); + writel_relaxed(val, pmu->membase + r->enable.reg); +} + +static int stm32_ddr_sel_evnt(struct stm32_ddr_pmu *pmu, struct stm32_ddr_= cnt *counter) +{ + const struct stm32_ddr_pmu_regspec *r =3D pmu->cfg->regs; + u32 cnt_sel_val; + + u32 group_val =3D STM32_DDR_PMU_GROUP_VALUE(counter->evt->attr.config); + u32 evt_val =3D STM32_DDR_PMU_EVENT_INDEX(counter->evt->attr.config); + + if (pmu->selected_set !=3D -1 && pmu->selected_set !=3D group_val) { + dev_err(pmu->dev, "Selected events are from different set\n"); + return -EINVAL; + } + pmu->selected_set =3D group_val; + + if (pmu->cfg->regs->cfg.reg) { + cnt_sel_val =3D readl_relaxed(pmu->membase + r->cfg.reg); + cnt_sel_val &=3D ~CFG_SEL_MSK; + cnt_sel_val |=3D (CFG_SEL_MSK & (group_val << CFG_SEL_SHIFT)); + writel_relaxed(cnt_sel_val, pmu->membase + r->cfg.reg); + + return 0; + } + + /* We assume cfg0 and cfg1 are filled in the match data */ + u32 cnt_idx =3D counter->idx; + u32 cnt_sel_evt_reg =3D r->cfg0.reg; + + if (!(cnt_idx < MP2_CNT_SEL_PER_REG)) { + cnt_sel_evt_reg =3D r->cfg1.reg; + cnt_idx -=3D MP2_CNT_SEL_PER_REG; + } + + cnt_sel_val =3D readl_relaxed(pmu->membase + cnt_sel_evt_reg); + cnt_sel_val &=3D ~GENMASK(8 * cnt_idx + 7, 8 * cnt_idx); + cnt_sel_val |=3D evt_val << (8 * cnt_idx); + + writel_relaxed(cnt_sel_val, pmu->membase + cnt_sel_evt_reg); + + return 0; +} + +static struct stm32_ddr_cnt *stm32_ddr_pmu_get_event_counter_mp1(struct st= m32_ddr_pmu *pmu, + struct perf_event *event) +{ + u32 config =3D event->attr.config; + u32 event_idx =3D STM32_DDR_PMU_EVENT_INDEX(config); + struct stm32_ddr_cnt *cnt; + + cnt =3D kzalloc(sizeof(*cnt), GFP_KERNEL); + if (!cnt) + return ERR_PTR(-ENOMEM); + + cnt->evt =3D event; + cnt->idx =3D event_idx; + event->pmu_private =3D cnt; + list_add(&cnt->cnt_list, &pmu->counters[event_idx]); + + return cnt; +} + +static struct stm32_ddr_cnt *stm32_ddr_pmu_get_event_counter_mp2(struct st= m32_ddr_pmu *pmu, + struct perf_event *event) +{ + struct stm32_ddr_cnt *cnt; + int idx =3D -1; + + /* Loop on all the counters except TIME_CNT_IDX */ + for (int i =3D 0; i < pmu->cfg->evt_counters_nb; i++) { + u64 config; + + if (list_empty(&pmu->counters[i])) { + idx =3D i; + continue; + } + config =3D list_first_entry(&pmu->counters[i], struct stm32_ddr_cnt, + cnt_list)->evt->attr.config; + if (config =3D=3D event->attr.config) { + idx =3D i; + break; + } + } + + if (idx =3D=3D -1) + return ERR_PTR(-ENOENT); + + cnt =3D kzalloc(sizeof(*cnt), GFP_KERNEL); + if (!cnt) + return ERR_PTR(-ENOMEM); + + cnt->evt =3D event; + cnt->idx =3D idx; + event->pmu_private =3D cnt; + + list_add(&cnt->cnt_list, &pmu->counters[idx]); + + return cnt; +} + +static inline struct stm32_ddr_cnt *stm32_get_event_counter(struct stm32_d= dr_pmu *pmu, + struct perf_event *event) +{ + return pmu->cfg->get_counter(pmu, event); +} + +static int stm32_ddr_pmu_get_counter(struct stm32_ddr_pmu *pmu, struct per= f_event *event) +{ + u32 time_cnt_idx =3D pmu->cfg->time_cnt_idx; + u32 config =3D event->attr.config; + struct stm32_ddr_cnt *cnt; + + pmu->selected_set =3D STM32_DDR_PMU_GROUP_VALUE(config); + + if (config =3D=3D TIME_CNT) { + cnt =3D kzalloc(sizeof(*cnt), GFP_KERNEL); + if (!cnt) + return -ENOMEM; + + cnt->evt =3D event; + cnt->idx =3D time_cnt_idx; + event->pmu_private =3D cnt; + list_add(&cnt->cnt_list, &pmu->counters[time_cnt_idx]); + + return 0; + } + + cnt =3D stm32_get_event_counter(pmu, event); + if (IS_ERR(cnt)) + return PTR_ERR(cnt); + + if (list_count_nodes(&cnt->cnt_list) =3D=3D 1) { + stm32_ddr_stop_counters(pmu); + stm32_ddr_sel_evnt(pmu, cnt); + stm32_ddr_counter_enable(pmu, cnt); + stm32_ddr_start_counters(pmu); + } + + return 0; +} + +static void stm32_ddr_pmu_free_counter(struct stm32_ddr_pmu *pmu, + struct stm32_ddr_cnt *counter) +{ + size_t count =3D list_count_nodes(&counter->cnt_list); + + if (counter->evt->attr.config !=3D TIME_CNT && count =3D=3D 1) + stm32_ddr_counter_disable(pmu, counter); + + list_del(&counter->cnt_list); + kfree(counter); +} + +static void stm32_ddr_pmu_event_update_list(struct stm32_ddr_pmu *pmu, str= uct list_head *list) +{ + struct stm32_ddr_cnt *counter =3D list_first_entry(list, struct stm32_ddr= _cnt, cnt_list); + const struct stm32_ddr_pmu_regspec *r =3D pmu->cfg->regs; + u32 val; + + if (counter->evt->attr.config !=3D TIME_CNT) + val =3D readl_relaxed(pmu->membase + r->counter_evt[counter->idx].reg); + else + val =3D readl_relaxed(pmu->membase + r->counter_time.reg); + + stm32_ddr_clear_counter(pmu, counter); + + list_for_each_entry(counter, list, cnt_list) + local64_add(val, &counter->evt->count); +} + +static void stm32_ddr_pmu_event_read(struct perf_event *event) +{ + struct stm32_ddr_pmu *pmu =3D to_stm32_ddr_pmu(event->pmu); + struct stm32_ddr_cnt *cnt =3D event->pmu_private; + + hrtimer_start(&pmu->hrtimer, pmu->poll_period, HRTIMER_MODE_REL_PINNED); + + stm32_ddr_stop_counters(pmu); + + stm32_ddr_pmu_event_update_list(pmu, &pmu->counters[cnt->idx]); + + stm32_ddr_start_counters(pmu); +} + +static void stm32_ddr_pmu_event_start(struct perf_event *event, int flags) +{ + struct stm32_ddr_pmu *pmu =3D to_stm32_ddr_pmu(event->pmu); + struct stm32_ddr_cnt *counter =3D event->pmu_private; + struct hw_perf_event *hw =3D &event->hw; + + if (WARN_ON_ONCE(!(hw->state & PERF_HES_STOPPED))) + return; + + if (flags & PERF_EF_RELOAD) + WARN_ON_ONCE(!(hw->state & PERF_HES_UPTODATE)); + + stm32_ddr_stop_counters(pmu); + + if (list_count_nodes(&counter->cnt_list) =3D=3D 1) + stm32_ddr_clear_counter(pmu, counter); + else + stm32_ddr_pmu_event_update_list(pmu, &pmu->counters[counter->idx]); + + stm32_ddr_start_counters(pmu); + local64_set(&hw->prev_count, 0); + hw->state =3D 0; +} + +static void stm32_ddr_pmu_event_stop(struct perf_event *event, int flags) +{ + struct hw_perf_event *hw =3D &event->hw; + + if (WARN_ON_ONCE(hw->state & PERF_HES_STOPPED)) + return; + + hw->state |=3D PERF_HES_STOPPED; + + if (flags & PERF_EF_UPDATE) { + stm32_ddr_pmu_event_read(event); + hw->state |=3D PERF_HES_UPTODATE; + } +} + +static int stm32_ddr_pmu_event_add(struct perf_event *event, int flags) +{ + struct stm32_ddr_pmu *pmu =3D to_stm32_ddr_pmu(event->pmu); + int ret; + + clk_enable(pmu->clk); + + hrtimer_start(&pmu->hrtimer, pmu->poll_period, HRTIMER_MODE_REL_PINNED); + + ret =3D stm32_ddr_pmu_get_counter(pmu, event); + if (ret) + return ret; + + event->hw.state =3D PERF_HES_STOPPED | PERF_HES_UPTODATE; + + if (flags & PERF_EF_START) + stm32_ddr_pmu_event_start(event, flags); + + return 0; +} + +static void stm32_ddr_pmu_event_del(struct perf_event *event, int flags) +{ + struct stm32_ddr_pmu *pmu =3D to_stm32_ddr_pmu(event->pmu); + struct stm32_ddr_cnt *counter =3D event->pmu_private; + bool events =3D true; + + stm32_ddr_pmu_event_stop(event, PERF_EF_UPDATE); + + stm32_ddr_pmu_free_counter(pmu, counter); + + for (int i =3D 0; i < pmu->cfg->counters_nb; i++) { + events =3D !list_empty(&pmu->counters[i]); + if (events) /* If there is activity nothing to do */ + return; + } + + hrtimer_cancel(&pmu->hrtimer); + stm32_ddr_stop_counters(pmu); + + pmu->selected_set =3D -1; + + clk_disable(pmu->clk); +} + +static int stm32_ddr_pmu_event_init(struct perf_event *event) +{ + if (event->attr.type !=3D event->pmu->type) + return -ENOENT; + + if (is_sampling_event(event) || event->attach_state & PERF_ATTACH_TASK) + return -EINVAL; + + return 0; +} + +static enum hrtimer_restart stm32_ddr_pmu_poll(struct hrtimer *hrtimer) +{ + struct stm32_ddr_pmu *pmu =3D hrtimer_to_stm32_ddr_pmu(hrtimer); + + stm32_ddr_stop_counters(pmu); + + for (int i =3D 0; i < MP2_CNT_NB; i++) + if (!list_empty(&pmu->counters[i])) + stm32_ddr_pmu_event_update_list(pmu, &pmu->counters[i]); + + if (list_empty(&pmu->counters[pmu->cfg->time_cnt_idx])) + stm32_ddr_clear_time_counter(pmu); + + stm32_ddr_start_counters(pmu); + + hrtimer_forward_now(hrtimer, pmu->poll_period); + + return HRTIMER_RESTART; +} + +static ssize_t stm32_ddr_pmu_sysfs_show(struct device *dev, struct device_= attribute *attr, + char *buf) +{ + struct perf_pmu_events_attr *pmu_attr; + + pmu_attr =3D container_of(attr, struct perf_pmu_events_attr, attr); + + return sysfs_emit(buf, "event=3D0x%02llx\n", pmu_attr->id); +} + +static int stm32_ddr_pmu_get_memory_type(struct stm32_ddr_pmu *pmu) +{ + struct platform_device *pdev =3D to_platform_device(pmu->dev); + struct device_node *memchan; + + memchan =3D of_parse_phandle(pdev->dev.of_node, "memory-channel", 0); + if (!memchan) + return dev_err_probe(&pdev->dev, -EINVAL, + "Missing device-tree property 'memory-channel'\n"); + + if (of_device_is_compatible(memchan, "jedec,lpddr4-channel")) + pmu->dram_type =3D STM32_DDR_PMU_LPDDR4; + else if (of_device_is_compatible(memchan, "jedec,lpddr3-channel")) + pmu->dram_type =3D STM32_DDR_PMU_LPDDR3; + else if (of_device_is_compatible(memchan, "jedec,ddr4-channel")) + pmu->dram_type =3D STM32_DDR_PMU_DDR4; + else if (of_device_is_compatible(memchan, "jedec,ddr3-channel")) + pmu->dram_type =3D STM32_DDR_PMU_DDR3; + else + return dev_err_probe(&pdev->dev, -EINVAL, "Unsupported memory channel ty= pe\n"); + + if (pmu->dram_type =3D=3D STM32_DDR_PMU_LPDDR3) + dev_warn(&pdev->dev, + "LPDDR3 supported by DDRPERFM but not supported by DDRCTRL/DDRPHY\n"); + + return 0; +} + +#define STM32_DDR_PMU_EVENT_ATTR(_name, _id) \ + PMU_EVENT_ATTR_ID(_name, stm32_ddr_pmu_sysfs_show, _id) + +static struct attribute *stm32_ddr_pmu_events_attrs_mp[] =3D { + STM32_DDR_PMU_EVENT_ATTR(perf_op_is_rd, PERF_OP_IS_RD), + STM32_DDR_PMU_EVENT_ATTR(perf_op_is_wr, PERF_OP_IS_WR), + STM32_DDR_PMU_EVENT_ATTR(perf_op_is_activate, PERF_OP_IS_ACTIVATE), + STM32_DDR_PMU_EVENT_ATTR(ctl_idle, CTL_IDLE), + STM32_DDR_PMU_EVENT_ATTR(perf_hpr_req_with_no_credit, PERF_HPR_REQ_WITH_N= O_CREDIT), + STM32_DDR_PMU_EVENT_ATTR(perf_lpr_req_with_no_credit, PERF_LPR_REQ_WITH_N= O_CREDIT), + STM32_DDR_PMU_EVENT_ATTR(cactive_ddrc, CACTIVE_DDRC), + STM32_DDR_PMU_EVENT_ATTR(perf_op_is_enter_powerdown, PERF_OP_IS_ENTER_POW= ERDOWN), + STM32_DDR_PMU_EVENT_ATTR(perf_op_is_refresh, PERF_OP_IS_REFRESH), + STM32_DDR_PMU_EVENT_ATTR(perf_selfresh_mode, PERF_SELFRESH_MODE), + STM32_DDR_PMU_EVENT_ATTR(dfi_lp_req, DFI_LP_REQ), + STM32_DDR_PMU_EVENT_ATTR(perf_hpr_xact_when_critical, PERF_HPR_XACT_WHEN_= CRITICAL), + STM32_DDR_PMU_EVENT_ATTR(perf_lpr_xact_when_critical, PERF_LPR_XACT_WHEN_= CRITICAL), + STM32_DDR_PMU_EVENT_ATTR(perf_wr_xact_when_critical, PERF_WR_XACT_WHEN_CR= ITICAL), + STM32_DDR_PMU_EVENT_ATTR(dfi_lp_req_cpy, DFI_LP_REQ), /* Suffixed '_cpy'= to allow the + * choice between sets 2 and 3 + */ + STM32_DDR_PMU_EVENT_ATTR(time_cnt, TIME_CNT), + NULL +}; + +static struct attribute_group stm32_ddr_pmu_events_attrs_group_mp =3D { + .name =3D "events", + .attrs =3D stm32_ddr_pmu_events_attrs_mp, +}; + +static struct attribute *stm32_ddr_pmu_events_attrs_mp2[] =3D { + STM32_DDR_PMU_EVENT_ATTR(dfi_is_act, DFI_IS_ACT), + STM32_DDR_PMU_EVENT_ATTR(dfi_is_prepb, DFI_IS_PREPB), + STM32_DDR_PMU_EVENT_ATTR(dfi_is_preab, DFI_IS_PREAB), + STM32_DDR_PMU_EVENT_ATTR(dfi_is_rd, DFI_IS_RD), + STM32_DDR_PMU_EVENT_ATTR(dfi_is_rda, DFI_IS_RDA), + STM32_DDR_PMU_EVENT_ATTR(dfi_is_wr, DFI_IS_WR), + STM32_DDR_PMU_EVENT_ATTR(dfi_is_wra, DFI_IS_WRA), + STM32_DDR_PMU_EVENT_ATTR(dfi_is_mwr, DFI_IS_MWR), + STM32_DDR_PMU_EVENT_ATTR(dfi_is_mwra, DFI_IS_MWRA), + STM32_DDR_PMU_EVENT_ATTR(dfi_is_mrw, DFI_IS_MRW), + STM32_DDR_PMU_EVENT_ATTR(dfi_is_mrr, DFI_IS_MRR), + STM32_DDR_PMU_EVENT_ATTR(dfi_is_refpb, DFI_IS_REFPB), + STM32_DDR_PMU_EVENT_ATTR(dfi_is_refab, DFI_IS_REFAB), + STM32_DDR_PMU_EVENT_ATTR(dfi_is_mpc, DFI_IS_MPC), + STM32_DDR_PMU_EVENT_ATTR(perf_op_is_act, PERF_OP_IS_ACT), + STM32_DDR_PMU_EVENT_ATTR(perf_op_is_rd, PERF_OP_IS_RD), + STM32_DDR_PMU_EVENT_ATTR(perf_op_is_wr, PERF_OP_IS_WR), + STM32_DDR_PMU_EVENT_ATTR(perf_op_is_mwr, PERF_OP_IS_MWR), + STM32_DDR_PMU_EVENT_ATTR(perf_op_is_ref, PERF_OP_IS_REF), + STM32_DDR_PMU_EVENT_ATTR(perf_op_is_crit_ref, PERF_OP_IS_CRIT_REF), + STM32_DDR_PMU_EVENT_ATTR(perf_op_is_spec_ref, PERF_OP_IS_SPEC_REF), + STM32_DDR_PMU_EVENT_ATTR(perf_op_is_zqcal, PERF_OP_IS_ZQCAL), + STM32_DDR_PMU_EVENT_ATTR(perf_op_is_enter_powdn, PERF_OP_IS_ENTER_POWDN), + STM32_DDR_PMU_EVENT_ATTR(perf_op_is_enter_selfref, PERF_OP_IS_ENTER_SELFR= EF), + STM32_DDR_PMU_EVENT_ATTR(perf_op_is_pre, PERF_OP_IS_PRE), + STM32_DDR_PMU_EVENT_ATTR(perf_op_is_pre_for_rdwr, PERF_OP_IS_PRE_FOR_RDWR= ), + STM32_DDR_PMU_EVENT_ATTR(perf_op_is_pre_for_others, PERF_OP_IS_PRE_FOR_OT= HERS), + STM32_DDR_PMU_EVENT_ATTR(perf_op_is_rd_activate, PERF_OP_IS_RD_ACTIVATE), + STM32_DDR_PMU_EVENT_ATTR(perf_hpr_req_with_nocredit, PERF_HPR_REQ_WITH_NO= CREDIT), + STM32_DDR_PMU_EVENT_ATTR(perf_lpr_req_with_nocredit, PERF_LPR_REQ_WITH_NO= CREDIT), + STM32_DDR_PMU_EVENT_ATTR(perf_hpr_xact_when_critical, PERF_HPR_XACT_WHEN_= CRITICAL), + STM32_DDR_PMU_EVENT_ATTR(perf_lpr_xact_when_critical, PERF_LPR_XACT_WHEN_= CRITICAL), + STM32_DDR_PMU_EVENT_ATTR(perf_wr_xact_when_critical, PERF_WR_XACT_WHEN_CR= ITICAL), + STM32_DDR_PMU_EVENT_ATTR(perf_rdwr_transitions, PERF_RDWR_TRANSITIONS), + STM32_DDR_PMU_EVENT_ATTR(perf_war_hazard, PERF_WAR_HAZARD), + STM32_DDR_PMU_EVENT_ATTR(perf_raw_hazard, PERF_RAW_HAZARD), + STM32_DDR_PMU_EVENT_ATTR(perf_waw_hazard, PERF_WAW_HAZARD), + STM32_DDR_PMU_EVENT_ATTR(perf_rank, PERF_RANK), + STM32_DDR_PMU_EVENT_ATTR(perf_read_bypass, PERF_READ_BYPASS), + STM32_DDR_PMU_EVENT_ATTR(perf_act_bypass, PERF_ACT_BYPASS), + STM32_DDR_PMU_EVENT_ATTR(perf_window_limit_reached_rd, PERF_WINDOW_LIMIT_= REACHED_RD), + STM32_DDR_PMU_EVENT_ATTR(perf_window_limit_reached_wr, PERF_WINDOW_LIMIT_= REACHED_WR), + STM32_DDR_PMU_EVENT_ATTR(time_cnt, TIME_CNT), + NULL +}; + +static struct attribute_group stm32_ddr_pmu_events_attrs_group_mp2 =3D { + .name =3D "events", + .attrs =3D stm32_ddr_pmu_events_attrs_mp2, +}; + +PMU_FORMAT_ATTR(event, "config:0-8"); + +static struct attribute *stm32_ddr_pmu_format_attrs[] =3D { + &format_attr_event.attr, + NULL +}; + +static const struct attribute_group stm32_ddr_pmu_format_attr_group =3D { + .name =3D "format", + .attrs =3D stm32_ddr_pmu_format_attrs, +}; + +static const struct attribute_group *stm32_ddr_pmu_attr_groups_mp1[] =3D { + &stm32_ddr_pmu_events_attrs_group_mp, + &stm32_ddr_pmu_format_attr_group, + NULL +}; + +static const struct attribute_group *stm32_ddr_pmu_attr_groups_mp2[] =3D { + &stm32_ddr_pmu_events_attrs_group_mp2, + &stm32_ddr_pmu_format_attr_group, + NULL +}; + +static int stm32_ddr_pmu_device_probe(struct platform_device *pdev) +{ + struct stm32_firewall firewall; + struct stm32_ddr_pmu *pmu; + struct reset_control *rst; + struct resource *res; + int ret; + + pmu =3D devm_kzalloc(&pdev->dev, struct_size(pmu, counters, MP2_CNT_NB), = GFP_KERNEL); + if (!pmu) + return -ENOMEM; + + platform_set_drvdata(pdev, pmu); + pmu->dev =3D &pdev->dev; + + pmu->cfg =3D device_get_match_data(pmu->dev); + + pmu->membase =3D devm_platform_get_and_ioremap_resource(pdev, 0, &res); + if (IS_ERR(pmu->membase)) + return PTR_ERR(pmu->membase); + + if (of_property_present(pmu->dev->of_node, "access-controllers")) { + ret =3D stm32_firewall_get_firewall(pmu->dev->of_node, &firewall, 1); + if (ret) + return dev_err_probe(pmu->dev, ret, "Failed to get firewall\n"); + ret =3D stm32_firewall_grant_access_by_id(&firewall, firewall.firewall_i= d); + if (ret) + return dev_err_probe(pmu->dev, ret, "Failed to grant access\n"); + } + + pmu->clk =3D devm_clk_get_optional_enabled(pmu->dev, NULL); + if (IS_ERR(pmu->clk)) + return dev_err_probe(pmu->dev, PTR_ERR(pmu->clk), + "Failed to get prepare enable clock\n"); + + rst =3D devm_reset_control_get_optional_exclusive(pmu->dev, NULL); + if (IS_ERR(rst)) + return dev_err_probe(pmu->dev, PTR_ERR(rst), "Failed to get reset\n"); + + reset_control_assert(rst); + reset_control_deassert(rst); + + pmu->poll_period =3D ms_to_ktime(POLL_MS); + hrtimer_setup(&pmu->hrtimer, stm32_ddr_pmu_poll, CLOCK_MONOTONIC, HRTIMER= _MODE_REL); + + for (int i =3D 0; i < MP2_CNT_NB; i++) + INIT_LIST_HEAD(&pmu->counters[i]); + + pmu->selected_set =3D -1; + + pmu->pmu =3D (struct pmu) { + .task_ctx_nr =3D perf_invalid_context, + .start =3D stm32_ddr_pmu_event_start, + .stop =3D stm32_ddr_pmu_event_stop, + .add =3D stm32_ddr_pmu_event_add, + .del =3D stm32_ddr_pmu_event_del, + .read =3D stm32_ddr_pmu_event_read, + .event_init =3D stm32_ddr_pmu_event_init, + .attr_groups =3D pmu->cfg->attribute, + .module =3D THIS_MODULE, + }; + + if (pmu->cfg->regs->dram_inf.reg) { + ret =3D stm32_ddr_pmu_get_memory_type(pmu); + if (ret) + return dev_err_probe(pmu->dev, ret, "Failed to get memory type\n"); + + writel_relaxed(pmu->dram_type, pmu->membase + pmu->cfg->regs->dram_inf.r= eg); + } + + ret =3D perf_pmu_register(&pmu->pmu, DRIVER_NAME, -1); + if (ret) + return dev_err_probe(pmu->dev, ret, + "Couldn't register DDRPERFM driver as a PMU\n"); + + clk_disable(pmu->clk); + + return 0; +} + +static void stm32_ddr_pmu_device_remove(struct platform_device *pdev) +{ + struct stm32_ddr_pmu *stm32_ddr_pmu =3D platform_get_drvdata(pdev); + + perf_pmu_unregister(&stm32_ddr_pmu->pmu); +} + +static int __maybe_unused stm32_ddr_pmu_device_resume(struct device *dev) +{ + struct stm32_ddr_pmu *pmu =3D dev_get_drvdata(dev); + + clk_enable(pmu->clk); + writel_relaxed(pmu->dram_type, pmu->membase + pmu->cfg->regs->dram_inf.re= g); + clk_disable(pmu->clk); + + return 0; +} + +static const struct stm32_ddr_pmu_regspec stm32_ddr_pmu_regspec_mp1 =3D { + .stop =3D { DDRPERFM_CTRL, CTRL_STOP }, + .start =3D { DDRPERFM_CTRL, CTRL_START }, + .enable =3D { DDRPERFM_CFG }, + .cfg =3D { DDRPERFM_CFG }, + .status =3D { DDRPERFM_STATUS, MP1_STATUS_BUSY }, + .clear_cnt =3D { DDRPERFM_CLR, MP1_CLR_CNT }, + .clear_time =3D { DDRPERFM_CLR, MP1_CLR_TIME }, + .counter_time =3D { DDRPERFM_TCNT }, + .counter_evt =3D { + { DDRPERFM_EVCNT(0) }, + { DDRPERFM_EVCNT(1) }, + { DDRPERFM_EVCNT(2) }, + { DDRPERFM_EVCNT(3) }, + }, +}; + +static const struct stm32_ddr_pmu_regspec stm32_ddr_pmu_regspec_mp2 =3D { + .stop =3D { DDRPERFM_CTRL, CTRL_STOP }, + .start =3D { DDRPERFM_CTRL, CTRL_START }, + .status =3D { DDRPERFM_MP2_STATUS, MP2_STATUS_BUSY }, + .clear_cnt =3D { DDRPERFM_CLR, MP2_CLR_CNT }, + .clear_time =3D { DDRPERFM_CLR, MP2_CLR_TIME }, + .cfg0 =3D { DDRPERFM_MP2_CFG0 }, + .cfg1 =3D { DDRPERFM_MP2_CFG1 }, + .enable =3D { DDRPERFM_MP2_CFG5 }, + .dram_inf =3D { DDRPERFM_MP2_DRAMINF }, + .counter_time =3D { DDRPERFM_MP2_TCNT }, + .counter_evt =3D { + { DDRPERFM_MP2_EVCNT(0) }, + { DDRPERFM_MP2_EVCNT(1) }, + { DDRPERFM_MP2_EVCNT(2) }, + { DDRPERFM_MP2_EVCNT(3) }, + { DDRPERFM_MP2_EVCNT(4) }, + { DDRPERFM_MP2_EVCNT(5) }, + { DDRPERFM_MP2_EVCNT(6) }, + { DDRPERFM_MP2_EVCNT(7) }, + }, +}; + +static const struct stm32_ddr_pmu_cfg stm32_ddr_pmu_cfg_mp1 =3D { + .regs =3D &stm32_ddr_pmu_regspec_mp1, + .attribute =3D stm32_ddr_pmu_attr_groups_mp1, + .counters_nb =3D MP1_CNT_NB, + .evt_counters_nb =3D MP1_CNT_NB - 1, /* Time counter is not an event coun= ter */ + .time_cnt_idx =3D MP1_TIME_CNT_IDX, + .get_counter =3D stm32_ddr_pmu_get_event_counter_mp1, +}; + +static const struct stm32_ddr_pmu_cfg stm32_ddr_pmu_cfg_mp2 =3D { + .regs =3D &stm32_ddr_pmu_regspec_mp2, + .attribute =3D stm32_ddr_pmu_attr_groups_mp2, + .counters_nb =3D MP2_CNT_NB, + .evt_counters_nb =3D MP2_CNT_NB - 1, /* Time counter is an event counter = */ + .time_cnt_idx =3D MP2_TIME_CNT_IDX, + .get_counter =3D stm32_ddr_pmu_get_event_counter_mp2, +}; + +static DEFINE_SIMPLE_DEV_PM_OPS(stm32_ddr_pmu_pm_ops, NULL, stm32_ddr_pmu_= device_resume); + +static const struct of_device_id stm32_ddr_pmu_of_match[] =3D { + { + .compatible =3D "st,stm32mp131-ddr-pmu", + .data =3D &stm32_ddr_pmu_cfg_mp1 + }, + { + .compatible =3D "st,stm32mp251-ddr-pmu", + .data =3D &stm32_ddr_pmu_cfg_mp2 + }, + { } +}; +MODULE_DEVICE_TABLE(of, stm32_ddr_pmu_of_match); + +static struct platform_driver stm32_ddr_pmu_driver =3D { + .driver =3D { + .name =3D DRIVER_NAME, + .pm =3D pm_sleep_ptr(&stm32_ddr_pmu_pm_ops), + .of_match_table =3D stm32_ddr_pmu_of_match, + }, + .probe =3D stm32_ddr_pmu_device_probe, + .remove =3D stm32_ddr_pmu_device_remove, +}; + +module_platform_driver(stm32_ddr_pmu_driver); + +MODULE_AUTHOR("Cl=C3=A9ment Le Goffic"); +MODULE_DESCRIPTION("STMicroelectronics STM32 DDR performance monitor drive= r"); +MODULE_LICENSE("GPL"); --=20 2.43.0 From nobody Sun Oct 5 23:37:45 2025 Received: from mx08-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7E54E273816; Mon, 28 Jul 2025 15:35:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=91.207.212.93 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753716919; cv=none; b=mghtAgU1r42NfQosL0QJX9eupIB0FudaEoFHPA2JR1eujJFkiSIRiZBz6chj1LNA4LcA2bZdl9LY3GLWrUmxojfHGC29y2lzrQbpHPU22cOddPfzlCgTWJAvD5U79DI5ZC9U7a+20Got60AmVvN2WpnK0T9nM5U6zGEj4vAjVm8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753716919; c=relaxed/simple; bh=2uEtFVwi+wdX8OeRQHgPRlqO3x1jsKN8u5e4kKD7Awk=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=P5cyHlcDZ0B+DRv5B7SUR5ufIPxeNax9hjgUwIXdlmwVSuUk0codFnXzbWEN+vFt/M5NUcm5NtuNx6CBSyLXgDc7WmDruvVX15jXVHByyeIK8TEHFGaWCWKSdBpzc0+cXub7gmwND/aLOIZny/ofA/JjDxTI9rMr5zvMzMB369A= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com; spf=pass smtp.mailfrom=foss.st.com; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b=gG0Y2yOT; arc=none smtp.client-ip=91.207.212.93 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=foss.st.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b="gG0Y2yOT" Received: from pps.filterd (m0369457.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 56SDr2Gx027841; Mon, 28 Jul 2025 17:35:01 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=selector1; bh= W7lja2ibWXfiVo4eDJLx4tgeIggbs4JL9GjrFt29DoI=; b=gG0Y2yOT1jDlR+cK EGtjFyZ3sRVlssE1wceff2KDnwFejXfgN1RJU7hTml/0QXMePRBp/Gj/KJwU2Gzg 9wFRVM6ZZSvyJuc04hjGkb7/CLvrxCjCjm96kXzIqcDKhpzz9qaYqNgcugz6lI7g wtTKydRYJNH85eSTJ8kcRCqvmH/dvaAPeUqkrTCqrGv5jmFJ1dSLhx0XBD5k1l0L 9VO6JVnC6edA8+RBB2+ew1riYBW7zsWQwppeqxEJN+iHIYmxhHEKKur7RrfOFbO/ 4ncAU4YmrBX8ZbpeXlUnKR7uRiNQL14ZHT4QCWJErwF6+klO3KGRQ1B4Hkhm4Chu iNdcVA== Received: from beta.dmz-ap.st.com (beta.dmz-ap.st.com [138.198.100.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 4859yndytr-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 28 Jul 2025 17:35:01 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 18CAA4004B; Mon, 28 Jul 2025 17:33:38 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 1187D78C90A; Mon, 28 Jul 2025 17:30:04 +0200 (CEST) Received: from localhost (10.252.23.100) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Mon, 28 Jul 2025 17:30:03 +0200 From: =?utf-8?q?Cl=C3=A9ment_Le_Goffic?= Date: Mon, 28 Jul 2025 17:29:45 +0200 Subject: [PATCH v5 14/20] Documentation: perf: stm32: add ddrperfm support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250728-ddrperfm-upstream-v5-14-03f1be8ad396@foss.st.com> References: <20250728-ddrperfm-upstream-v5-0-03f1be8ad396@foss.st.com> In-Reply-To: <20250728-ddrperfm-upstream-v5-0-03f1be8ad396@foss.st.com> To: Will Deacon , Mark Rutland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Philipp Zabel , Jonathan Corbet , Gatien Chevallier , Michael Turquette , Stephen Boyd , Gabriel Fernandez , Krzysztof Kozlowski , Le Goffic , Julius Werner CC: , , , , , , , =?utf-8?q?Cl=C3=A9ment_Le_Goffic?= X-Mailer: b4 0.15-dev-8018a X-ClientProxiedBy: SHFCAS1NODE2.st.com (10.75.129.73) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-28_03,2025-07-28_01,2025-03-28_01 The DDRPERFM is the DDR Performance Monitor embedded in STM32MPU SoC. This documentation introduces the DDRPERFM, the stm32-ddr-pmu driver supporting it and how to use it with the perf tool. Signed-off-by: Cl=C3=A9ment Le Goffic --- Documentation/admin-guide/perf/index.rst | 1 + Documentation/admin-guide/perf/stm32-ddr-pmu.rst | 86 ++++++++++++++++++++= ++++ 2 files changed, 87 insertions(+) diff --git a/Documentation/admin-guide/perf/index.rst b/Documentation/admin= -guide/perf/index.rst index 072b510385c4..33aedc4ee5c3 100644 --- a/Documentation/admin-guide/perf/index.rst +++ b/Documentation/admin-guide/perf/index.rst @@ -29,3 +29,4 @@ Performance monitor support cxl ampere_cspmu mrvl-pem-pmu + stm32-ddr-pmu diff --git a/Documentation/admin-guide/perf/stm32-ddr-pmu.rst b/Documentati= on/admin-guide/perf/stm32-ddr-pmu.rst new file mode 100644 index 000000000000..5b02bf44dd7a --- /dev/null +++ b/Documentation/admin-guide/perf/stm32-ddr-pmu.rst @@ -0,0 +1,86 @@ +.. SPDX-License-Identifier: GPL-2.0 + +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +STM32 DDR Performance Monitor (DDRPERFM) +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +The DDRPERFM is the DDR Performance Monitor embedded in STM32MPU SoC. +The DDR controller provides events to DDRPERFM, once selected they are cou= nted in the DDRPERFM +peripheral. + +In MP1 family, the DDRPERFM is able to count 4 different events at the sam= e time. +However, the 4 events must belong to the same set. +One hardware counter is dedicated to the time counter, `time_cnt`. + +In MP2 family, the DDRPERFM is able to select between 44 different DDR eve= nts. +As for MP1, there is a dedicated hardware counter for the time. +It is incremented every 4 DDR clock cycles. +All the other counters can be freely allocated to count any other DDR even= t. + +The stm32-ddr-pmu driver relies on the perf PMU framework to expose the co= unters via sysfs: + +On MP1: + + .. code-block:: bash + + $ ls /sys/bus/event_source/devices/stm32_ddr_pmu/events/ + cactive_ddrc perf_lpr_req_with_no_credit perf_op_= is_wr + ctl_idle perf_lpr_xact_when_critical perf_sel= fresh_mode + dfi_lp_req perf_op_is_activate perf_wr_= xact_when_critical + dfi_lp_req_cpy perf_op_is_enter_powerdown time_cnt + perf_hpr_req_with_no_credit perf_op_is_rd + perf_hpr_xact_when_critical perf_op_is_refresh + +On MP2: + + .. code-block:: bash + + $ ls /sys/bus/event_source/devices/stm32_ddr_pmu/events/ + dfi_is_act perf_hpr_req_with_nocredit perf_op_is_spec_ref + dfi_is_mpc perf_hpr_xact_when_critical perf_op_is_wr + dfi_is_mrr perf_lpr_req_with_nocredit perf_op_is_zqcal + dfi_is_mrw perf_lpr_xact_when_critical perf_rank + dfi_is_mwr perf_op_is_act perf_raw_hazard + dfi_is_mwra perf_op_is_crit_ref perf_rdwr_transitions + dfi_is_preab perf_op_is_enter_powdn perf_read_bypass + dfi_is_prepb perf_op_is_enter_selfref perf_war_hazard + dfi_is_rd perf_op_is_mwr perf_waw_hazard + dfi_is_rda perf_op_is_pre perf_window_limit_re= ached_rd + dfi_is_refab perf_op_is_pre_for_others perf_window_limit_re= ached_wr + dfi_is_refpb perf_op_is_pre_for_rdwr perf_wr_xact_when_cr= itical + dfi_is_wr perf_op_is_rd time_cnt + dfi_is_wra perf_op_is_rd_activate + perf_act_bypass perf_op_is_ref + + +The perf PMU framework is usually invoked via the 'perf stat' tool. + + +Example: + + .. code-block:: bash + + $ perf stat --timeout 60000 -e stm32_ddr_pmu/dfi_is_act/,\ + > stm32_ddr_pmu/dfi_is_rd/,\ + > stm32_ddr_pmu/dfi_is_wr/,\ + > stm32_ddr_pmu/dfi_is_refab/,\ + > stm32_ddr_pmu/dfi_is_mrw/,\ + > stm32_ddr_pmu/dfi_is_rda/,\ + > stm32_ddr_pmu/dfi_is_wra/,\ + > stm32_ddr_pmu/dfi_is_mrr/,\ + > stm32_ddr_pmu/time_cnt/ \ + > -a sleep 5 + + Performance counter stats for 'system wide': + + 481025 stm32_ddr_pmu/dfi_is_act/ + 732166 stm32_ddr_pmu/dfi_is_rd/ + 144926 stm32_ddr_pmu/dfi_is_wr/ + 644154 stm32_ddr_pmu/dfi_is_refab/ + 0 stm32_ddr_pmu/dfi_is_mrw/ + 0 stm32_ddr_pmu/dfi_is_rda/ + 0 stm32_ddr_pmu/dfi_is_wra/ + 0 stm32_ddr_pmu/dfi_is_mrr/ + 752347686 stm32_ddr_pmu/time_cnt/ + + 5.014910750 seconds time elapsed --=20 2.43.0 From nobody Sun Oct 5 23:37:45 2025 Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E36F8276027; Mon, 28 Jul 2025 15:35:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.132.182.106 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753716949; cv=none; b=IjXbTh3s9kJ45uCGwcBpUBt9WSiUFEkiQwCwcWT4EUm3gabLBfftJICv/WJMIBqA84TDpxKeUuox+W7m42jdFURPs+zs0zodvfkRkvYoxdyXaFfcZMWtW2+YU3XddQImjCbCZnjAblINRMn4tP/G/G4Tn1S89/SDpzEdOL5uSak= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753716949; c=relaxed/simple; bh=PeN3qmCWQUdwNQs4xuvTgl/wQEdVxnzDNM1iGwMrCyQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=S/qVPmdptF4jD5tQshZgKWp7rcNObBzgVUBZs8O+FUqZKSk4KDhsG+TLQthy9Swa7LMBQ9xKJJaCxn1AEsIAd0dwzjADD5MP8YgUTVa4VwPijE8zBq7v7Y+i7ORL3BvypBN1qjx7TO7RlFwo0o/czwt4LG/sdytHVLn/kTvvKHE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com; spf=pass smtp.mailfrom=foss.st.com; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b=VbMn4Ot9; arc=none smtp.client-ip=185.132.182.106 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=foss.st.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b="VbMn4Ot9" Received: from pps.filterd (m0241204.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 56SEw402011575; Mon, 28 Jul 2025 17:35:17 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=selector1; bh= iltrvkkBDPNUkwWqDFThCKXQjo7LhI+eeBGbd3adnYk=; b=VbMn4Ot9NVluY1dW xjK47cfKv+HqVRSupAxfUkS+Y8AxrPMzP69/5bWMOQm/UaWCK6oc5XUP5lDeEB0Z N3v4XaJoOYgHgUXzvIBckbqQlAn3DD4igMRSmQKLRjmuZPZSHaLy3eKfoU4onK+7 czLXyAvpIKLsFkkTmMtvz/h6P2wQx64yO8zvSBOkxua6DnBVUkKICoCIBGNNCFqf 31q/LyEucApfB4hBVL9TjWevQMQghOeXkw5+PLQopnpZ2WApAIvlT+re18zXCEmv YyqZrp8DwHAyYP3hoZFDjlgaycFYv0OXPOaybGB9ioiPok0KrAhyGP0fhr8BX6Up yRJJkA== Received: from beta.dmz-ap.st.com (beta.dmz-ap.st.com [138.198.100.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 484pc28wbb-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 28 Jul 2025 17:35:17 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 1CD124004D; Mon, 28 Jul 2025 17:33:49 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 13B04787C39; Mon, 28 Jul 2025 17:30:05 +0200 (CEST) Received: from localhost (10.252.23.100) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Mon, 28 Jul 2025 17:30:04 +0200 From: =?utf-8?q?Cl=C3=A9ment_Le_Goffic?= Date: Mon, 28 Jul 2025 17:29:46 +0200 Subject: [PATCH v5 15/20] MAINTAINERS: add myself as STM32 DDR PMU maintainer Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250728-ddrperfm-upstream-v5-15-03f1be8ad396@foss.st.com> References: <20250728-ddrperfm-upstream-v5-0-03f1be8ad396@foss.st.com> In-Reply-To: <20250728-ddrperfm-upstream-v5-0-03f1be8ad396@foss.st.com> To: Will Deacon , Mark Rutland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Philipp Zabel , Jonathan Corbet , Gatien Chevallier , Michael Turquette , Stephen Boyd , Gabriel Fernandez , Krzysztof Kozlowski , Le Goffic , Julius Werner CC: , , , , , , , =?utf-8?q?Cl=C3=A9ment_Le_Goffic?= X-Mailer: b4 0.15-dev-8018a X-ClientProxiedBy: SHFCAS1NODE2.st.com (10.75.129.73) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-28_03,2025-07-28_01,2025-03-28_01 Add Cl=C3=A9ment Le Goffic as STM32 DDR PMU maintainer. Signed-off-by: Cl=C3=A9ment Le Goffic --- MAINTAINERS | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 10850512c118..247f07ae4176 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -23487,6 +23487,13 @@ S: Maintained F: Documentation/devicetree/bindings/power/supply/st,stc3117.yaml F: drivers/power/supply/stc3117_fuel_gauge.c =20 +ST STM32 DDR PMU +M: Cl=C3=A9ment Le Goffic +S: Maintained +F: Documentation/admin-guide/perf/stm32-ddr-pmu.rst +F: Documentation/devicetree/bindings/perf/st,stm32-ddr-pmu.yaml +F: drivers/perf/stm32_ddr-pmu.c + ST STM32 FIREWALL M: Gatien Chevallier S: Maintained --=20 2.43.0 From nobody Sun Oct 5 23:37:45 2025 Received: from mx07-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3534827A92F; Mon, 28 Jul 2025 15:35:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=91.207.212.93 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753716934; cv=none; b=jzBdQq2wSbrjXkWBMZh0AVnHS57YPM+ZwmNBDjtlHQ0xtJi8FIXRI2tZEXuNSKEVUO6jI6uphnbvh32Z65nl8Subq9c/QmoOkOJ/c4VAf/ETMtYEDHYlHLh/TwHRGtJKjmwzO8uo10ivW1u8KDEMg3odIQbePmaLerj3u79gHtE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753716934; c=relaxed/simple; bh=gftIvYHzveImR+MPjt/uzTmWFEBJ3zj0CJjUcncYRD4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=ZQvIoV/ToC8ivpRFo+rNOz2lZx5/pSCjwtGdZno7CiPJm4YOIaKze7u5mfWz7z7zyjCMuNRyAn699Ddj0+uzSV8PzKUHfLvpZNpz4t+tfmlgxExs7iS6Z17nmXFxvkkj5BoBAe98Y3Revm7s/BAaZeVyzNgxz+64EitsOXYZVx0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com; spf=pass smtp.mailfrom=foss.st.com; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b=XvqiPzga; arc=none smtp.client-ip=91.207.212.93 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=foss.st.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b="XvqiPzga" Received: from pps.filterd (m0046660.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 56SFSBDQ025333; Mon, 28 Jul 2025 17:35:17 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=selector1; bh= +oFosf+Y2aWw9hUSMPebh2RDsEkKVFT8bx1JKOIHJNs=; b=XvqiPzgaI7nYwWks o9sIsJZDwVBJ8mZoWfH0fG9ajlDiMRBIL03AbuQUdVE5Atq3LnkqlB2t79LUl+S4 g4QXQvzVBKl3wa5ltaCTm4je/ev47rms4g+fFSRgLlQ4cYoChZq8ZtPse5+yfv6k TaPqTmUweztgvxWq1FtfnOlcYcD9LjGEIVKl1hxBc3sagVNU0U3S4xcydEEV0gzi pwMy6RJpD6FLLEQzStdaRqJoceN3GcoqZFFl4K1PI6dxwdzEE23iLWlt1oowsBJG xOUl+O64tnlQqUb5SI+tm848wyvRWYjzErYo2NVwfvSgExijQFs7GX1dF4RcR8mH XmX96A== Received: from beta.dmz-ap.st.com (beta.dmz-ap.st.com [138.198.100.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 484m590qjy-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 28 Jul 2025 17:35:17 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 91ED240052; Mon, 28 Jul 2025 17:33:49 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 15A3778C90F; Mon, 28 Jul 2025 17:30:06 +0200 (CEST) Received: from localhost (10.252.23.100) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Mon, 28 Jul 2025 17:30:05 +0200 From: =?utf-8?q?Cl=C3=A9ment_Le_Goffic?= Date: Mon, 28 Jul 2025 17:29:47 +0200 Subject: [PATCH v5 16/20] ARM: dts: stm32: add ddrperfm on stm32mp131 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250728-ddrperfm-upstream-v5-16-03f1be8ad396@foss.st.com> References: <20250728-ddrperfm-upstream-v5-0-03f1be8ad396@foss.st.com> In-Reply-To: <20250728-ddrperfm-upstream-v5-0-03f1be8ad396@foss.st.com> To: Will Deacon , Mark Rutland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Philipp Zabel , Jonathan Corbet , Gatien Chevallier , Michael Turquette , Stephen Boyd , Gabriel Fernandez , Krzysztof Kozlowski , Le Goffic , Julius Werner CC: , , , , , , , =?utf-8?q?Cl=C3=A9ment_Le_Goffic?= X-Mailer: b4 0.15-dev-8018a X-ClientProxiedBy: SHFCAS1NODE2.st.com (10.75.129.73) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-28_03,2025-07-28_01,2025-03-28_01 The DDRPERFM is the DDR Performance Monitor embedded in STM32MP131 SoC. Signed-off-by: Cl=C3=A9ment Le Goffic --- arch/arm/boot/dts/st/stm32mp131.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/boot/dts/st/stm32mp131.dtsi b/arch/arm/boot/dts/st/st= m32mp131.dtsi index 492bcf586361..e097723789aa 100644 --- a/arch/arm/boot/dts/st/stm32mp131.dtsi +++ b/arch/arm/boot/dts/st/stm32mp131.dtsi @@ -998,6 +998,13 @@ iwdg2: watchdog@5a002000 { status =3D "disabled"; }; =20 + ddrperfm: perf@5a007000 { + compatible =3D "st,stm32mp131-ddr-pmu"; + reg =3D <0x5a007000 0x400>; + clocks =3D <&rcc DDRPERFM>; + resets =3D <&rcc DDRPERFM_R>; + }; + rtc: rtc@5c004000 { compatible =3D "st,stm32mp1-rtc"; reg =3D <0x5c004000 0x400>; --=20 2.43.0 From nobody Sun Oct 5 23:37:45 2025 Received: from mx08-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5B6C4275B09; Mon, 28 Jul 2025 15:35:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=91.207.212.93 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753716933; cv=none; b=ozb4Ag1JdZU/vqjp1b4w7hrluZ39bDpaYYXkS0IlowYyVtfhc+wqx8CuCz4YX8/grl9GdG/rS9HqzdplyDmOhqeeAstYJvXQwRbELb0rqUVXlZfcZqQOA6agy8WMOXulqFweuobNyBUMN6/QNrgYoGDjOgpMpzq3w3/qm8Adshw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753716933; c=relaxed/simple; bh=pay9TmTh3yLow9rYjWJAd2mCiKrqeCMu+ieuOzNTvQs=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=abF+jaG682QBr1d8Ozh+KpRHdnWN0HJyBXzy/OJqnXo0ugHCxFwytUcRU37LZmuJ8YsZzr5b3AcR1eVfG5BzVmmpboXa21UCmpDi/VAlpQgCaSRyxshJyX2CNBQB4E+6YmbjLfNHsj5zJ0PWaBj3U405GxWiKJOpMB9E73Hq/Ho= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com; spf=pass smtp.mailfrom=foss.st.com; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b=lf5iHL0+; arc=none smtp.client-ip=91.207.212.93 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=foss.st.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b="lf5iHL0+" Received: from pps.filterd (m0369457.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 56SFGkj2005578; Mon, 28 Jul 2025 17:35:16 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=selector1; bh= qThLZiY/wcF/wXoPU6DZ22JEMA0Tul4CRJwH6uwAl+U=; b=lf5iHL0+7DUBSdGL mfVMnrWDcGSa4KXl8h+DQ7ZBYZ2zTNs1gsxF1VycNwwTq/2C4vwcPWArasv1SrIW yKQvdoXlxfJ1576PrMHWD9WkqZQ9eM8vnOPJL6/8deBCKqvnXmgpWJNbKcQC4gV1 XpHNw0fbzCEhAYRzDZOA8lAjOukHmk5QlPaEQmXpjS8jKvdBKfexiJjsKPZXtspk Q0e2bytMWc0Oyh050R5wuvpBRsZ11RGM4bKoD4+saxhEG2qZhHXWVO80ykstWSfl Hv+WcPAGDMCDEglUw3oLD5eTN2GoK2OGpdc+Ef8HkYgeNBWpOQHFKGxILBfudMti KCZinA== Received: from beta.dmz-ap.st.com (beta.dmz-ap.st.com [138.198.100.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 4859yndyug-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 28 Jul 2025 17:35:16 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 9135840051; Mon, 28 Jul 2025 17:33:49 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 1B71F78C90E; Mon, 28 Jul 2025 17:30:07 +0200 (CEST) Received: from localhost (10.252.23.100) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Mon, 28 Jul 2025 17:30:06 +0200 From: =?utf-8?q?Cl=C3=A9ment_Le_Goffic?= Date: Mon, 28 Jul 2025 17:29:48 +0200 Subject: [PATCH v5 17/20] ARM: dts: stm32: add ddrperfm on stm32mp151 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250728-ddrperfm-upstream-v5-17-03f1be8ad396@foss.st.com> References: <20250728-ddrperfm-upstream-v5-0-03f1be8ad396@foss.st.com> In-Reply-To: <20250728-ddrperfm-upstream-v5-0-03f1be8ad396@foss.st.com> To: Will Deacon , Mark Rutland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Philipp Zabel , Jonathan Corbet , Gatien Chevallier , Michael Turquette , Stephen Boyd , Gabriel Fernandez , Krzysztof Kozlowski , Le Goffic , Julius Werner CC: , , , , , , , =?utf-8?q?Cl=C3=A9ment_Le_Goffic?= X-Mailer: b4 0.15-dev-8018a X-ClientProxiedBy: SHFCAS1NODE2.st.com (10.75.129.73) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-28_03,2025-07-28_01,2025-03-28_01 The DDRPERFM is the DDR Performance Monitor embedded in STM32MP151 SoC. Signed-off-by: Cl=C3=A9ment Le Goffic --- arch/arm/boot/dts/st/stm32mp151.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/boot/dts/st/stm32mp151.dtsi b/arch/arm/boot/dts/st/st= m32mp151.dtsi index 0daa8ffe2ff5..e121de52a054 100644 --- a/arch/arm/boot/dts/st/stm32mp151.dtsi +++ b/arch/arm/boot/dts/st/stm32mp151.dtsi @@ -383,6 +383,13 @@ usbphyc_port1: usb-phy@1 { }; }; =20 + ddrperfm: perf@5a007000 { + compatible =3D "st,stm32mp151-ddr-pmu", "st,stm32mp131-ddr-pmu"; + reg =3D <0x5a007000 0x400>; + clocks =3D <&rcc DDRPERFM>; + resets =3D <&rcc DDRPERFM_R>; + }; + rtc: rtc@5c004000 { compatible =3D "st,stm32mp1-rtc"; reg =3D <0x5c004000 0x400>; --=20 2.43.0 From nobody Sun Oct 5 23:37:45 2025 Received: from mx07-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CA52F275AFE; Mon, 28 Jul 2025 15:35:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=91.207.212.93 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753716932; cv=none; b=T7yf39BbBUhTamBk3jG86hZp+9NBcOscYh4QzhhN1RNP8PsN7+e1nupblwpnfmz5TpvlmdFxy7rukoEfA5TK7vD9TkE26y3tSJxG10U9APllL6sQmr0TMWtWviassVNbXNdvZDrWDFlEhfsc+T+pkgsGXcTietjJD9SUyhsg8FY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753716932; c=relaxed/simple; bh=jDxrKSVKGmymiWgFfc3XLLghQxyNU894E3heEmmTqGc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=IkudYoBXlkmOsZmil0xHrjIlCaN42zgCMpMJBl0v1dDwRCwoabgvC8zTZHYHfN4yDF+Z8t1rHFnSlmL0nrOI3/ooy3TUIfCNLk7H0y2avEwhnRV7r7Cm/bEb7Ti22XkGTzpWPdmp4AH5HptzHT57FKBw4Lp2+VhPklU2/OL4faM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com; spf=pass smtp.mailfrom=foss.st.com; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b=qaWex+LS; arc=none smtp.client-ip=91.207.212.93 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=foss.st.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b="qaWex+LS" Received: from pps.filterd (m0046661.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 56SDEpoJ022333; Mon, 28 Jul 2025 17:35:16 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=selector1; bh= SuBSodyyqcKAz1sJaFnr1XdxWrUs+npg1uqS49q9/0Y=; b=qaWex+LSbuZ/CU1u uUC4wpY4f6VttcJ1B/iAHV+5lgVkOqk4zWBnKkhG4ZawCkuKO5+iFlSL5p1HhNp1 Rp3gYsAEyt0Qatr2LJOYsJ2qEUFKFoGiJjZEm6PxPT48NEAIE/OKdr+d/KxPWutF NzXBDG2zm0iKjeRJEB2wtjkfmAHKKrvgMWLQxum/mNSAJokm85xyUu4xLQEsxxl1 X35WtWQ9Exb795U7WJsrHlbchAJozDNk/B5Gz3R+cphCSF6NcQQDVSy03+J+eSe5 L5QDsu5ZbPbzPO8WDhEr2/a5GxPeSMkqu5oxRHGXodGY2QnHw10Blx/sGUSrBYNW 3uC01g== Received: from beta.dmz-ap.st.com (beta.dmz-ap.st.com [138.198.100.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 484nwgge41-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 28 Jul 2025 17:35:16 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 94BEA40053; Mon, 28 Jul 2025 17:33:49 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 23C2C78C910; Mon, 28 Jul 2025 17:30:08 +0200 (CEST) Received: from localhost (10.252.23.100) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Mon, 28 Jul 2025 17:30:07 +0200 From: =?utf-8?q?Cl=C3=A9ment_Le_Goffic?= Date: Mon, 28 Jul 2025 17:29:49 +0200 Subject: [PATCH v5 18/20] arm64: dts: st: add ddrperfm on stm32mp251 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250728-ddrperfm-upstream-v5-18-03f1be8ad396@foss.st.com> References: <20250728-ddrperfm-upstream-v5-0-03f1be8ad396@foss.st.com> In-Reply-To: <20250728-ddrperfm-upstream-v5-0-03f1be8ad396@foss.st.com> To: Will Deacon , Mark Rutland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Philipp Zabel , Jonathan Corbet , Gatien Chevallier , Michael Turquette , Stephen Boyd , Gabriel Fernandez , Krzysztof Kozlowski , Le Goffic , Julius Werner CC: , , , , , , , =?utf-8?q?Cl=C3=A9ment_Le_Goffic?= X-Mailer: b4 0.15-dev-8018a X-ClientProxiedBy: SHFCAS1NODE2.st.com (10.75.129.73) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-28_03,2025-07-28_01,2025-03-28_01 The DDRPERFM is the DDR Performance Monitor embedded in STM32MP251 SoC. Keep the node disabled at SoC level as it requires the property `st,dram-type` which is provided in board dtsi file. Signed-off-by: Cl=C3=A9ment Le Goffic --- arch/arm64/boot/dts/st/stm32mp251.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/s= t/stm32mp251.dtsi index 0683c2d5cb6f..7f138324610a 100644 --- a/arch/arm64/boot/dts/st/stm32mp251.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi @@ -1577,5 +1577,12 @@ exti2: interrupt-controller@46230000 { <0>, <&intc GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>; /* EXTI_70 */ }; + + ddrperfm: perf@48041000 { + compatible =3D "st,stm32mp251-ddr-pmu"; + reg =3D <0x48041000 0x400>; + access-controllers =3D <&rcc 104>; + status =3D "disabled"; + }; }; }; --=20 2.43.0 From nobody Sun Oct 5 23:37:45 2025 Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F304227C162; Mon, 28 Jul 2025 15:35:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.132.182.106 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753716934; cv=none; b=fenOnfZTnvGBA6EzEvd8zPDsnTQIazauO1fqMyJxNvHV+SluCwHRvlLbF5cEDjFn0VrFFLd1KNS1sqwZVnlc3UQK0RPi2Xkm5hERLdN+fhnWxozfbjSeusaMpDYTN9NixBXli48ITOLShKZJP6qAdjXUIEk51iuwNzAdKPvEuIo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753716934; c=relaxed/simple; bh=c5RN1PJ2jWZpcD31tgu2dPIQqUIfEUl+l6dcon/cpoo=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=L0oPw2JfuWJT/7AWYdFqk5qQyemeFISdMQNGny93OicM5H1Emrfnn2c8SCHvxrDUT8GuYa7LJLFas1Ne8NufC5i3l2MML2GIvKisll8+kadayxx1LMHK5VRHd5LCOFmQ0FyNZpk4uoXj0w2S9DguLRycEo8UCfIOnIC7kB0yR/w= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com; spf=pass smtp.mailfrom=foss.st.com; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b=oApuPc79; arc=none smtp.client-ip=185.132.182.106 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=foss.st.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b="oApuPc79" Received: from pps.filterd (m0369458.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 56SCE6sR026923; Mon, 28 Jul 2025 17:35:17 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=selector1; bh= eJrc2cACDhSOzVDLTaVrQsrujHpWGGs7dlhdmyDAAho=; b=oApuPc79eip//KOw wyvdk0iBp0R8FtiJrBLJmUDNQi5qMb2T9WZT0xRmmTu3VGO5svUgaCwhD6ubgyDe C/YMW97AYfDscRZ76/MR8KAciBqgDS4YatMLUASlWPu6KCpKIEXdhw6xkQ8CaQJD FEcXK+COmKrFzXXiO+4yc8pUD+zceQP241ADLVS+kfI7NXG+/Mq4kVO2cO072ZWB Goy+zoox1y2ydECaUoLQQKOovz/mJ2wo5zO6n9wSrHbOm3YZ2xwSOunQC13WG6wr rgJ/0//HCVnemyL2nF9MkCPzmtj2jT8aywr8aoFUuwjEBNe0SsqSn+DSo0s7Mtlh wGPedQ== Received: from beta.dmz-ap.st.com (beta.dmz-ap.st.com [138.198.100.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 4858k4x9nv-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 28 Jul 2025 17:35:17 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 9517040054; Mon, 28 Jul 2025 17:33:49 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 2CAA178C913; Mon, 28 Jul 2025 17:30:09 +0200 (CEST) Received: from localhost (10.252.23.100) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Mon, 28 Jul 2025 17:30:08 +0200 From: =?utf-8?q?Cl=C3=A9ment_Le_Goffic?= Date: Mon, 28 Jul 2025 17:29:50 +0200 Subject: [PATCH v5 19/20] arm64: dts: st: support ddrperfm on stm32mp257f-dk Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250728-ddrperfm-upstream-v5-19-03f1be8ad396@foss.st.com> References: <20250728-ddrperfm-upstream-v5-0-03f1be8ad396@foss.st.com> In-Reply-To: <20250728-ddrperfm-upstream-v5-0-03f1be8ad396@foss.st.com> To: Will Deacon , Mark Rutland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Philipp Zabel , Jonathan Corbet , Gatien Chevallier , Michael Turquette , Stephen Boyd , Gabriel Fernandez , Krzysztof Kozlowski , Le Goffic , Julius Werner CC: , , , , , , , =?utf-8?q?Cl=C3=A9ment_Le_Goffic?= X-Mailer: b4 0.15-dev-8018a X-ClientProxiedBy: SHFCAS1NODE2.st.com (10.75.129.73) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-28_03,2025-07-28_01,2025-03-28_01 Configure DDRPERFM node on stm32mp257f-dk board. Disable the node as DDRPERFM will produce an error message if it's clock (shared with the DDRCTRL on STM32MP25x) is secured by common bootloaders. Signed-off-by: Cl=C3=A9ment Le Goffic --- arch/arm64/boot/dts/st/stm32mp257f-dk.dts | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp257f-dk.dts b/arch/arm64/boot/dt= s/st/stm32mp257f-dk.dts index 45ffa358c800..81b115280bd4 100644 --- a/arch/arm64/boot/dts/st/stm32mp257f-dk.dts +++ b/arch/arm64/boot/dts/st/stm32mp257f-dk.dts @@ -84,6 +84,11 @@ &arm_wdt { status =3D "okay"; }; =20 +&ddrperfm { + memory-channel =3D <&lpddr_channel>; + status =3D "disabled"; +}; + &scmi_regu { scmi_vddio1: regulator@0 { regulator-min-microvolt =3D <1800000>; --=20 2.43.0 From nobody Sun Oct 5 23:37:45 2025 Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A0DBF274B5F; Mon, 28 Jul 2025 15:35:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.132.182.106 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753716922; cv=none; b=rcFZ7B6QeJDk38hWbu2VFflTYPJhCncnlK1ZBJCwK5vNHuvwKMUznxq2wjCYqO2mXaiBRFNjQvQ7HaRv1PIH/UFcUKw5QEIU8AKivlDFVzBSeaLaDIEHQ+7wfbGPuFelHhdKuWfrmW8PFeRX2EW/HqzI/QNseeStkU0IFkQVTlM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753716922; c=relaxed/simple; bh=dsBC3EguWry8hjqdSMJSjmmwvKBOhx+LpeiASpxU3JM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=SGYFDPHnak6ZqzzEkOGyx1IwbG4hQOUSYWbaPAzpMhViLvorOi29nGYXgyBFHG4Pujsv3QWwhOLYMGZrofaW0ddeIBisHIa+YpmeylJPVLtsP69USfKRKrJiZVvpTI5no9hrfRr01tpyMaNw4UGraeejXn279ZotMRDGwscsV1o= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com; spf=pass smtp.mailfrom=foss.st.com; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b=Q8MSKWUb; arc=none smtp.client-ip=185.132.182.106 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=foss.st.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b="Q8MSKWUb" Received: from pps.filterd (m0288072.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 56SFGvgq026171; Mon, 28 Jul 2025 17:35:04 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=selector1; bh= yH22w/zX/Kh1SA0KcC16iKvtnozL0k8lEkuhUtR9r24=; b=Q8MSKWUbBp6+r5T/ 9h+LdGEEL/+wW/yKzywpJj+HhfcBvbP+0nFRYvl0yjFQ+KOghi9zvmLf7+iXtZzh sVT9k33OHPWvzMwatwFrMQLF8p/6eyjND9UWutat07dB5J8UrRP9+7vC2O0NAriz H47L0OGNVLHPLLsiP2VyCRqJc9VTe6f8u0HEr8homm2KgmuCKwb6UIzxgAWuOt4H BGayJGpFsm6cViMGJP3YxII6f0Pj+kMACZBW6aBbPm4HefwimLqLUovqbdrUgW9d FZCKWzPl2yDeMpCz1uP4sDZPsbU7gzWBwNrIeBf4msFv/O+WaMK+ZhEsQ6e+1Y69 BDEVNQ== Received: from beta.dmz-ap.st.com (beta.dmz-ap.st.com [138.198.100.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 484memhajd-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 28 Jul 2025 17:35:04 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id CCD2840044; Mon, 28 Jul 2025 17:33:48 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 3829378C911; Mon, 28 Jul 2025 17:30:10 +0200 (CEST) Received: from localhost (10.252.23.100) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Mon, 28 Jul 2025 17:30:09 +0200 From: =?utf-8?q?Cl=C3=A9ment_Le_Goffic?= Date: Mon, 28 Jul 2025 17:29:51 +0200 Subject: [PATCH v5 20/20] arm64: dts: st: support ddrperfm on stm32mp257f-ev1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250728-ddrperfm-upstream-v5-20-03f1be8ad396@foss.st.com> References: <20250728-ddrperfm-upstream-v5-0-03f1be8ad396@foss.st.com> In-Reply-To: <20250728-ddrperfm-upstream-v5-0-03f1be8ad396@foss.st.com> To: Will Deacon , Mark Rutland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Philipp Zabel , Jonathan Corbet , Gatien Chevallier , Michael Turquette , Stephen Boyd , Gabriel Fernandez , Krzysztof Kozlowski , Le Goffic , Julius Werner CC: , , , , , , , =?utf-8?q?Cl=C3=A9ment_Le_Goffic?= X-Mailer: b4 0.15-dev-8018a X-ClientProxiedBy: SHFCAS1NODE2.st.com (10.75.129.73) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-28_03,2025-07-28_01,2025-03-28_01 Configure DDRPERFM node on stm32mp257f-ev1 board. Disable the node as DDRPERFM will produce an error message if it's clock (shared with the DDRCTRL on STM32MP25x) is secured by common bootloaders. Signed-off-by: Cl=C3=A9ment Le Goffic --- arch/arm64/boot/dts/st/stm32mp257f-ev1.dts | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts b/arch/arm64/boot/d= ts/st/stm32mp257f-ev1.dts index e11ce66be948..3d1e2000f631 100644 --- a/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts +++ b/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts @@ -130,6 +130,11 @@ csi_source: endpoint { }; }; =20 +&ddrperfm { + memory-channel =3D <&ddr_channel>; + status =3D "disabled"; +}; + &dcmipp { status =3D "okay"; port { --=20 2.43.0