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[46.142.11.190]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3b778eb284fsm5621555f8f.12.2025.07.27.04.48.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 27 Jul 2025 04:48:05 -0700 (PDT) From: Jonas Jelonek To: linux-i2c@vger.kernel.org, Chris Packham , Andi Shyti , Rob Herring , Krzysztof Kozlowski , Conor Dooley , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Markus Stockhausen , Jonas Jelonek Subject: [PATCH v3 1/3] i2c: rework RTL9300 I2C controller driver Date: Sun, 27 Jul 2025 11:47:58 +0000 Message-ID: <20250727114800.3046-2-jelonek.jonas@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250727114800.3046-1-jelonek.jonas@gmail.com> References: <20250727114800.3046-1-jelonek.jonas@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Rework the RTL9300 I2C controller driver to use more of the regmap API, especially make use of reg_field and regmap_field to represent registers instead of macros. Most register operations are performed through regmap_field_* API then. Handle SCL selection using separate chip-specific functions since this is already known to differ between the Realtek SoC families in such a way that this cannot be properly handled using just a different reg_field. These changes make it a lot easier to add support for newer generations or to handle differences between specific revisions within a series. Support can be added by defining a separate driver data structure with the corresponding register field definitions and linking it to a new compatible string. Reviewed-by: Chris Packham Tested-by: Chris Packham # On RTL9302c Signed-off-by: Jonas Jelonek --- drivers/i2c/busses/i2c-rtl9300.c | 190 ++++++++++++++++++++----------- 1 file changed, 124 insertions(+), 66 deletions(-) diff --git a/drivers/i2c/busses/i2c-rtl9300.c b/drivers/i2c/busses/i2c-rtl9= 300.c index e064e8a4a1f0..f8e81102ee74 100644 --- a/drivers/i2c/busses/i2c-rtl9300.c +++ b/drivers/i2c/busses/i2c-rtl9300.c @@ -23,94 +23,115 @@ struct rtl9300_i2c_chan { u8 sda_pin; }; =20 +enum rtl9300_i2c_reg_scope { + REG_SCOPE_GLOBAL, + REG_SCOPE_MASTER, +}; + +struct rtl9300_i2c_reg_field { + struct reg_field field; + enum rtl9300_i2c_reg_scope scope; +}; + +enum rtl9300_i2c_reg_fields { + F_DATA_WIDTH =3D 0, + F_DEV_ADDR, + F_I2C_FAIL, + F_I2C_TRIG, + F_MEM_ADDR, + F_MEM_ADDR_WIDTH, + F_RD_MODE, + F_RWOP, + F_SCL_FREQ, + F_SCL_SEL, + F_SDA_OUT_SEL, + F_SDA_SEL, + + /* keep last */ + F_NUM_FIELDS +}; + +struct rtl9300_i2c_drv_data { + struct rtl9300_i2c_reg_field field_desc[F_NUM_FIELDS]; + int (*select_scl)(struct rtl9300_i2c *i2c, u8 scl); + u32 data_reg; + u8 max_nchan; +}; + #define RTL9300_I2C_MUX_NCHAN 8 =20 struct rtl9300_i2c { struct regmap *regmap; struct device *dev; struct rtl9300_i2c_chan chans[RTL9300_I2C_MUX_NCHAN]; + struct regmap_field *fields[F_NUM_FIELDS]; u32 reg_base; + u32 data_reg; u8 sda_pin; struct mutex lock; }; =20 #define RTL9300_I2C_MST_CTRL1 0x0 -#define RTL9300_I2C_MST_CTRL1_MEM_ADDR_OFS 8 -#define RTL9300_I2C_MST_CTRL1_MEM_ADDR_MASK GENMASK(31, 8) -#define RTL9300_I2C_MST_CTRL1_SDA_OUT_SEL_OFS 4 -#define RTL9300_I2C_MST_CTRL1_SDA_OUT_SEL_MASK GENMASK(6, 4) -#define RTL9300_I2C_MST_CTRL1_GPIO_SCL_SEL BIT(3) -#define RTL9300_I2C_MST_CTRL1_RWOP BIT(2) -#define RTL9300_I2C_MST_CTRL1_I2C_FAIL BIT(1) -#define RTL9300_I2C_MST_CTRL1_I2C_TRIG BIT(0) #define RTL9300_I2C_MST_CTRL2 0x4 -#define RTL9300_I2C_MST_CTRL2_RD_MODE BIT(15) -#define RTL9300_I2C_MST_CTRL2_DEV_ADDR_OFS 8 -#define RTL9300_I2C_MST_CTRL2_DEV_ADDR_MASK GENMASK(14, 8) -#define RTL9300_I2C_MST_CTRL2_DATA_WIDTH_OFS 4 -#define RTL9300_I2C_MST_CTRL2_DATA_WIDTH_MASK GENMASK(7, 4) -#define RTL9300_I2C_MST_CTRL2_MEM_ADDR_WIDTH_OFS 2 -#define RTL9300_I2C_MST_CTRL2_MEM_ADDR_WIDTH_MASK GENMASK(3, 2) -#define RTL9300_I2C_MST_CTRL2_SCL_FREQ_OFS 0 -#define RTL9300_I2C_MST_CTRL2_SCL_FREQ_MASK GENMASK(1, 0) #define RTL9300_I2C_MST_DATA_WORD0 0x8 #define RTL9300_I2C_MST_DATA_WORD1 0xc #define RTL9300_I2C_MST_DATA_WORD2 0x10 #define RTL9300_I2C_MST_DATA_WORD3 0x14 - #define RTL9300_I2C_MST_GLB_CTRL 0x384 =20 + static int rtl9300_i2c_reg_addr_set(struct rtl9300_i2c *i2c, u32 reg, u16 = len) { - u32 val, mask; int ret; =20 - val =3D len << RTL9300_I2C_MST_CTRL2_MEM_ADDR_WIDTH_OFS; - mask =3D RTL9300_I2C_MST_CTRL2_MEM_ADDR_WIDTH_MASK; - - ret =3D regmap_update_bits(i2c->regmap, i2c->reg_base + RTL9300_I2C_MST_C= TRL2, mask, val); + ret =3D regmap_field_write(i2c->fields[F_MEM_ADDR_WIDTH], len); if (ret) return ret; =20 - val =3D reg << RTL9300_I2C_MST_CTRL1_MEM_ADDR_OFS; - mask =3D RTL9300_I2C_MST_CTRL1_MEM_ADDR_MASK; + return regmap_field_write(i2c->fields[F_MEM_ADDR], reg); +} =20 - return regmap_update_bits(i2c->regmap, i2c->reg_base + RTL9300_I2C_MST_CT= RL1, mask, val); +static int rtl9300_i2c_select_scl(struct rtl9300_i2c *i2c, u8 scl) +{ + return regmap_field_write(i2c->fields[F_SCL_SEL], 1); } =20 static int rtl9300_i2c_config_io(struct rtl9300_i2c *i2c, u8 sda_pin) { + struct rtl9300_i2c_drv_data *drv_data; int ret; - u32 val, mask; =20 - ret =3D regmap_update_bits(i2c->regmap, RTL9300_I2C_MST_GLB_CTRL, BIT(sda= _pin), BIT(sda_pin)); + drv_data =3D (struct rtl9300_i2c_drv_data *)device_get_match_data(i2c->de= v); + + ret =3D regmap_field_update_bits(i2c->fields[F_SDA_SEL], BIT(sda_pin), BI= T(sda_pin)); if (ret) return ret; =20 - val =3D (sda_pin << RTL9300_I2C_MST_CTRL1_SDA_OUT_SEL_OFS) | - RTL9300_I2C_MST_CTRL1_GPIO_SCL_SEL; - mask =3D RTL9300_I2C_MST_CTRL1_SDA_OUT_SEL_MASK | RTL9300_I2C_MST_CTRL1_G= PIO_SCL_SEL; + ret =3D regmap_field_write(i2c->fields[F_SDA_OUT_SEL], sda_pin); + if (ret) + return ret; =20 - return regmap_update_bits(i2c->regmap, i2c->reg_base + RTL9300_I2C_MST_CT= RL1, mask, val); + return drv_data->select_scl(i2c, 0); } =20 static int rtl9300_i2c_config_xfer(struct rtl9300_i2c *i2c, struct rtl9300= _i2c_chan *chan, u16 addr, u16 len) { - u32 val, mask; - - val =3D chan->bus_freq << RTL9300_I2C_MST_CTRL2_SCL_FREQ_OFS; - mask =3D RTL9300_I2C_MST_CTRL2_SCL_FREQ_MASK; + int ret; =20 - val |=3D addr << RTL9300_I2C_MST_CTRL2_DEV_ADDR_OFS; - mask |=3D RTL9300_I2C_MST_CTRL2_DEV_ADDR_MASK; + ret =3D regmap_field_write(i2c->fields[F_SCL_FREQ], chan->bus_freq); + if (ret) + return ret; =20 - val |=3D ((len - 1) & 0xf) << RTL9300_I2C_MST_CTRL2_DATA_WIDTH_OFS; - mask |=3D RTL9300_I2C_MST_CTRL2_DATA_WIDTH_MASK; + ret =3D regmap_field_write(i2c->fields[F_DEV_ADDR], addr); + if (ret) + return ret; =20 - mask |=3D RTL9300_I2C_MST_CTRL2_RD_MODE; + ret =3D regmap_field_write(i2c->fields[F_DATA_WIDTH], (len - 1) & 0xf); + if (ret) + return ret; =20 - return regmap_update_bits(i2c->regmap, i2c->reg_base + RTL9300_I2C_MST_CT= RL2, mask, val); + return regmap_field_write(i2c->fields[F_RD_MODE], 0); } =20 static int rtl9300_i2c_read(struct rtl9300_i2c *i2c, u8 *buf, int len) @@ -121,8 +142,7 @@ static int rtl9300_i2c_read(struct rtl9300_i2c *i2c, u8= *buf, int len) if (len > 16) return -EIO; =20 - ret =3D regmap_bulk_read(i2c->regmap, i2c->reg_base + RTL9300_I2C_MST_DAT= A_WORD0, - vals, ARRAY_SIZE(vals)); + ret =3D regmap_bulk_read(i2c->regmap, i2c->data_reg, vals, ARRAY_SIZE(val= s)); if (ret) return ret; =20 @@ -149,49 +169,46 @@ static int rtl9300_i2c_write(struct rtl9300_i2c *i2c,= u8 *buf, int len) vals[i/4] |=3D buf[i]; } =20 - return regmap_bulk_write(i2c->regmap, i2c->reg_base + RTL9300_I2C_MST_DAT= A_WORD0, - vals, ARRAY_SIZE(vals)); + return regmap_bulk_write(i2c->regmap, i2c->data_reg, vals, ARRAY_SIZE(val= s)); } =20 static int rtl9300_i2c_writel(struct rtl9300_i2c *i2c, u32 data) { - return regmap_write(i2c->regmap, i2c->reg_base + RTL9300_I2C_MST_DATA_WOR= D0, data); + return regmap_write(i2c->regmap, i2c->data_reg, data); } =20 static int rtl9300_i2c_execute_xfer(struct rtl9300_i2c *i2c, char read_wri= te, int size, union i2c_smbus_data *data, int len) { - u32 val, mask; + u32 val; int ret; =20 - val =3D read_write =3D=3D I2C_SMBUS_WRITE ? RTL9300_I2C_MST_CTRL1_RWOP : = 0; - mask =3D RTL9300_I2C_MST_CTRL1_RWOP; - - val |=3D RTL9300_I2C_MST_CTRL1_I2C_TRIG; - mask |=3D RTL9300_I2C_MST_CTRL1_I2C_TRIG; + ret =3D regmap_field_write(i2c->fields[F_RWOP], read_write =3D=3D I2C_SMB= US_WRITE); + if (ret) + return ret; =20 - ret =3D regmap_update_bits(i2c->regmap, i2c->reg_base + RTL9300_I2C_MST_C= TRL1, mask, val); + ret =3D regmap_field_write(i2c->fields[F_I2C_TRIG], 1); if (ret) return ret; =20 - ret =3D regmap_read_poll_timeout(i2c->regmap, i2c->reg_base + RTL9300_I2C= _MST_CTRL1, - val, !(val & RTL9300_I2C_MST_CTRL1_I2C_TRIG), 100, 2000); + regmap_field_read_poll_timeout(i2c->fields[F_I2C_TRIG], val, !val, 100, 2= 000); if (ret) return ret; =20 - if (val & RTL9300_I2C_MST_CTRL1_I2C_FAIL) + ret =3D regmap_field_read(i2c->fields[F_I2C_FAIL], &val); + if (ret) + return ret; + if (val) return -EIO; =20 if (read_write =3D=3D I2C_SMBUS_READ) { if (size =3D=3D I2C_SMBUS_BYTE || size =3D=3D I2C_SMBUS_BYTE_DATA) { - ret =3D regmap_read(i2c->regmap, - i2c->reg_base + RTL9300_I2C_MST_DATA_WORD0, &val); + ret =3D regmap_read(i2c->regmap, i2c->data_reg, &val); if (ret) return ret; data->byte =3D val & 0xff; } else if (size =3D=3D I2C_SMBUS_WORD_DATA) { - ret =3D regmap_read(i2c->regmap, - i2c->reg_base + RTL9300_I2C_MST_DATA_WORD0, &val); + ret =3D regmap_read(i2c->regmap, i2c->data_reg, &val); if (ret) return ret; data->word =3D val & 0xffff; @@ -331,6 +348,8 @@ static int rtl9300_i2c_probe(struct platform_device *pd= ev) u32 clock_freq, sda_pin; int ret, i =3D 0; struct fwnode_handle *child; + struct rtl9300_i2c_drv_data *drv_data; + struct reg_field fields[F_NUM_FIELDS]; =20 i2c =3D devm_kzalloc(dev, sizeof(*i2c), GFP_KERNEL); if (!i2c) @@ -349,9 +368,22 @@ static int rtl9300_i2c_probe(struct platform_device *p= dev) =20 platform_set_drvdata(pdev, i2c); =20 - if (device_get_child_node_count(dev) >=3D RTL9300_I2C_MUX_NCHAN) + drv_data =3D (struct rtl9300_i2c_drv_data *)device_get_match_data(i2c->de= v); + if (device_get_child_node_count(dev) >=3D drv_data->max_nchan) return dev_err_probe(dev, -EINVAL, "Too many channels\n"); =20 + i2c->data_reg =3D i2c->reg_base + drv_data->data_reg; + for (i =3D 0; i < F_NUM_FIELDS; i++) { + fields[i] =3D drv_data->field_desc[i].field; + if (drv_data->field_desc[i].scope =3D=3D REG_SCOPE_MASTER) + fields[i].reg +=3D i2c->reg_base; + } + ret =3D devm_regmap_field_bulk_alloc(dev, i2c->regmap, i2c->fields, + fields, F_NUM_FIELDS); + if (ret) + return ret; + + i =3D 0; device_for_each_child_node(dev, child) { struct rtl9300_i2c_chan *chan =3D &i2c->chans[i]; struct i2c_adapter *adap =3D &chan->adap; @@ -400,11 +432,37 @@ static int rtl9300_i2c_probe(struct platform_device *= pdev) return 0; } =20 +#define GLB_REG_FIELD(reg, msb, lsb) \ + { .field =3D REG_FIELD(reg, msb, lsb), .scope =3D REG_SCOPE_GLOBAL } +#define MST_REG_FIELD(reg, msb, lsb) \ + { .field =3D REG_FIELD(reg, msb, lsb), .scope =3D REG_SCOPE_MASTER } + +static const struct rtl9300_i2c_drv_data rtl9300_i2c_drv_data =3D { + .field_desc =3D { + [F_MEM_ADDR] =3D MST_REG_FIELD(RTL9300_I2C_MST_CTRL1, 8, 31), + [F_SDA_OUT_SEL] =3D MST_REG_FIELD(RTL9300_I2C_MST_CTRL1, 4, 6), + [F_SCL_SEL] =3D MST_REG_FIELD(RTL9300_I2C_MST_CTRL1, 3, 3), + [F_RWOP] =3D MST_REG_FIELD(RTL9300_I2C_MST_CTRL1, 2, 2), + [F_I2C_FAIL] =3D MST_REG_FIELD(RTL9300_I2C_MST_CTRL1, 1, 1), + [F_I2C_TRIG] =3D MST_REG_FIELD(RTL9300_I2C_MST_CTRL1, 0, 0), + [F_RD_MODE] =3D MST_REG_FIELD(RTL9300_I2C_MST_CTRL2, 15, 15), + [F_DEV_ADDR] =3D MST_REG_FIELD(RTL9300_I2C_MST_CTRL2, 8, 14), + [F_DATA_WIDTH] =3D MST_REG_FIELD(RTL9300_I2C_MST_CTRL2, 4, 7), + [F_MEM_ADDR_WIDTH] =3D MST_REG_FIELD(RTL9300_I2C_MST_CTRL2, 2, 3), + [F_SCL_FREQ] =3D MST_REG_FIELD(RTL9300_I2C_MST_CTRL2, 0, 1), + [F_SDA_SEL] =3D GLB_REG_FIELD(RTL9300_I2C_MST_GLB_CTRL, 0, 7), + }, + .select_scl =3D rtl9300_i2c_select_scl, + .data_reg =3D RTL9300_I2C_MST_DATA_WORD0, + .max_nchan =3D RTL9300_I2C_MUX_NCHAN, +}; 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[46.142.11.190]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3b778eb284fsm5621555f8f.12.2025.07.27.04.48.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 27 Jul 2025 04:48:06 -0700 (PDT) From: Jonas Jelonek To: linux-i2c@vger.kernel.org, Chris Packham , Andi Shyti , Rob Herring , Krzysztof Kozlowski , Conor Dooley , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Markus Stockhausen , Jonas Jelonek Subject: [PATCH v3 2/3] dt-bindings: i2c: realtek,rtl9301-i2c: extend for RTL9310 support Date: Sun, 27 Jul 2025 11:47:59 +0000 Message-ID: <20250727114800.3046-3-jelonek.jonas@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250727114800.3046-1-jelonek.jonas@gmail.com> References: <20250727114800.3046-1-jelonek.jonas@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add dt-bindings for RTL9310 series I2C controller. Adjust the regex for child-node address to account for the fact that RTL9310 supports 12 instead of only 8 SDA lines. Also, narrow this per variant. Add a vendor-specific property to explicitly specify the Realtek-internal ID of the defined I2C controller/master. This is required, in particular for RTL9310, to describe the correct I2C master. Require this property for RTL9310. Add compatibles for known SoC variants RTL9311, RTL9312 and RTL9313. Signed-off-by: Jonas Jelonek --- .../bindings/i2c/realtek,rtl9301-i2c.yaml | 58 +++++++++++++++++-- 1 file changed, 53 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/i2c/realtek,rtl9301-i2c.yaml= b/Documentation/devicetree/bindings/i2c/realtek,rtl9301-i2c.yaml index 69ac5db8b914..29676e99a8c3 100644 --- a/Documentation/devicetree/bindings/i2c/realtek,rtl9301-i2c.yaml +++ b/Documentation/devicetree/bindings/i2c/realtek,rtl9301-i2c.yaml @@ -10,9 +10,11 @@ maintainers: - Chris Packham =20 description: - The RTL9300 SoC has two I2C controllers. Each of these has an SCL line (= which - if not-used for SCL can be a GPIO). There are 8 common SDA lines that ca= n be - assigned to either I2C controller. + The RTL9300 SoCs have two I2C controllers. Each of these has an SCL line + (which if not-used for SCL can be a GPIO). There are 8 common SDA lines + that can be assigned to either I2C controller. + The RTL9310 SoCs have equal capabilities but support 12 common SDA lines + which can be assigned to either I2C controller. =20 properties: compatible: @@ -23,7 +25,15 @@ properties: - realtek,rtl9302c-i2c - realtek,rtl9303-i2c - const: realtek,rtl9301-i2c - - const: realtek,rtl9301-i2c + - items: + - enum: + - realtek,rtl9311-i2c + - realtek,rtl9312-i2c + - realtek,rtl9313-i2c + - const: realtek,rtl9310-i2c + - enum: + - realtek,rtl9301-i2c + - realtek,rtl9310-i2c =20 reg: items: @@ -35,8 +45,15 @@ properties: "#size-cells": const: 0 =20 + realtek,mst-id: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Realtek-internal ID of the I2C controller/master. + minimum: 1 + maximum: 2 + patternProperties: - '^i2c@[0-7]$': + '^i2c@([0-9]|1[0-1])$': $ref: /schemas/i2c/i2c-controller.yaml unevaluatedProperties: false =20 @@ -48,6 +65,25 @@ patternProperties: required: - reg =20 + +allOf: + - if: + properties: + compatible: + contains: + const: realtek,rtl9310-i2c + then: + required: + - realtek,mst-id + - if: + properties: + compatible: + contains: + const: realtek,rtl9301-i2c + then: + patternProperties: + '^i2c@([8-9]|1[0-1])$': false + required: - compatible - reg @@ -68,3 +104,15 @@ examples: #size-cells =3D <0>; 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[46.142.11.190]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3b778eb284fsm5621555f8f.12.2025.07.27.04.48.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 27 Jul 2025 04:48:07 -0700 (PDT) From: Jonas Jelonek To: linux-i2c@vger.kernel.org, Chris Packham , Andi Shyti , Rob Herring , Krzysztof Kozlowski , Conor Dooley , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Markus Stockhausen , Jonas Jelonek Subject: [PATCH v3 3/3] i2c: add RTL9310 support to RTL9300 I2C controller driver Date: Sun, 27 Jul 2025 11:48:00 +0000 Message-ID: <20250727114800.3046-4-jelonek.jonas@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250727114800.3046-1-jelonek.jonas@gmail.com> References: <20250727114800.3046-1-jelonek.jonas@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add support for the internal I2C controllers of RTL9310 series based SoCs to the driver for RTL9300. Add register definitions, chip-specific functions and compatible strings for known RTL9310-based SoCs RTL9311, RTL9312 and RTL9313. Make use of a new device tree property 'realtek,mst-id' which needs to be specified in case both or only the second master is used. This is required due how the register layout changed in contrast to RTL9300, which has SCL selection in a global register instead of a master-specific one. Signed-off-by: Jonas Jelonek --- drivers/i2c/busses/i2c-rtl9300.c | 43 +++++++++++++++++++++++++++++++- 1 file changed, 42 insertions(+), 1 deletion(-) diff --git a/drivers/i2c/busses/i2c-rtl9300.c b/drivers/i2c/busses/i2c-rtl9= 300.c index f8e81102ee74..9bd8a62a2ba0 100644 --- a/drivers/i2c/busses/i2c-rtl9300.c +++ b/drivers/i2c/busses/i2c-rtl9300.c @@ -59,6 +59,7 @@ struct rtl9300_i2c_drv_data { }; =20 #define RTL9300_I2C_MUX_NCHAN 8 +#define RTL9310_I2C_MUX_NCHAN 12 =20 struct rtl9300_i2c { struct regmap *regmap; @@ -67,6 +68,7 @@ struct rtl9300_i2c { struct regmap_field *fields[F_NUM_FIELDS]; u32 reg_base; u32 data_reg; + u8 scl_num; u8 sda_pin; struct mutex lock; }; @@ -79,6 +81,11 @@ struct rtl9300_i2c { #define RTL9300_I2C_MST_DATA_WORD3 0x14 #define RTL9300_I2C_MST_GLB_CTRL 0x384 =20 +#define RTL9310_I2C_MST_IF_CTRL 0x1004 +#define RTL9310_I2C_MST_IF_SEL 0x1008 +#define RTL9310_I2C_MST_CTRL 0x0 +#define RTL9310_I2C_MST_MEMADDR_CTRL 0x4 +#define RTL9310_I2C_MST_DATA_CTRL 0x8 =20 static int rtl9300_i2c_reg_addr_set(struct rtl9300_i2c *i2c, u32 reg, u16 = len) { @@ -96,6 +103,11 @@ static int rtl9300_i2c_select_scl(struct rtl9300_i2c *i= 2c, u8 scl) return regmap_field_write(i2c->fields[F_SCL_SEL], 1); } =20 +static int rtl9310_i2c_select_scl(struct rtl9300_i2c *i2c, u8 scl) +{ + return regmap_field_update_bits(i2c->fields[F_SCL_SEL], BIT(scl), BIT(scl= )); +} + static int rtl9300_i2c_config_io(struct rtl9300_i2c *i2c, u8 sda_pin) { struct rtl9300_i2c_drv_data *drv_data; @@ -111,7 +123,7 @@ static int rtl9300_i2c_config_io(struct rtl9300_i2c *i2= c, u8 sda_pin) if (ret) return ret; =20 - return drv_data->select_scl(i2c, 0); + return drv_data->select_scl(i2c, i2c->scl_num); } =20 static int rtl9300_i2c_config_xfer(struct rtl9300_i2c *i2c, struct rtl9300= _i2c_chan *chan, @@ -346,6 +358,7 @@ static int rtl9300_i2c_probe(struct platform_device *pd= ev) struct device *dev =3D &pdev->dev; struct rtl9300_i2c *i2c; u32 clock_freq, sda_pin; + u8 mst_id; int ret, i =3D 0; struct fwnode_handle *child; struct rtl9300_i2c_drv_data *drv_data; @@ -366,6 +379,11 @@ static int rtl9300_i2c_probe(struct platform_device *p= dev) if (ret) return ret; =20 + ret =3D device_property_read_u8(dev, "realtek,mst-id", &mst_id); + if (ret || mst_id !=3D 2) + mst_id =3D 1; + i2c->scl_num =3D mst_id - 1; + platform_set_drvdata(pdev, i2c); =20 drv_data =3D (struct rtl9300_i2c_drv_data *)device_get_match_data(i2c->de= v); @@ -457,12 +475,35 @@ static const struct rtl9300_i2c_drv_data rtl9300_i2c_= drv_data =3D { .max_nchan =3D RTL9300_I2C_MUX_NCHAN, }; =20 +static const struct rtl9300_i2c_drv_data rtl9310_i2c_drv_data =3D { + .field_desc =3D { + [F_SCL_SEL] =3D GLB_REG_FIELD(RTL9310_I2C_MST_IF_SEL, 12, 13), + [F_SDA_SEL] =3D GLB_REG_FIELD(RTL9310_I2C_MST_IF_SEL, 0, 11), + [F_SCL_FREQ] =3D MST_REG_FIELD(RTL9310_I2C_MST_CTRL, 30, 31), + [F_DEV_ADDR] =3D MST_REG_FIELD(RTL9310_I2C_MST_CTRL, 11, 17), + [F_SDA_OUT_SEL] =3D MST_REG_FIELD(RTL9310_I2C_MST_CTRL, 18, 21), + [F_MEM_ADDR_WIDTH] =3D MST_REG_FIELD(RTL9310_I2C_MST_CTRL, 9, 10), + [F_DATA_WIDTH] =3D MST_REG_FIELD(RTL9310_I2C_MST_CTRL, 5, 8), + [F_RD_MODE] =3D MST_REG_FIELD(RTL9310_I2C_MST_CTRL, 4, 4), + [F_RWOP] =3D MST_REG_FIELD(RTL9310_I2C_MST_CTRL, 2, 2), + [F_I2C_FAIL] =3D MST_REG_FIELD(RTL9310_I2C_MST_CTRL, 1, 1), + [F_I2C_TRIG] =3D MST_REG_FIELD(RTL9310_I2C_MST_CTRL, 0, 0), + [F_MEM_ADDR] =3D MST_REG_FIELD(RTL9310_I2C_MST_MEMADDR_CTRL, 0, 23), + }, + .select_scl =3D rtl9310_i2c_select_scl, + .data_reg =3D RTL9310_I2C_MST_DATA_CTRL, + .max_nchan =3D RTL9310_I2C_MUX_NCHAN, +}; =20 static const struct of_device_id i2c_rtl9300_dt_ids[] =3D { { .compatible =3D "realtek,rtl9301-i2c", .data =3D (void *) &rtl9300_i2c_= drv_data }, { .compatible =3D "realtek,rtl9302b-i2c", .data =3D (void *) &rtl9300_i2c= _drv_data }, { .compatible =3D "realtek,rtl9302c-i2c", .data =3D (void *) &rtl9300_i2c= _drv_data }, { .compatible =3D "realtek,rtl9303-i2c", .data =3D (void *) &rtl9300_i2c_= drv_data }, + { .compatible =3D "realtek,rtl9310-i2c", .data =3D (void *) &rtl9310_i2c_= drv_data }, + { .compatible =3D "realtek,rtl9311-i2c", .data =3D (void *) &rtl9310_i2c_= drv_data }, + { .compatible =3D "realtek,rtl9312-i2c", .data =3D (void *) &rtl9310_i2c_= drv_data }, + { .compatible =3D "realtek,rtl9313-i2c", .data =3D (void *) &rtl9310_i2c_= drv_data }, {} }; MODULE_DEVICE_TABLE(of, i2c_rtl9300_dt_ids); --=20 2.48.1