From nobody Mon Oct 6 03:13:30 2025 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 495E2BA3F; Sun, 27 Jul 2025 07:17:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.61.82.184 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753600625; cv=none; b=FvN6MSuurkP2fyj0dDL4tAh5DjLTBvbPLO9asZ3TtjKacg24dXtpTrLQfnkw+n4M/+/zzW8zKX00++WTqsyDTyEgaqHvYG/hUo1juHFzRkmho9NXrfBd14DjNcK1ywWVD4Y5fNLqbCQ4q/QriokqmKWjnKAE4uy8EZojDq1qvnk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753600625; c=relaxed/simple; bh=Ap7KlXUexDaxC0bm/3hly9hFKEgs/sppHz+f1lLQ97I=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=AvcpjLoYBD6mYpSh7mr/fMoUBHXWnaJ9UjMUldTa+CikxcGdVr/gF0+X807q7Z7tOuu6bifjDtM6YOSU2DN8imBe+8PNDv3kZ5QxoND28aRmBnMefgwMk4wAejMiN0/yZjYtu2ihvZd2mwcduQFjq1gV66Voyv4mDWLMsFuuLU0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=JwneVsfU; arc=none smtp.client-ip=210.61.82.184 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="JwneVsfU" X-UUID: ae9172646ab911f0b33aeb1e7f16c2b6-20250727 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=h3xfRIA1MWnnwK9QehcSTbsTqW/dyTAHteqQQVk9tms=; b=JwneVsfUROeRh9jwj+SSh9jROMaFIM9bq2HjHy6R6WVFe7y768TyrCKh2KZXL5FTstDSGPKbHkL8Qt9rAFD4TCdPLep3ijDOTS8k7ikvWTui02WoscXZfEEAsL+dE67ZeWL9odEgDzEjPY8mRkju6ttxVMdDEQzebOUIE0BZzPc=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.3.2,REQID:a686bb6f-3b0c-47b9-bcde-ad8d5bfff25e,IP:0,UR L:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION:r elease,TS:0 X-CID-META: VersionHash:9eb4ff7,CLOUDID:ec5dd208-aadc-4681-92d7-012627504691,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:81|82|102,TC:nil,Content:0|15|50,EDM :-3,IP:nil,URL:0,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0 ,AV:0,LES:1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-CID-RHF: D41D8CD98F00B204E9800998ECF8427E X-UUID: ae9172646ab911f0b33aeb1e7f16c2b6-20250727 Received: from mtkmbs13n2.mediatek.inc [(172.21.101.108)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 2118310573; Sun, 27 Jul 2025 15:16:57 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs13n2.mediatek.inc (172.21.101.108) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.39; Sun, 27 Jul 2025 15:16:55 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1258.39 via Frontend Transport; Sun, 27 Jul 2025 15:16:53 +0800 From: Jay Liu To: Chun-Kuang Hu , Philipp Zabel , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , Jay Liu , AngeloGioacchino Del Regno , Hsin-Yi Wang , CK Hu , Yongqiang Niu CC: , , , , Subject: [PATCH v2 2/7] drm/mediatek: fix CCORR mtk_ctm_s31_32_to_s1_n function issue Date: Sun, 27 Jul 2025 15:15:52 +0800 Message-ID: <20250727071609.26037-3-jay.liu@mediatek.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20250727071609.26037-1-jay.liu@mediatek.com> References: <20250727071609.26037-1-jay.liu@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" if matrixbit is 11, The range of color matrix is from 0 to (BIT(12) - 1). Values from 0 to (BIT(11) - 1) represent positive numbers, values from BIT(11) to (BIT(12) - 1) represent negative numbers. For example, -1 need converted to 8191. so convert S31.32 to HW Q2.11 format by drm_color_ctm_s31_32_to_qm_n, and set int_bits to 2. Fixes: 738ed4156fba ("drm/mediatek: Add matrix_bits private data for ccorr") Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Jay Liu Signed-off-by: 20220315152503 created --- drivers/gpu/drm/mediatek/mtk_disp_ccorr.c | 24 ++--------------------- 1 file changed, 2 insertions(+), 22 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c b/drivers/gpu/drm/me= diatek/mtk_disp_ccorr.c index 85ba109d6383..b097c20877f3 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c @@ -80,27 +80,6 @@ void mtk_ccorr_stop(struct device *dev) writel_relaxed(0x0, ccorr->regs + DISP_CCORR_EN); } =20 -/* Converts a DRM S31.32 value to the HW S1.n format. */ -static u16 mtk_ctm_s31_32_to_s1_n(u64 in, u32 n) -{ - u16 r; - - /* Sign bit. */ - r =3D in & BIT_ULL(63) ? BIT(n + 1) : 0; - - if ((in & GENMASK_ULL(62, 33)) > 0) { - /* identity value 0x100000000 -> 0x400(mt8183), */ - /* identity value 0x100000000 -> 0x800(mt8192), */ - /* if bigger this, set it to max 0x7ff. */ - r |=3D GENMASK(n, 0); - } else { - /* take the n+1 most important bits. */ - r |=3D (in >> (32 - n)) & GENMASK(n, 0); - } - - return r; -} - bool mtk_ccorr_ctm_set(struct device *dev, struct drm_crtc_state *state) { struct mtk_disp_ccorr *ccorr =3D dev_get_drvdata(dev); @@ -109,6 +88,7 @@ bool mtk_ccorr_ctm_set(struct device *dev, struct drm_cr= tc_state *state) const u64 *input; uint16_t coeffs[9] =3D { 0 }; int i; + int int_bits =3D 2; struct cmdq_pkt *cmdq_pkt =3D NULL; u32 matrix_bits =3D ccorr->data->matrix_bits; =20 @@ -119,7 +99,7 @@ bool mtk_ccorr_ctm_set(struct device *dev, struct drm_cr= tc_state *state) input =3D ctm->matrix; =20 for (i =3D 0; i < ARRAY_SIZE(coeffs); i++) - coeffs[i] =3D mtk_ctm_s31_32_to_s1_n(input[i], matrix_bits); + coeffs[i] =3D drm_color_ctm_s31_32_to_qm_n(input[i], int_bits, matrix_bi= ts); =20 mtk_ddp_write(cmdq_pkt, coeffs[0] << 16 | coeffs[1], &ccorr->cmdq_reg, ccorr->regs, DISP_CCORR_COEF_0); --=20 2.46.0