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Fri, 25 Jul 2025 09:57:02 -0700 (PDT) Received: from localhost ([2a02:8308:a00c:e200:8c15:2281:5347:b367]) by smtp.gmail.com with UTF8SMTPSA id ffacd0b85a97d-3b778ec36bcsm380333f8f.37.2025.07.25.09.57.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Jul 2025 09:57:01 -0700 (PDT) From: =?UTF-8?q?Radim=20Kr=C4=8Dm=C3=A1=C5=99?= To: linux-riscv@lists.infradead.org Cc: linux-kernel@vger.kernel.org, Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Deepak Gupta , stable@vger.kernel.org, Alexandre Ghiti Subject: [PATCH v2 2/4] riscv: use lw when reading int cpu in asm_per_cpu Date: Fri, 25 Jul 2025 18:54:10 +0200 Message-ID: <20250725165410.2896641-5-rkrcmar@ventanamicro.com> X-Mailer: git-send-email 2.50.0 In-Reply-To: <20250725165410.2896641-3-rkrcmar@ventanamicro.com> References: <20250725165410.2896641-3-rkrcmar@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable REG_L is wrong, because thread_info.cpu is 32-bit, not xlen-bit wide. The struct currently has a hole after cpu, so little endian accesses seemed fine. Fixes: be97d0db5f44 ("riscv: VMAP_STACK overflow detection thread-safe") Cc: Reviewed-by: Alexandre Ghiti Signed-off-by: Radim Kr=C4=8Dm=C3=A1=C5=99 --- v2: split for stable [Alex] --- arch/riscv/include/asm/asm.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/include/asm/asm.h b/arch/riscv/include/asm/asm.h index a8a2af6dfe9d..2a16e88e13de 100644 --- a/arch/riscv/include/asm/asm.h +++ b/arch/riscv/include/asm/asm.h @@ -91,7 +91,7 @@ #endif =20 .macro asm_per_cpu dst sym tmp - REG_L \tmp, TASK_TI_CPU_NUM(tp) + lw \tmp, TASK_TI_CPU_NUM(tp) slli \tmp, \tmp, PER_CPU_OFFSET_SHIFT la \dst, __per_cpu_offset add \dst, \dst, \tmp --=20 2.50.0