From nobody Mon Oct 6 03:12:34 2025 Received: from relay6-d.mail.gandi.net (relay6-d.mail.gandi.net [217.70.183.198]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2A7EE17A2F6; Fri, 25 Jul 2025 15:26:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.198 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753457192; cv=none; b=Ix24nuQCl8DJh/2spzQpfISAQjA7TcHhb+aRSrwG3d6lj4eGxYauDiv3BzESYQOjgDKz68FbW2oR1bNE/AuO/gTPEq6jcAEPP6kzNpE2oN1zZj5ndWXZpyELNkh1IHHtWd9RW9jFSlz//F9P12OrpAMUUTMNpy5vridHIgz1FSQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753457192; c=relaxed/simple; bh=meYnIjzl7nC328j1X7tKnCKfhvXyG4iKQmvYUD7Wme0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=JceOQZDYxRtarOnTcTPQtNZqraqWBNRh1bz9dNh+5XQHuSW24XyZrUipLlnM9aIIxJ540ZSY9aPcBCEHJa9XU3vcDGDGrgv6VgrJPN+ICUQKYe6oucAv76aCjEDZK39l9cv0ioHsv1igq6oR9vKdeEeH81Gx3vnYY/WgCwkkBWA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=B7RIOhyf; arc=none smtp.client-ip=217.70.183.198 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="B7RIOhyf" Received: by mail.gandi.net (Postfix) with ESMTPA id A0694441FE; Fri, 25 Jul 2025 15:26:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1753457187; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Was7fZ97bXuHBZTu5UyDFMzUodkIqUeVg40SMOF2Ny4=; b=B7RIOhyfKWdG6nGm9LJf/UyPgsBN5xz16on62ycbB0BEzLNz8VqUszbnumGHVrPSZw3V1/ P/BpX9X8WazzWYbwLrYogSJ3/z+aE357CM7hiUftgK7/TUHxhTTdQrus8389NTo4651Q7u 84s0q85qU3pRaVhTuE15WxQUJ+K0pVtVc6eXGh1Hsv8YuKJ1P6VO8v+xe2HHM9XHr01MjG LXqy5MkTTen506ZWXh1HUXR1S1V+Xo14evdIr52NItHo+dcy83Y0Fy7vDibukqS4qlsNoh 8+HtXe1S0UJW+wcAwhwu5gAhj7xIesv5TW7RMiEixCo1AU/Gkx+oEd6VjKsZCQ== From: Herve Codina To: Hoan Tran , Linus Walleij , Bartosz Golaszewski , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm , Saravana Kannan , Serge Semin , Herve Codina Cc: Phil Edworthy , linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Miquel Raynal , Thomas Petazzoni Subject: [PATCH 1/6] dt-bindings: gpio: snps,dw-apb: Add support for Renesas RZ/N1 Date: Fri, 25 Jul 2025 17:26:10 +0200 Message-ID: <20250725152618.32886-2-herve.codina@bootlin.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20250725152618.32886-1-herve.codina@bootlin.com> References: <20250725152618.32886-1-herve.codina@bootlin.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-GND-State: clean X-GND-Score: -100 X-GND-Cause: gggruggvucftvghtrhhoucdtuddrgeeffedrtdefgdekfeekkecutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfitefpfffkpdcuggftfghnshhusghstghrihgsvgenuceurghilhhouhhtmecufedtudenucesvcftvggtihhpihgvnhhtshculddquddttddmnecujfgurhephffvvefufffkofgjfhgggfestdekredtredttdenucfhrhhomhepjfgvrhhvvgcuvehoughinhgruceohhgvrhhvvgdrtghoughinhgrsegsohhothhlihhnrdgtohhmqeenucggtffrrghtthgvrhhnpeehffeigfejueelueeuffelueefgfelhfejhfehieegudekteeiledttdfhffekffenucfkphepledtrdekledrudeifedruddvjeenucevlhhushhtvghrufhiiigvpedtnecurfgrrhgrmhepihhnvghtpeeltddrkeelrdduieefrdduvdejpdhhvghloheplhhotggrlhhhohhsthdrlhhotggrlhguohhmrghinhdpmhgrihhlfhhrohhmpehhvghrvhgvrdgtohguihhnrgessghoohhtlhhinhdrtghomhdpnhgspghrtghpthhtohepudekpdhrtghpthhtohephhhorghnsehoshdrrghmphgvrhgvtghomhhpuhhtihhnghdrtghomhdprhgtphhtthhopehlihhnuhhsrdifrghllhgvihhjsehlihhnrghrohdrohhrghdprhgtphhtthhopegsrhhglhessghguggvvhdrphhlpdhrtghpthhtoheprhhosghhsehkvghrnhgvlhdrohhrghdprhgtphhtthhopehkrhiikhdoughtsehkvghrnhgvlhdrohhrghdprhgtphhtt hhopegtohhnohhrodgutheskhgvrhhnvghlrdhorhhgpdhrtghpthhtohepghgvvghrthdorhgvnhgvshgrshesghhlihguvghrrdgsvgdprhgtphhtthhopehmrghgnhhushdruggrmhhmsehgmhgrihhlrdgtohhm X-GND-Sasl: herve.codina@bootlin.com Content-Type: text/plain; charset="utf-8" The RZ/N1 SoCs uses the Synopsys DesignWare IP to handle GPIO blocks. Add RZ/N1 SoC and family compatible strings. Signed-off-by: Herve Codina --- .../devicetree/bindings/gpio/snps,dw-apb-gpio.yaml | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/gpio/snps,dw-apb-gpio.yaml b= /Documentation/devicetree/bindings/gpio/snps,dw-apb-gpio.yaml index ab2afc0e4153..ceb71b5ac688 100644 --- a/Documentation/devicetree/bindings/gpio/snps,dw-apb-gpio.yaml +++ b/Documentation/devicetree/bindings/gpio/snps,dw-apb-gpio.yaml @@ -20,7 +20,13 @@ properties: pattern: "^gpio@[0-9a-f]+$" =20 compatible: - const: snps,dw-apb-gpio + oneOf: + - const: snps,dw-apb-gpio + - items: + - enum: + - renesas,r9a06g032-gpio + - const: renesas,rzn1-gpio + - const: snps,dw-apb-gpio =20 "#address-cells": const: 1 --=20 2.50.1 From nobody Mon Oct 6 03:12:34 2025 Received: from relay6-d.mail.gandi.net (relay6-d.mail.gandi.net [217.70.183.198]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2D10122D795; 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arc=none smtp.client-ip=217.70.183.198 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="T0uVsPW4" Received: by mail.gandi.net (Postfix) with ESMTPA id 969F8442AD; Fri, 25 Jul 2025 15:26:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1753457188; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=xT+Y9zqqESB7APfaKivY2kPsEidZC+QbvEhv3rMkh3g=; b=T0uVsPW4PX144LvxqrZvvcbE4fZ/GNN+iEALBLP4Z9Px+GIpq0ktvBWzpKOpuzzDxer4Fj By8IK01TPP2bYaA9NJwqAkfnFXwNd1FQ6H5/2C89IMPEw6hT7tVJ3wBahplfMQdo0brkOF DGuVd5/sdHtQe0fOXKraJEP9aXjs4bbmYPKucKjHNViiMV2OvZtVBu4MiM+Oa1KLZTVkdp RoBr4R30Ar+W7moUAzmltP3Z6yw7qeh56l82R84kMTXQmjzBfE1igcm3+pQkDYCSHGja4D n1XqsAOKWR1ETeYa8fCKHDBtE4U7kOF9BR41jV2UEG5DFd30mK1RJiku2grOSw== From: Herve Codina To: Hoan Tran , Linus Walleij , Bartosz Golaszewski , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm , Saravana Kannan , Serge Semin , Herve Codina Cc: Phil Edworthy , linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Miquel Raynal , Thomas Petazzoni Subject: [PATCH 2/6] ARM: dts: r9a06g032: Add GPIO controllers Date: Fri, 25 Jul 2025 17:26:11 +0200 Message-ID: <20250725152618.32886-3-herve.codina@bootlin.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20250725152618.32886-1-herve.codina@bootlin.com> References: <20250725152618.32886-1-herve.codina@bootlin.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-GND-State: clean X-GND-Score: -100 X-GND-Cause: gggruggvucftvghtrhhoucdtuddrgeeffedrtdefgdekfeekkecutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfitefpfffkpdcuggftfghnshhusghstghrihgsvgenuceurghilhhouhhtmecufedtudenucesvcftvggtihhpihgvnhhtshculddquddttddmnecujfgurhephffvvefufffkofgjfhgggfestdekredtredttdenucfhrhhomhepjfgvrhhvvgcuvehoughinhgruceohhgvrhhvvgdrtghoughinhgrsegsohhothhlihhnrdgtohhmqeenucggtffrrghtthgvrhhnpeehffeigfejueelueeuffelueefgfelhfejhfehieegudekteeiledttdfhffekffenucfkphepledtrdekledrudeifedruddvjeenucevlhhushhtvghrufhiiigvpedtnecurfgrrhgrmhepihhnvghtpeeltddrkeelrdduieefrdduvdejpdhhvghloheplhhotggrlhhhohhsthdrlhhotggrlhguohhmrghinhdpmhgrihhlfhhrohhmpehhvghrvhgvrdgtohguihhnrgessghoohhtlhhinhdrtghomhdpnhgspghrtghpthhtohepudekpdhrtghpthhtohephhhorghnsehoshdrrghmphgvrhgvtghomhhpuhhtihhnghdrtghomhdprhgtphhtthhopehlihhnuhhsrdifrghllhgvihhjsehlihhnrghrohdrohhrghdprhgtphhtthhopegsrhhglhessghguggvvhdrphhlpdhrtghpthhtoheprhhosghhsehkvghrnhgvlhdrohhrghdprhgtphhtthhopehkrhiikhdoughtsehkvghrnhgvlhdrohhrghdprhgtphhtt hhopegtohhnohhrodgutheskhgvrhhnvghlrdhorhhgpdhrtghpthhtohepghgvvghrthdorhgvnhgvshgrshesghhlihguvghrrdgsvgdprhgtphhtthhopehmrghgnhhushdruggrmhhmsehgmhgrihhlrdgtohhm X-GND-Sasl: herve.codina@bootlin.com Content-Type: text/plain; charset="utf-8" Add GPIO controllers (Synosys DesignWare IPs) available in the r9a06g032 (RZ/N1D) SoC. Signed-off-by: Herve Codina --- arch/arm/boot/dts/renesas/r9a06g032.dtsi | 127 +++++++++++++++++++++++ 1 file changed, 127 insertions(+) diff --git a/arch/arm/boot/dts/renesas/r9a06g032.dtsi b/arch/arm/boot/dts/r= enesas/r9a06g032.dtsi index 80ad1fdc77a0..7f71c01af409 100644 --- a/arch/arm/boot/dts/renesas/r9a06g032.dtsi +++ b/arch/arm/boot/dts/renesas/r9a06g032.dtsi @@ -499,6 +499,133 @@ gic: interrupt-controller@44101000 { ; }; =20 + /* + * The GPIO mapping to the corresponding pins is not obvious. + * See the hardware documentation for details. + */ + gpio0: gpio@5000b000 { + compatible =3D "renesas,r9a06g032-gpio", "renesas,rzn1-gpio", "snps,dw-= apb-gpio"; + reg =3D <0x5000b000 0x80>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&sysctrl R9A06G032_HCLK_GPIO0>; + clock-names =3D "bus"; + status =3D "disabled"; + + /* GPIO0a[0] connected to pin GPIO0 */ + /* GPIO0a[1..2] connected to pins GPIO3..4 */ + /* GPIO0a[3..4] connected to pins GPIO9..10 */ + /* GPIO0a[5] connected to pin GPIO12 */ + /* GPIO0a[6..7] connected to pins GPIO15..16 */ + /* GPIO0a[8..9] connected to pins GPIO21..22 */ + /* GPIO0a[10] connected to pin GPIO24 */ + /* GPIO0a[11..12] connected to pins GPIO27..28 */ + /* GPIO0a[13..14] connected to pins GPIO33..34 */ + /* GPIO0a[15] connected to pin GPIO36 */ + /* GPIO0a[16..17] connected to pins GPIO39..40 */ + /* GPIO0a[18..19] connected to pins GPIO45..46 */ + /* GPIO0a[20] connected to pin GPIO48 */ + /* GPIO0a[21..22] connected to pins GPIO51..52 */ + /* GPIO0a[23..24] connected to pins GPIO57..58 */ + /* GPIO0a[25..31] connected to pins GPIO62..68 */ + gpio0a: gpio@0 { + compatible =3D "snps,dw-apb-gpio-port"; + bank-name =3D "gpio0a"; + gpio-controller; + #gpio-cells =3D <2>; + snps,nr-gpios =3D <32>; + reg =3D <0>; + }; + + /* GPIO0b[0..1] connected to pins GPIO1..2 */ + /* GPIO0b[2..5] connected to pins GPIO5..8 */ + /* GPIO0b[6] connected to pin GPIO11 */ + /* GPIO0b[7..8] connected to pins GPIO13..14 */ + /* GPIO0b[9..12] connected to pins GPIO17..20 */ + /* GPIO0b[13] connected to pin GPIO23 */ + /* GPIO0b[14..15] connected to pins GPIO25..26 */ + /* GPIO0b[16..19] connected to pins GPIO29..32 */ + /* GPIO0b[20] connected to pin GPIO35 */ + /* GPIO0b[21..22] connected to pins GPIO37..38 */ + /* GPIO0b[23..26] connected to pins GPIO41..44 */ + /* GPIO0b[27] connected to pin GPIO47 */ + /* GPIO0b[28..29] connected to pins GPIO49..50 */ + /* GPIO0b[30..31] connected to pins GPIO53..54 */ + gpio0b: gpio@1 { + compatible =3D "snps,dw-apb-gpio-port"; + bank-name =3D "gpio0b"; + gpio-controller; + #gpio-cells =3D <2>; + snps,nr-gpios =3D <32>; + reg =3D <1>; + }; + }; + + gpio1: gpio@5000c000 { + compatible =3D "renesas,r9a06g032-gpio", "renesas,rzn1-gpio", "snps,dw-= apb-gpio"; + reg =3D <0x5000c000 0x80>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&sysctrl R9A06G032_HCLK_GPIO1>; + clock-names =3D "bus"; + status =3D "disabled"; + + /* GPIO1a[0..4] connected to pins GPIO69..73 */ + /* GPIO1a[5..31] connected to pins GPIO95..121 */ + gpio1a: gpio@0 { + compatible =3D "snps,dw-apb-gpio-port"; + bank-name =3D "gpio1a"; + gpio-controller; + #gpio-cells =3D <2>; + snps,nr-gpios =3D <32>; + reg =3D <0>; + }; + + /* GPIO1b[0..1] connected to pins GPIO55..56 */ + /* GPIO1b[2..4] connected to pins GPIO59..61 */ + /* GPIO1b[5..25] connected to pins GPIO74..94 */ + /* GPIO1b[26..31] connected to pins GPIO150..155 */ + gpio1b: gpio@1 { + compatible =3D "snps,dw-apb-gpio-port"; + bank-name =3D "gpio1b"; + gpio-controller; + #gpio-cells =3D <2>; + snps,nr-gpios =3D <32>; + reg =3D <1>; + }; + }; + + gpio2: gpio@5000d000 { + compatible =3D "renesas,r9a06g032-gpio", "renesas,rzn1-gpio", "snps,dw-= apb-gpio"; + reg =3D <0x5000d000 0x80>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&sysctrl R9A06G032_HCLK_GPIO2>; + clock-names =3D "bus"; + status =3D "disabled"; + + /* GPIO2a[0..27] connected to pins GPIO122..149 */ + /* GPIO2a[28..31] connected to pins GPIO156..159 */ + gpio2a: gpio@0 { + compatible =3D "snps,dw-apb-gpio-port"; + bank-name =3D "gpio2a"; + gpio-controller; + #gpio-cells =3D <2>; + snps,nr-gpios =3D <32>; + reg =3D <0>; + }; + + /* GPIO2b[0..9] connected to pins GPIO160..169 */ + gpio2b: gpio@1 { + compatible =3D "snps,dw-apb-gpio-port"; + bank-name =3D "gpio2b"; + gpio-controller; + #gpio-cells =3D <2>; + snps,nr-gpios =3D <10>; + reg =3D <1>; + }; + }; + can0: can@52104000 { compatible =3D "renesas,r9a06g032-sja1000", "renesas,rzn1-sja1000"; reg =3D <0x52104000 0x800>; --=20 2.50.1 From nobody Mon Oct 6 03:12:34 2025 Received: from relay6-d.mail.gandi.net (relay6-d.mail.gandi.net [217.70.183.198]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4072223ABAB; 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arc=none smtp.client-ip=217.70.183.198 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="V35E1STU" Received: by mail.gandi.net (Postfix) with ESMTPA id 9F445442B6; Fri, 25 Jul 2025 15:26:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1753457189; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=32YGeynYn2xNilHcQnK7qlzkEemEAVUdzQTGyDSqIwo=; b=V35E1STUzR1e+msXHwHxpzqAtIdbhs1xNGvACk3hQaJZO+Em3DJUaqf989eyk8X4H9QSzI 8B9JQhDLo3mISBdE2Dr6jsLyaiBgfuQxtPMtbtuaXVNYnMKvHpoir88CYamOJcwtxcyvVO 70LCi5Pf/rNEYSv0AbDq/+ASEPLVeV0ODsr1Bi8LD0+pfz7ThqXyyWfX7dAhIItmklyTwj vHkA0/+/P0vOuOcr7evhltMBsvOCJSN8JUU+JXqNDz8Fms9nScdaNesCWX8DbA3Hpbi+u0 hdVvDjEllquRYafXRCDkZyp4bnTRo7Tb4rB7625yd39cK6brXnryBEdbolTN+A== From: Herve Codina To: Hoan Tran , Linus Walleij , Bartosz Golaszewski , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm , Saravana Kannan , Serge Semin , Herve Codina Cc: Phil Edworthy , linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Miquel Raynal , Thomas Petazzoni Subject: [PATCH 3/6] dt-bindings: soc: renesas: Add the Renesas RZ/N1 GPIO Interrupt Multiplexer Date: Fri, 25 Jul 2025 17:26:12 +0200 Message-ID: <20250725152618.32886-4-herve.codina@bootlin.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20250725152618.32886-1-herve.codina@bootlin.com> References: <20250725152618.32886-1-herve.codina@bootlin.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-GND-State: clean X-GND-Score: -100 X-GND-Cause: gggruggvucftvghtrhhoucdtuddrgeeffedrtdefgdekfeekkecutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfitefpfffkpdcuggftfghnshhusghstghrihgsvgenuceurghilhhouhhtmecufedtudenucesvcftvggtihhpihgvnhhtshculddquddttddmnecujfgurhephffvvefufffkofgjfhgggfestdekredtredttdenucfhrhhomhepjfgvrhhvvgcuvehoughinhgruceohhgvrhhvvgdrtghoughinhgrsegsohhothhlihhnrdgtohhmqeenucggtffrrghtthgvrhhnpeefhffhfeevudevuddtteefvdevudefteeiteefjeetgfetieeggfekjefggedtudenucffohhmrghinhepuggvvhhitggvthhrvggvrdhorhhgnecukfhppeeltddrkeelrdduieefrdduvdejnecuvehluhhsthgvrhfuihiivgeptdenucfrrghrrghmpehinhgvthepledtrdekledrudeifedruddvjedphhgvlhhopehlohgtrghlhhhoshhtrdhlohgtrghlughomhgrihhnpdhmrghilhhfrhhomhephhgvrhhvvgdrtghoughinhgrsegsohhothhlihhnrdgtohhmpdhnsggprhgtphhtthhopedukedprhgtphhtthhopehhohgrnhesohhsrdgrmhhpvghrvggtohhmphhuthhinhhgrdgtohhmpdhrtghpthhtoheplhhinhhushdrfigrlhhlvghijheslhhinhgrrhhordhorhhgpdhrtghpthhtohepsghrghhlsegsghguvghvrdhplhdprhgtphhtthhopehrohgshheskhgvrhhnvghlrdhorhhgpdhrtghpthhtohepk hhriihkodgutheskhgvrhhnvghlrdhorhhgpdhrtghpthhtoheptghonhhorhdoughtsehkvghrnhgvlhdrohhrghdprhgtphhtthhopehgvggvrhhtodhrvghnvghsrghssehglhhiuggvrhdrsggvpdhrtghpthhtohepmhgrghhnuhhsrdgurghmmhesghhmrghilhdrtghomh X-GND-Sasl: herve.codina@bootlin.com Content-Type: text/plain; charset="utf-8" On the Renesas RZ/N1 SoC, GPIOs can generate interruptions. Those interruption lines are multiplexed by the GPIO Interrupt Multiplexer in order to map 32 * 3 GPIO interrupt lines to 8 GIC interrupt lines. The GPIO interrupt multiplexer IP does nothing but select 8 GPIO IRQ lines out of the 96 available to wire them to the GIC input lines. Signed-off-by: Herve Codina --- .../soc/renesas/renesas,rzn1-gpioirqmux.yaml | 99 +++++++++++++++++++ 1 file changed, 99 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/renesas/renesas,r= zn1-gpioirqmux.yaml diff --git a/Documentation/devicetree/bindings/soc/renesas/renesas,rzn1-gpi= oirqmux.yaml b/Documentation/devicetree/bindings/soc/renesas/renesas,rzn1-g= pioirqmux.yaml new file mode 100644 index 000000000000..d2b380f15be7 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/renesas/renesas,rzn1-gpioirqmux= .yaml @@ -0,0 +1,99 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/renesas/renesas,rzn1-gpioirqmux.yam= l# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas RZ/N1 SoCs GPIO Interrupt Multiplexer + +description: | + The Renesas RZ/N1 GPIO Interrupt Multiplexer multiplexes GPIO interrupt + lines to the interrupt controller available in the SoC. + + It selects up to 8 of the 96 GPIO interrupt lines available and connect= them + to 8 output interrupt lines. + +maintainers: + - Herve Codina + +properties: + compatible: + items: + - enum: + - renesas,r9a06g032-gpioirqmux + - const: renesas,rzn1-gpioirqmux + + reg: + maxItems: 1 + + interrupts: + minItems: 8 + maxItems: 8 + description: + Output interrupt lines + + "#address-cells": + const: 0 + + "#interrupt-cells": + const: 1 + + interrupt-map-mask: + items: + - const: 0x7f + + interrupt-map: + description: + Specifies the mapping from external GPIO interrupt lines to the outp= ut + interrupts. + +required: + - compatible + - reg + - interrupts + - "#address-cells" + - "#interrupt-cells" + - interrupt-map-mask + - interrupt-map + +additionalProperties: false + +examples: + - | + #include + + gic: interrupt-controller { + interrupt-controller; + #interrupt-cells =3D <3>; + }; + + interrupt-controller@51000480 { + compatible =3D "renesas,r9a06g032-gpioirqmux", "renesas,rzn1-gpioi= rqmux"; + reg =3D <0x51000480 0x20>; + interrupts =3D , + , + , + , + , + , + , + ; + #address-cells =3D <0>; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0x7f>; + /* + * The child interrupt number is computed using the following form= ula: + * gpio_bank * 32 + gpio_number + * + * with: + * - gpio_bank: The GPIO bank number + * - 0 for GPIO0A, + * - 1 for GPIO1A, + * - 2 for GPIO2A + * - gpio_number: Number of the gpio in the bank (0..31) + */ + interrupt-map =3D + <32 &gic GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, /* GPIO1A.0 */ + <89 &gic GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, /* GPIO2A.25 */ + <9 &gic GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; /* GPIO0A.9 */ + }; --=20 2.50.1 From nobody Mon Oct 6 03:12:34 2025 Received: from relay6-d.mail.gandi.net (relay6-d.mail.gandi.net [217.70.183.198]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 493742EE61D; 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arc=none smtp.client-ip=217.70.183.198 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="j8SFW7JL" Received: by mail.gandi.net (Postfix) with ESMTPA id A8144442A6; Fri, 25 Jul 2025 15:26:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1753457190; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=KI8gIiTqmJ5104K5wsgg/sQVoQYLaSObfOOkROi20qc=; b=j8SFW7JLWxhRSRdoY4kSXY76G82N4PGWJUTxCohI0PyYISQIljHc4t1WPPi+hNUR6BIRO/ RZDN6SATlGb7BuIE1957Wn1HBcAnd0ypQn7VYwREbitpQ+ILsxez50LVy9ut16Jb6Vd1Lb 64PgHcPNeyVa/348znRqSOO8ncU5ru+HRhROtbVCNjYMjncJkuNfXXcCD9u6FZNkKWU5MT WyiP5mhNT4u+74wcBBJkmBVmaaAszHBBv7r26ikWABJgCnzG6aFFnhPBgiVnFKgpE+OzzE mcYCamqhG79MkHl7zpY5YnhPi9KK1JsddnddsG8fjhd3OULLrXLoKA8TV/wTIA== From: Herve Codina To: Hoan Tran , Linus Walleij , Bartosz Golaszewski , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm , Saravana Kannan , Serge Semin , Herve Codina Cc: Phil Edworthy , linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Miquel Raynal , Thomas Petazzoni Subject: [PATCH 4/6] of/irq: Introduce of_irq_foreach_imap Date: Fri, 25 Jul 2025 17:26:13 +0200 Message-ID: <20250725152618.32886-5-herve.codina@bootlin.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20250725152618.32886-1-herve.codina@bootlin.com> References: <20250725152618.32886-1-herve.codina@bootlin.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-GND-State: clean X-GND-Score: -100 X-GND-Cause: gggruggvucftvghtrhhoucdtuddrgeeffedrtdefgdekfeekkecutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfitefpfffkpdcuggftfghnshhusghstghrihgsvgenuceurghilhhouhhtmecufedtudenucesvcftvggtihhpihgvnhhtshculddquddttddmnecujfgurhephffvvefufffkofgjfhgggfestdekredtredttdenucfhrhhomhepjfgvrhhvvgcuvehoughinhgruceohhgvrhhvvgdrtghoughinhgrsegsohhothhlihhnrdgtohhmqeenucggtffrrghtthgvrhhnpeehffeigfejueelueeuffelueefgfelhfejhfehieegudekteeiledttdfhffekffenucfkphepledtrdekledrudeifedruddvjeenucevlhhushhtvghrufhiiigvpedvnecurfgrrhgrmhepihhnvghtpeeltddrkeelrdduieefrdduvdejpdhhvghloheplhhotggrlhhhohhsthdrlhhotggrlhguohhmrghinhdpmhgrihhlfhhrohhmpehhvghrvhgvrdgtohguihhnrgessghoohhtlhhinhdrtghomhdpnhgspghrtghpthhtohepudekpdhrtghpthhtohephhhorghnsehoshdrrghmphgvrhgvtghomhhpuhhtihhnghdrtghomhdprhgtphhtthhopehlihhnuhhsrdifrghllhgvihhjsehlihhnrghrohdrohhrghdprhgtphhtthhopegsrhhglhessghguggvvhdrphhlpdhrtghpthhtoheprhhosghhsehkvghrnhgvlhdrohhrghdprhgtphhtthhopehkrhiikhdoughtsehkvghrnhgvlhdrohhrghdprhgtphhtt hhopegtohhnohhrodgutheskhgvrhhnvghlrdhorhhgpdhrtghpthhtohepghgvvghrthdorhgvnhgvshgrshesghhlihguvghrrdgsvgdprhgtphhtthhopehmrghgnhhushdruggrmhhmsehgmhgrihhlrdgtohhm X-GND-Sasl: herve.codina@bootlin.com Content-Type: text/plain; charset="utf-8" of_irq_foreach_imap is an iterator designed to help a driver to parse an interrupt-map property. Indeed some drivers need to know details about the interrupt mapping described in the device-tree in order to set internal registers accordingly. Signed-off-by: Herve Codina --- drivers/of/irq.c | 70 ++++++++++++++++++++++++++++++++++++++++++ include/linux/of_irq.h | 11 +++++++ 2 files changed, 81 insertions(+) diff --git a/drivers/of/irq.c b/drivers/of/irq.c index f8ad79b9b1c9..863b31eb3c1a 100644 --- a/drivers/of/irq.c +++ b/drivers/of/irq.c @@ -157,6 +157,76 @@ const __be32 *of_irq_parse_imap_parent(const __be32 *i= map, int len, struct of_ph return imap; } =20 +/** + * of_irq_foreach_imap - Iterate through interrupt-map items + * @np: device node where interrupt-map is available + * @func: function called on each interrupt-map items + * @data: data passe to @func + * + * This function iterates through interrupt-map items and calls @func on e= ach + * item. The parent interrupt described in the interrupt-map item is parsed + * and passed to @func using a pointer to a struct of_phandle_args. + * Also the imap raw value is passed in order to allow @func to look at ot= her + * values of the interrupt-map (child unit address and child interrupt + * specificer) + * + * If @func returns an error, the iteration stops and this error is return= ed. + */ +int of_irq_foreach_imap(struct device_node *np, + int (*func)(void *data, + const __be32 *imap, + const struct of_phandle_args *parent_args), + void *data) +{ + const __be32 *imap, *imap_end, *imap_parent, *imap_next; + struct of_phandle_args parent_args; + u32 tmp, parent_offset; + int imaplen; + int ret; + + /* + * parent_offset is the offset where the parent part is starting. + * In other words, the offset where the parent interrupt controller + * phandle is present. + * + * Compute this offset (child #interrupt-cells + child #address-cells) + */ + parent_offset =3D of_bus_n_addr_cells(np); + + ret =3D of_property_read_u32(np, "#interrupt-cells", &tmp); + if (ret) + return ret; + + parent_offset +=3D tmp; + + imap =3D of_get_property(np, "interrupt-map", &imaplen); + if (!imap) + return -ENOENT; + + imaplen /=3D sizeof(*imap); + imap_end =3D imap + imaplen; + + while (imap + parent_offset + 1 < imap_end) { + imap_parent =3D imap + parent_offset; + + imap_next =3D of_irq_parse_imap_parent(imap_parent, + imap_end - imap_parent, + &parent_args); + if (!imap_next) + return -EINVAL; + + ret =3D func(data, imap, &parent_args); + of_node_put(parent_args.np); + if (ret) + return ret; + + imap =3D imap_next; + } + + return 0; +} +EXPORT_SYMBOL_GPL(of_irq_foreach_imap); + /** * of_irq_parse_raw - Low level interrupt tree parsing * @addr: address specifier (start of "reg" property of the device) in be3= 2 format diff --git a/include/linux/of_irq.h b/include/linux/of_irq.h index 6337ad4e5fe8..b89920c6ab55 100644 --- a/include/linux/of_irq.h +++ b/include/linux/of_irq.h @@ -47,6 +47,10 @@ extern int of_irq_get_byname(struct device_node *dev, co= nst char *name); extern int of_irq_to_resource_table(struct device_node *dev, struct resource *res, int nr_irqs); extern struct device_node *of_irq_find_parent(struct device_node *child); +extern int of_irq_foreach_imap(struct device_node *np, + int (*func)(void *data, const __be32 *imap, + const struct of_phandle_args *parent_args), + void *data); extern struct irq_domain *of_msi_get_domain(struct device *dev, const struct device_node *np, enum irq_domain_bus_token token); @@ -85,6 +89,13 @@ static inline void *of_irq_find_parent(struct device_nod= e *child) { return NULL; } +static inline int of_irq_foreach_imap(struct device_node *np, + int (*func)(void *data, const __be32 *imap, + const struct of_phandle_args *parent_args), + void *data) +{ + return -EINVAL; +} =20 static inline struct irq_domain *of_msi_get_domain(struct device *dev, struct device_node *np, --=20 2.50.1 From nobody Mon Oct 6 03:12:34 2025 Received: from relay6-d.mail.gandi.net (relay6-d.mail.gandi.net [217.70.183.198]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 521302EE97E; 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arc=none smtp.client-ip=217.70.183.198 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="cVmWSZuV" Received: by mail.gandi.net (Postfix) with ESMTPA id AC24B442B7; Fri, 25 Jul 2025 15:26:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1753457191; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=+2bVnURAI35njT7CHzoVAKYMvlvIjGI7coGMmmFm+tk=; b=cVmWSZuVUD4d/BzyZ2P3M3yN57ldaaR296hxd9KdXEzno4up4DcxsTf3A/AtiMNowyL3M2 Hd0TMhxKNfi5WShO8d12RijLrFow8LbayKFJ902n/dPF/KjmsdvGSs1h7DlcYquf6rOOCr wvJZdrToVGj7WW+BXcxj1wW0sgeKr8th+6vVNNuQbxQp2LBpmj+G0fjrPLLKmRjVNQzGD/ bArBSEw83AWbhAH6XqNtTFSHwCqQ5+r4PttVt3iyl6YnqnxToBhmsb5s7Ori0bEpxQKjxu GPrwNZfOE9Dfnx48lX6W34wWT4UifAM7A6GzRJIC4CuvfdMmXgkLGIWkzMAbWw== From: Herve Codina To: Hoan Tran , Linus Walleij , Bartosz Golaszewski , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm , Saravana Kannan , Serge Semin , Herve Codina Cc: Phil Edworthy , linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Miquel Raynal , Thomas Petazzoni Subject: [PATCH 5/6] soc: renesas: Add support for Renesas RZ/N1 GPIO Interrupt Multiplexer Date: Fri, 25 Jul 2025 17:26:14 +0200 Message-ID: <20250725152618.32886-6-herve.codina@bootlin.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20250725152618.32886-1-herve.codina@bootlin.com> References: <20250725152618.32886-1-herve.codina@bootlin.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-GND-State: clean X-GND-Score: -100 X-GND-Cause: gggruggvucftvghtrhhoucdtuddrgeeffedrtdefgdekfeekkecutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfitefpfffkpdcuggftfghnshhusghstghrihgsvgenuceurghilhhouhhtmecufedtudenucesvcftvggtihhpihgvnhhtshculddquddttddmnecujfgurhephffvvefufffkofgjfhgggfestdekredtredttdenucfhrhhomhepjfgvrhhvvgcuvehoughinhgruceohhgvrhhvvgdrtghoughinhgrsegsohhothhlihhnrdgtohhmqeenucggtffrrghtthgvrhhnpeehffeigfejueelueeuffelueefgfelhfejhfehieegudekteeiledttdfhffekffenucfkphepledtrdekledrudeifedruddvjeenucevlhhushhtvghrufhiiigvpedvnecurfgrrhgrmhepihhnvghtpeeltddrkeelrdduieefrdduvdejpdhhvghloheplhhotggrlhhhohhsthdrlhhotggrlhguohhmrghinhdpmhgrihhlfhhrohhmpehhvghrvhgvrdgtohguihhnrgessghoohhtlhhinhdrtghomhdpnhgspghrtghpthhtohepudekpdhrtghpthhtohephhhorghnsehoshdrrghmphgvrhgvtghomhhpuhhtihhnghdrtghomhdprhgtphhtthhopehlihhnuhhsrdifrghllhgvihhjsehlihhnrghrohdrohhrghdprhgtphhtthhopegsrhhglhessghguggvvhdrphhlpdhrtghpthhtoheprhhosghhsehkvghrnhgvlhdrohhrghdprhgtphhtthhopehkrhiikhdoughtsehkvghrnhgvlhdrohhrghdprhgtphhtt hhopegtohhnohhrodgutheskhgvrhhnvghlrdhorhhgpdhrtghpthhtohepghgvvghrthdorhgvnhgvshgrshesghhlihguvghrrdgsvgdprhgtphhtthhopehmrghgnhhushdruggrmhhmsehgmhgrihhlrdgtohhm X-GND-Sasl: herve.codina@bootlin.com Content-Type: text/plain; charset="utf-8" On the Renesas RZ/N1 SoC, GPIOs can generate interruptions. Those interruption lines are multiplexed by the GPIO Interrupt Multiplexer in order to map 32 * 3 GPIO interrupt lines to 8 GIC interrupt lines. The GPIO interrupt multiplexer IP does nothing but select 8 GPIO IRQ lines out of the 96 available to wire them to the GIC input lines. Signed-off-by: Herve Codina --- drivers/soc/renesas/Kconfig | 4 + drivers/soc/renesas/Makefile | 1 + drivers/soc/renesas/rzn1_irqmux.c | 169 ++++++++++++++++++++++++++++++ 3 files changed, 174 insertions(+) create mode 100644 drivers/soc/renesas/rzn1_irqmux.c diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig index fbc3b69d21a7..9e8ac33052fb 100644 --- a/drivers/soc/renesas/Kconfig +++ b/drivers/soc/renesas/Kconfig @@ -58,6 +58,7 @@ config ARCH_RZN1 select PM select PM_GENERIC_DOMAINS select ARM_AMBA + select RZN1_IRQMUX =20 if ARM && ARCH_RENESAS =20 @@ -435,6 +436,9 @@ config PWC_RZV2M config RST_RCAR bool "Reset Controller support for R-Car" if COMPILE_TEST =20 +config RZN1_IRQMUX + bool "Renesas RZ/N1 GPIO IRQ multiplexer support" if COMPILE_TEST + config SYSC_RZ bool "System controller for RZ SoCs" if COMPILE_TEST =20 diff --git a/drivers/soc/renesas/Makefile b/drivers/soc/renesas/Makefile index 3bdcc6a395d5..daa932c7698d 100644 --- a/drivers/soc/renesas/Makefile +++ b/drivers/soc/renesas/Makefile @@ -14,4 +14,5 @@ obj-$(CONFIG_SYS_R9A09G057) +=3D r9a09g057-sys.o # Family obj-$(CONFIG_PWC_RZV2M) +=3D pwc-rzv2m.o obj-$(CONFIG_RST_RCAR) +=3D rcar-rst.o +obj-$(CONFIG_RZN1_IRQMUX) +=3D rzn1_irqmux.o obj-$(CONFIG_SYSC_RZ) +=3D rz-sysc.o diff --git a/drivers/soc/renesas/rzn1_irqmux.c b/drivers/soc/renesas/rzn1_i= rqmux.c new file mode 100644 index 000000000000..37e41c2b9104 --- /dev/null +++ b/drivers/soc/renesas/rzn1_irqmux.c @@ -0,0 +1,169 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * RZ/N1 GPIO Interrupt Multiplexer + * + * Copyright 2025 Schneider Electric + * Author: Herve Codina + */ + +#include +#include +#include +#include +#include + +#define IRQMUX_MAX_IRQS 8 + +static int irqmux_is_phandle_args_equal(const struct of_phandle_args *a, + const struct of_phandle_args *b) +{ + int i; + + if (a->np !=3D b->np) + return false; + + if (a->args_count !=3D b->args_count) + return false; + + for (i =3D 0; i < a->args_count; i++) { + if (a->args[i] !=3D b->args[i]) + return false; + } + + return true; +} + +static int irqmux_find_interrupt_index(struct device *dev, struct device_n= ode *np, + const struct of_phandle_args *expected_irq) +{ + struct of_phandle_args out_irq; + bool is_equal; + int ret; + int i; + + for (i =3D 0; i < IRQMUX_MAX_IRQS; i++) { + ret =3D of_irq_parse_one(np, i, &out_irq); + if (ret) + return ret; + + is_equal =3D irqmux_is_phandle_args_equal(expected_irq, &out_irq); + of_node_put(out_irq.np); + if (is_equal) + return i; + } + + return -ENOENT; +} + +struct irqmux_cb_data { + struct device_node *np; + struct device *dev; + u32 __iomem *regs; +}; + +static int irqmux_imap_cb(void *data, const __be32 *imap, + const struct of_phandle_args *parent_args) +{ + struct irqmux_cb_data *priv =3D data; + u32 src_hwirq; + int index; + + /* + * The child #address-cells is 0. Already checked in irqmux_setup(). + * The first value in imap is the src_hwirq + */ + src_hwirq =3D be32_to_cpu(*imap); + + /* + * Get the index in our interrupt array that matches the parent in the + * interrupt-map + */ + index =3D irqmux_find_interrupt_index(priv->dev, priv->np, parent_args); + if (index < 0) + return dev_err_probe(priv->dev, index, "output interrupt not found\n"); + + dev_info(priv->dev, "interrupt %u mapped to output interrupt[%u]\n", + src_hwirq, index); + + /* + * Our interrupt array items matches 1:1 the interrupt lines that could + * be configured by registers (same order, same number). + * Configure the related register with the src hwirq retrieved from the + * interrupt-map. + */ + writel(src_hwirq, priv->regs + index); + + return 0; +} + +static int irqmux_setup(struct device *dev, struct device_node *np, u32 __= iomem *regs) +{ + struct irqmux_cb_data cb_data; + u32 tmp; + int ret; + + /* We support only #interrupt-cells =3D <1> and #address-cells =3D <0> */ + ret =3D of_property_read_u32(np, "#interrupt-cells", &tmp); + if (ret) + return ret; + if (tmp !=3D 1) + return -EINVAL; + + ret =3D of_property_read_u32(np, "#address-cells", &tmp); + if (ret) + return ret; + if (tmp !=3D 0) + return -EINVAL; + + cb_data.dev =3D dev; + cb_data.regs =3D regs; + cb_data.np =3D np; + return of_irq_foreach_imap(np, irqmux_imap_cb, &cb_data); +} + +static int irqmux_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct device_node *np =3D dev->of_node; + u32 __iomem *regs; + int nr_irqs; + int ret; + + regs =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(regs)) + return PTR_ERR(regs); + + nr_irqs =3D of_irq_count(np); + if (nr_irqs < 0) + return nr_irqs; + + if (nr_irqs > IRQMUX_MAX_IRQS) { + dev_err(dev, "too many output interrupts\n"); + return -ENOENT; + } + + ret =3D irqmux_setup(dev, np, regs); + if (ret) + return dev_err_probe(dev, ret, "failed to setup mux\n"); + + return 0; +} + +static const struct of_device_id irqmux_of_match[] =3D { + { .compatible =3D "renesas,rzn1-gpioirqmux", }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, irq_mux_of_match); + +static struct platform_driver irqmux_driver =3D { + .probe =3D irqmux_probe, + .driver =3D { + .name =3D "rzn1_irqmux", + .of_match_table =3D irqmux_of_match, + }, +}; +module_platform_driver(irqmux_driver); + +MODULE_AUTHOR("Herve Codina "); +MODULE_DESCRIPTION("Renesas RZ/N1 GPIO IRQ Multiplexer Driver"); +MODULE_LICENSE("GPL"); --=20 2.50.1 From nobody Mon Oct 6 03:12:34 2025 Received: from relay6-d.mail.gandi.net (relay6-d.mail.gandi.net [217.70.183.198]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3AE7A2EE615; Fri, 25 Jul 2025 15:26:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.198 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753457196; cv=none; b=TGpBtsQmSQ584ZhGvwLFhOiqY7Y2UIHLNzKa3ueDa9VNbx2MC+1zv65lFAoJ+4KeJdCq9tMxvGyK+8wB2FBD8J2M9hKYDwqExHGK91WaxaeAQj3xP1PV44nTt4xVsrau8DRQQo89vM9FXGKGmAPeIifVwwxtwSTwO1LzoghcJyE= ARC-Message-Signature: i=1; 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charset="utf-8" In the RZ/N1 SoC, the GPIO interrupts are multiplexed using the GPIO Interrupt Multiplexer. Add the multiplexer node and connect GPIO interrupt lines to the multiplexer. The interrupt-map available in the multiplexer node has to be updated in dts files depending on the GPIO usage. Indeed, the usage of an interrupt for a GPIO is board dependent. Up to 8 GPIOs can be used as an interrupt line (one per multiplexer output interrupt). Signed-off-by: Herve Codina --- arch/arm/boot/dts/renesas/r9a06g032.dtsi | 45 ++++++++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/arch/arm/boot/dts/renesas/r9a06g032.dtsi b/arch/arm/boot/dts/r= enesas/r9a06g032.dtsi index 7f71c01af409..0e2e0fe92cd3 100644 --- a/arch/arm/boot/dts/renesas/r9a06g032.dtsi +++ b/arch/arm/boot/dts/renesas/r9a06g032.dtsi @@ -535,6 +535,14 @@ gpio0a: gpio@0 { #gpio-cells =3D <2>; snps,nr-gpios =3D <32>; reg =3D <0>; + + interrupt-controller; + interrupt-parent =3D <&gpioirqmux>; + interrupts =3D < 0 1 2 3 4 5 6 7 + 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 + 24 25 26 27 28 29 30 31 >; + #interrupt-cells =3D <2>; }; =20 /* GPIO0b[0..1] connected to pins GPIO1..2 */ @@ -579,6 +587,14 @@ gpio1a: gpio@0 { #gpio-cells =3D <2>; snps,nr-gpios =3D <32>; reg =3D <0>; + + interrupt-controller; + interrupt-parent =3D <&gpioirqmux>; + interrupts =3D < 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 >; + #interrupt-cells =3D <2>; }; =20 /* GPIO1b[0..1] connected to pins GPIO55..56 */ @@ -613,6 +629,14 @@ gpio2a: gpio@0 { #gpio-cells =3D <2>; snps,nr-gpios =3D <32>; reg =3D <0>; + + interrupt-controller; + interrupt-parent =3D <&gpioirqmux>; + interrupts =3D < 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 >; + #interrupt-cells =3D <2>; }; =20 /* GPIO2b[0..9] connected to pins GPIO160..169 */ @@ -626,6 +650,27 @@ gpio2b: gpio@1 { }; }; =20 + gpioirqmux: interrupt-controller@51000480 { + compatible =3D "renesas,r9a06g032-gpioirqmux", "renesas,rzn1-gpioirqmux= "; + reg =3D <0x51000480 0x20>; + interrupts =3D , + , + , + , + , + , + , + ; + #interrupt-cells =3D <1>; + #address-cells =3D <0>; + interrupt-map-mask =3D <0x7f>; + + /* interrupt-map has to be updated according to GPIO usage */ + interrupt-map =3D <0 &gic GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; + + status =3D "disabled"; + }; + can0: can@52104000 { compatible =3D "renesas,r9a06g032-sja1000", "renesas,rzn1-sja1000"; reg =3D <0x52104000 0x800>; --=20 2.50.1