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Fri, 25 Jul 2025 10:22:34 GMT Received: from cse-cd01-lnx.ap.qualcomm.com (cse-cd01-lnx.qualcomm.com [10.64.75.209]) by APTAIPPMTA01.qualcomm.com (PPS) with ESMTPS id 56PAMXvV027645 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 25 Jul 2025 10:22:34 +0000 Received: by cse-cd01-lnx.ap.qualcomm.com (Postfix, from userid 4438065) id E2458211E6; Fri, 25 Jul 2025 18:22:32 +0800 (CST) From: Ziyue Zhang To: andersson@kernel.org, konradybcio@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, jingoohan1@gmail.com, mani@kernel.org, lpieralisi@kernel.org, kwilczynski@kernel.org, bhelgaas@google.com, johan+linaro@kernel.org, vkoul@kernel.org, kishon@kernel.org, neil.armstrong@linaro.org, abel.vesa@linaro.org, kw@linux.com Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, linux-phy@lists.infradead.org, qiang.yu@oss.qualcomm.com, quic_krichai@quicinc.com, quic_vbadigan@quicinc.com, Ziyue Zhang Subject: [PATCH v7 2/3] arm64: dts: qcom: sa8775p: remove aux clock from pcie phy Date: Fri, 25 Jul 2025 18:22:30 +0800 Message-Id: <20250725102231.3608298-3-ziyue.zhang@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250725102231.3608298-1-ziyue.zhang@oss.qualcomm.com> References: <20250725102231.3608298-1-ziyue.zhang@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: skjv_WB98foTsT_rtvwRi_8ej5HyGAw_ X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzI1MDA4OCBTYWx0ZWRfXzX2BxlzP87MZ 9BUgmXaRk4zgTU++lG6wn6BqZ4Ic42fOUyfJrJxGjqngICt4Uh3lcI0tbRei2l3zfGRdWIoZYJX ZpHgsTm6d7Z0/3irzOHaSiDbz7XJ4nbWpdNFx13KVoeqqiRPBIT8AcTbrMEflkttBHZMB7vnN8x Ipua174wLJT0NXtM0NWBB4ehVZT3Nhq9pNm8ZOBPiXSgLok4VvTndAz7vPzCpDEXDE5w2MQtHu2 Nyf5JzeFQxJzTItGKtRI4pVbksYPPu/hTnkhwZyu3ikfWpIxrI7zBFqUY0ILoJb2G4SgnDPzRZP /b8MlA1rvb7r2BLhqshiHpDaNHHn6sxMSVcFOx8ByzaALxBq/FNWtjeaoqmkOuze8QM2PiRzGbs Qa+zG4hJ0jmdQfvqfzbTVTEsBAN6Lnrz8ebXjacOgI59BCMnwa6wk962YQYqMwNjVTXOpJGy X-Proofpoint-GUID: skjv_WB98foTsT_rtvwRi_8ej5HyGAw_ X-Authority-Analysis: v=2.4 cv=S8bZwJsP c=1 sm=1 tr=0 ts=68835c19 cx=c_pps a=nuhDOHQX5FNHPW3J6Bj6AA==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=Wb1JkmetP80A:10 a=EUspDBNiAAAA:8 a=EluF0xcg-2KMSqT-UJQA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-25_03,2025-07-24_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 lowpriorityscore=0 mlxlogscore=999 bulkscore=0 impostorscore=0 spamscore=0 malwarescore=0 adultscore=0 suspectscore=0 phishscore=0 priorityscore=1501 mlxscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507250088 The gcc_aux_clk is used by the PCIe Root Complex (RC) and is not required by the PHY. The correct clock for the PHY is gcc_phy_aux_clk, which this patch uses to replace the incorrect reference. The distinction between AUX_CLK and PHY_AUX_CLK is important: AUX_CLK is typically used by the controller, while PHY_AUX_CLK is required by certain PHYs=E2=80=94particularly Gen4 QMP PHYs=E2=80=94for internal operations suc= h as clock gating and power management. Some non-Gen4 Qualcomm PHYs also use PHY_AUX_CLK, but they do not require AUX_CLK. This change ensures proper clock configuration and avoids unnecessary dependencies. Signed-off-by: Ziyue Zhang Reviewed-by: Johan Hovold Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 28 +++++++++++++++------------ 1 file changed, 16 insertions(+), 12 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qc= om/sa8775p.dtsi index 9997a29901f5..39a4f59d8925 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -7707,16 +7707,18 @@ pcie0_phy: phy@1c04000 { compatible =3D "qcom,sa8775p-qmp-gen4x2-pcie-phy"; reg =3D <0x0 0x1c04000 0x0 0x2000>; =20 - clocks =3D <&gcc GCC_PCIE_0_AUX_CLK>, + clocks =3D <&gcc GCC_PCIE_0_PHY_AUX_CLK>, <&gcc GCC_PCIE_0_CFG_AHB_CLK>, <&gcc GCC_PCIE_CLKREF_EN>, <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>, <&gcc GCC_PCIE_0_PIPE_CLK>, - <&gcc GCC_PCIE_0_PIPEDIV2_CLK>, - <&gcc GCC_PCIE_0_PHY_AUX_CLK>; - - clock-names =3D "aux", "cfg_ahb", "ref", "rchng", "pipe", - "pipediv2", "phy_aux"; + <&gcc GCC_PCIE_0_PIPEDIV2_CLK>; + clock-names =3D "aux", + "cfg_ahb", + "ref", + "rchng", + "pipe", + "pipediv2"; =20 assigned-clocks =3D <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; assigned-clock-rates =3D <100000000>; @@ -7873,16 +7875,18 @@ pcie1_phy: phy@1c14000 { compatible =3D "qcom,sa8775p-qmp-gen4x4-pcie-phy"; reg =3D <0x0 0x1c14000 0x0 0x4000>; =20 - clocks =3D <&gcc GCC_PCIE_1_AUX_CLK>, + clocks =3D <&gcc GCC_PCIE_1_PHY_AUX_CLK>, <&gcc GCC_PCIE_1_CFG_AHB_CLK>, <&gcc GCC_PCIE_CLKREF_EN>, <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>, <&gcc GCC_PCIE_1_PIPE_CLK>, - <&gcc GCC_PCIE_1_PIPEDIV2_CLK>, - <&gcc GCC_PCIE_1_PHY_AUX_CLK>; - - clock-names =3D "aux", "cfg_ahb", "ref", "rchng", "pipe", - "pipediv2", "phy_aux"; + <&gcc GCC_PCIE_1_PIPEDIV2_CLK>; + clock-names =3D "aux", + "cfg_ahb", + "ref", + "rchng", + "pipe", + "pipediv2"; =20 assigned-clocks =3D <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>; assigned-clock-rates =3D <100000000>; --=20 2.34.1