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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-23fa48fd29dsm33641435ad.176.2025.07.25.03.08.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Jul 2025 03:08:39 -0700 (PDT) From: Jie Gan To: Suzuki K Poulose , Mike Leach , James Clark , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Alexander Shishkin , Tingwei Zhang , Jinlong Mao Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, Jie Gan , Krzysztof Kozlowski Subject: [PATCH v4 06/10] dt-bindings: arm: add an interrupt property for Coresight CTCU Date: Fri, 25 Jul 2025 18:08:02 +0800 Message-Id: <20250725100806.1157-7-jie.gan@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250725100806.1157-1-jie.gan@oss.qualcomm.com> References: <20250725100806.1157-1-jie.gan@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Authority-Analysis: v=2.4 cv=BMKzrEQG c=1 sm=1 tr=0 ts=688357aa cx=c_pps a=IZJwPbhc+fLeJZngyXXI0A==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=Wb1JkmetP80A:10 a=KKAkSRfTAAAA:8 a=EUspDBNiAAAA:8 a=gSyxy6DGYGa4b6s9XCEA:9 a=uG9DUKGECoFWVXl0Dc02:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-ORIG-GUID: 8cNySwPYth0gPb1UH3lNpwE5f2UM66al X-Proofpoint-GUID: 8cNySwPYth0gPb1UH3lNpwE5f2UM66al X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzI1MDA4NSBTYWx0ZWRfX4KDy0Bfql3Jk FTl9ZEGLmKPUKsG87v1q4El09zog73pO93Kz0l5d2Kzj8wzTIU7B+Oowrip+QRWrrDPVcUvPWY7 b38+MgyZdlqLWx1vrS4uuJMWM73yzBQl9xaoUF4Y7kHA/Hk2AfPjIuwJtVCnzdLQlYg6SJiMWAC VveWg8iTJVT24WFzyuAPIdFy69t7+HNxXWaxiLs3ugK778hH6Bd6TNAnsdyLbuwQuMkqlXDEIxD fXCvmxXAAlDKqk5vyRshHcUqswQnf7+09j94crb6VyMWdC4XfrpyG3d8sufqumixzn3Fiv7Wkas QQUswLSfcKvvV+wxhr4LtZnklduzC6tCrja3pzhvOFOBuqHIKUiJ6S+DDWr/zNc1AI1e90NQWCU 2vt8fPFNg+dbEIpbYI4GIB4MWWB4J9qp9e59E0p+8OEWV0LkodJSWZ8YopnWQKqYigd7iBYX X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-25_02,2025-07-24_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 mlxscore=0 spamscore=0 impostorscore=0 priorityscore=1501 bulkscore=0 malwarescore=0 adultscore=0 phishscore=0 suspectscore=0 mlxlogscore=999 clxscore=1015 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507250085 Content-Type: text/plain; charset="utf-8" Add an interrupt property to CTCU device. The interrupt will be triggered when the data size in the ETR buffer exceeds the threshold of the BYTECNTRVAL register. Programming a threshold in the BYTECNTRVAL register of CTCU device will enable the interrupt. Acked-by: Krzysztof Kozlowski Signed-off-by: Jie Gan --- .../bindings/arm/qcom,coresight-ctcu.yaml | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml= b/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml index 843b52eaf872..ea05ad8f3dd3 100644 --- a/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml +++ b/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml @@ -39,6 +39,16 @@ properties: items: - const: apb =20 + interrupts: + items: + - description: Byte cntr interrupt for etr0 + - description: Byte cntr interrupt for etr1 + + interrupt-names: + items: + - const: etr0 + - const: etr1 + in-ports: $ref: /schemas/graph.yaml#/properties/ports =20 @@ -56,6 +66,8 @@ additionalProperties: false =20 examples: - | + #include + ctcu@1001000 { compatible =3D "qcom,sa8775p-ctcu"; reg =3D <0x1001000 0x1000>; @@ -63,6 +75,11 @@ examples: clocks =3D <&aoss_qmp>; clock-names =3D "apb"; =20 + interrupts =3D , + ; + interrupt-names =3D "etr0", + "etr1"; + in-ports { #address-cells =3D <1>; #size-cells =3D <0>; --=20 2.34.1