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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-23fa48fd29dsm33641435ad.176.2025.07.25.03.08.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Jul 2025 03:08:16 -0700 (PDT) From: Jie Gan To: Suzuki K Poulose , Mike Leach , James Clark , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Alexander Shishkin , Tingwei Zhang , Jinlong Mao Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, Jie Gan Subject: [PATCH v4 01/10] coresight: core: Refactoring ctcu_get_active_port and make it generic Date: Fri, 25 Jul 2025 18:07:57 +0800 Message-Id: <20250725100806.1157-2-jie.gan@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250725100806.1157-1-jie.gan@oss.qualcomm.com> References: <20250725100806.1157-1-jie.gan@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: aRvlpTAuzpiqLYb5NMj0Hn4Dfh7uMAf6 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzI1MDA4NSBTYWx0ZWRfX9lPzAyCnkXQe YDR5Dl7kBZCIbu4kwOz1AFPVL7rCaiyBItTlaXHfCFmKYK+L9xgCTsG7BdiRgvbhwJrsB0DjNu8 AL8oT7X8sVY58hV459Zh+zRE1LYu/2c7PaEUJNm7P1QO2TCWLkIDQaF/PYHgOVvloG8U1WbJcrG tHrrg1r7k0reoGdgubZxQOMXGH7KllRY88VrFOlzyqDf1hrULZGKqYQjoxjzQ+FQyMFiSg3S+I9 stKg7JMRqxtJxDHxBXRZvZsfnE7AHTFZJUoLiRBmNVeUgJx/I9CGzuYKVIAjL4bmBggLxyEMbNN Bet+qmrY6RKEE5u1GyfKX1g4X4f1N+fmGTapoDRXVppOZ4MC3ppbNVsAHzLl0raL1ffJg5IETwT D23uw0MUKbCFEuAPLN3oRsuqzTpamR2KGgx9gZVL/X9jo3zyZrUpFDmPZ11mFzJz5XK8D42T X-Proofpoint-GUID: aRvlpTAuzpiqLYb5NMj0Hn4Dfh7uMAf6 X-Authority-Analysis: v=2.4 cv=S8bZwJsP c=1 sm=1 tr=0 ts=68835793 cx=c_pps a=JL+w9abYAAE89/QcEU+0QA==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=Wb1JkmetP80A:10 a=EUspDBNiAAAA:8 a=UMME_An3wchvczm7DuYA:9 a=324X-CrmTo6CU4MGRt3R:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-25_02,2025-07-24_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 lowpriorityscore=0 mlxlogscore=999 bulkscore=0 impostorscore=0 spamscore=0 malwarescore=0 adultscore=0 suspectscore=0 phishscore=0 priorityscore=1501 mlxscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507250085 Content-Type: text/plain; charset="utf-8" Remove ctcu_get_active_port from CTCU module and add it to the core framework. The port number is crucial for the CTCU device to identify which ETR it serves. With the port number we can correctly get required parameters of the CTCU device in TMC module. Signed-off-by: Jie Gan --- drivers/hwtracing/coresight/coresight-core.c | 24 +++++++++++++++++++ .../hwtracing/coresight/coresight-ctcu-core.c | 19 +-------------- drivers/hwtracing/coresight/coresight-priv.h | 2 ++ 3 files changed, 27 insertions(+), 18 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/hwtraci= ng/coresight/coresight-core.c index 1accd7cbd54b..042c4fa39e55 100644 --- a/drivers/hwtracing/coresight/coresight-core.c +++ b/drivers/hwtracing/coresight/coresight-core.c @@ -580,6 +580,30 @@ struct coresight_device *coresight_get_sink(struct cor= esight_path *path) } EXPORT_SYMBOL_GPL(coresight_get_sink); =20 +/** + * coresight_get_in_port_dest: get the in-port number of the dest device + * that is connected to the src device. + * + * @src: csdev of the source device. + * @dest: csdev of the destination device. + * + * Return: port number upon success or -EINVAL for fail. + */ +int coresight_get_in_port_dest(struct coresight_device *src, + struct coresight_device *dest) +{ + struct coresight_platform_data *pdata =3D dest->pdata; + int i; + + for (i =3D 0; i < pdata->nr_inconns; ++i) { + if (pdata->in_conns[i]->src_dev =3D=3D src) + return pdata->in_conns[i]->dest_port; + } + + return -EINVAL; +} +EXPORT_SYMBOL_GPL(coresight_get_in_port_dest); + u32 coresight_get_sink_id(struct coresight_device *csdev) { if (!csdev->ea) diff --git a/drivers/hwtracing/coresight/coresight-ctcu-core.c b/drivers/hw= tracing/coresight/coresight-ctcu-core.c index c6bafc96db96..3bdedf041390 100644 --- a/drivers/hwtracing/coresight/coresight-ctcu-core.c +++ b/drivers/hwtracing/coresight/coresight-ctcu-core.c @@ -118,23 +118,6 @@ static int __ctcu_set_etr_traceid(struct coresight_dev= ice *csdev, u8 traceid, in return 0; } =20 -/* - * Searching the sink device from helper's view in case there are multiple= helper devices - * connected to the sink device. - */ -static int ctcu_get_active_port(struct coresight_device *sink, struct core= sight_device *helper) -{ - struct coresight_platform_data *pdata =3D helper->pdata; - int i; - - for (i =3D 0; i < pdata->nr_inconns; ++i) { - if (pdata->in_conns[i]->src_dev =3D=3D sink) - return pdata->in_conns[i]->dest_port; - } - - return -EINVAL; -} - static int ctcu_set_etr_traceid(struct coresight_device *csdev, struct cor= esight_path *path, bool enable) { @@ -147,7 +130,7 @@ static int ctcu_set_etr_traceid(struct coresight_device= *csdev, struct coresight return -EINVAL; } =20 - port_num =3D ctcu_get_active_port(sink, csdev); + port_num =3D coresight_get_in_port_dest(sink, csdev); if (port_num < 0) return -EINVAL; =20 diff --git a/drivers/hwtracing/coresight/coresight-priv.h b/drivers/hwtraci= ng/coresight/coresight-priv.h index 33e22b1ba043..e51b22b8ebde 100644 --- a/drivers/hwtracing/coresight/coresight-priv.h +++ b/drivers/hwtracing/coresight/coresight-priv.h @@ -156,6 +156,8 @@ void coresight_remove_links(struct coresight_device *or= ig, u32 coresight_get_sink_id(struct coresight_device *csdev); void coresight_path_assign_trace_id(struct coresight_path *path, enum cs_mode mode); +int coresight_get_in_port_dest(struct coresight_device *src, + struct coresight_device *dest); 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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-23fa48fd29dsm33641435ad.176.2025.07.25.03.08.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Jul 2025 03:08:21 -0700 (PDT) From: Jie Gan To: Suzuki K Poulose , Mike Leach , James Clark , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Alexander Shishkin , Tingwei Zhang , Jinlong Mao Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, Jie Gan Subject: [PATCH v4 02/10] coresight: core: add a new API to retrieve the helper device Date: Fri, 25 Jul 2025 18:07:58 +0800 Message-Id: <20250725100806.1157-3-jie.gan@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250725100806.1157-1-jie.gan@oss.qualcomm.com> References: <20250725100806.1157-1-jie.gan@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-GUID: pNVq3O0ZfSw1x45FbURhvjikhHFO51gx X-Proofpoint-ORIG-GUID: pNVq3O0ZfSw1x45FbURhvjikhHFO51gx X-Authority-Analysis: v=2.4 cv=bKAWIO+Z c=1 sm=1 tr=0 ts=68835797 cx=c_pps a=oF/VQ+ItUULfLr/lQ2/icg==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=Wb1JkmetP80A:10 a=EUspDBNiAAAA:8 a=ViBFXQGRTvhYuEXyb1sA:9 a=3WC7DwWrALyhR5TkjVHa:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzI1MDA4NSBTYWx0ZWRfX9+dfDYfUISFX 0O5chMnu6UHBFyxXEqalF0qAWum3nWxFMM+yYVYDqaWgKorBKzUbKntTPmk1FtL/uZCfBRtwKQ9 h35lYnQoTsVz4SaW5ZMIK+KrR/sZpRt4najdmIhICYRhivRq8U687xpTnAsxZP1fG0ym29MOUH6 1w5Yq6ZiUSDLtjCGU9cAYnBICwQfd/OAXpQ02Yw34z3eVMV6azlOVspqf98RQ93dZMCSSxRCHVS 6Jz2d7Ols+moyZ/yJKRoKl2LS6ABymbLDazlsq/lKDpjteDr/r8g8X7TkdpDqdMsT2RmFSngkng yhm0csBPwJ8xaVTbnuL1de6oiFJ3mmaovAKDMm4afxGP0kw4Td7Xehfoo7RIxbcv2YymFTjzqL0 EohC0Lq+7n4oD80XDKj547uWo2tUl/yErYKwhqeKphgY+RphiJNxUEAiriV+KZdhpmxxRM1E X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-25_02,2025-07-24_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 bulkscore=0 spamscore=0 mlxlogscore=999 clxscore=1015 phishscore=0 priorityscore=1501 lowpriorityscore=0 adultscore=0 mlxscore=0 suspectscore=0 malwarescore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507250085 Content-Type: text/plain; charset="utf-8" Retrieving the helper device of the specific coresight device based on its helper_subtype because a single coresight device may has multiple types of the helper devices. Signed-off-by: Jie Gan Reviewed-by: Mike Leach --- drivers/hwtracing/coresight/coresight-core.c | 35 ++++++++++++++++++++ drivers/hwtracing/coresight/coresight-priv.h | 2 ++ 2 files changed, 37 insertions(+) diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/hwtraci= ng/coresight/coresight-core.c index 042c4fa39e55..018b1119c48a 100644 --- a/drivers/hwtracing/coresight/coresight-core.c +++ b/drivers/hwtracing/coresight/coresight-core.c @@ -580,6 +580,41 @@ struct coresight_device *coresight_get_sink(struct cor= esight_path *path) } EXPORT_SYMBOL_GPL(coresight_get_sink); =20 +/** + * coresight_get_helper: find the helper device of the assigned csdev. + * + * @csdev: The csdev the helper device is conntected to. + * @type: helper_subtype of the expected helper device. + * + * Retrieve the helper device for the specific csdev based on its + * helper_subtype. + * + * Return: the helper's csdev upon success or NULL for fail. + */ +struct coresight_device *coresight_get_helper(struct coresight_device *csd= ev, + int type) +{ + int i; + struct coresight_device *helper; + + /* protect the connections */ + mutex_lock(&coresight_mutex); + for (i =3D 0; i < csdev->pdata->nr_outconns; ++i) { + helper =3D csdev->pdata->out_conns[i]->dest_dev; + if (!helper || !coresight_is_helper(helper)) + continue; + + if (helper->subtype.helper_subtype =3D=3D type) { + mutex_unlock(&coresight_mutex); + return helper; + } + } + mutex_unlock(&coresight_mutex); + + return NULL; +} +EXPORT_SYMBOL_GPL(coresight_get_helper); + /** * coresight_get_in_port_dest: get the in-port number of the dest device * that is connected to the src device. diff --git a/drivers/hwtracing/coresight/coresight-priv.h b/drivers/hwtraci= ng/coresight/coresight-priv.h index e51b22b8ebde..f80122827934 100644 --- a/drivers/hwtracing/coresight/coresight-priv.h +++ b/drivers/hwtracing/coresight/coresight-priv.h @@ -158,6 +158,8 @@ void coresight_path_assign_trace_id(struct coresight_pa= th *path, enum cs_mode mode); int coresight_get_in_port_dest(struct coresight_device *src, struct coresight_device *dest); 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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-23fa48fd29dsm33641435ad.176.2025.07.25.03.08.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Jul 2025 03:08:25 -0700 (PDT) From: Jie Gan To: Suzuki K Poulose , Mike Leach , James Clark , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Alexander Shishkin , Tingwei Zhang , Jinlong Mao Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, Jie Gan Subject: [PATCH v4 03/10] coresight: tmc: add etr_buf_list to store allocated etr_buf Date: Fri, 25 Jul 2025 18:07:59 +0800 Message-Id: <20250725100806.1157-4-jie.gan@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250725100806.1157-1-jie.gan@oss.qualcomm.com> References: <20250725100806.1157-1-jie.gan@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Authority-Analysis: v=2.4 cv=NfTm13D4 c=1 sm=1 tr=0 ts=6883579b cx=c_pps a=JL+w9abYAAE89/QcEU+0QA==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=Wb1JkmetP80A:10 a=EUspDBNiAAAA:8 a=ORm1qb0EFYpRwVLUulEA:9 a=324X-CrmTo6CU4MGRt3R:22 X-Proofpoint-ORIG-GUID: NR2zia_0B0UYxZWSluYsJEYN3CpjSybr X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzI1MDA4NSBTYWx0ZWRfXwa8AokiZIWJ4 EPJC/q/SAtWhyCI7zRmLH2Fk+gHBnSadlaskuSH5BTSJ8K9oDzmdWxAzDaPEKlDiCEtECDj7arg X6+hiHbDu0cCjOgZsBMWhaNETw79rtD7BCYNkAvm5WgExb4AVzgxKbvNcn7mPDcgWZXWCGX2Xq+ qxkTJybw4soDffzqP6XN6Ojf8YBWBA+YxIW3Cd3UwmaXlyA4V7mgCD8jdN1v+hPyJbA+cQV7FAv LgGD5slgKA5D8M5GghHCGoGINQ+lds22IJ2yESkOwanwwGbSwGg/7cgjnBiZahyhnI1iQw3JP9N KnlfEX6fQibncVyQVPJYDUZ3w41+neyRNHSdohcuLTP0OQffb4nsB/tDoCMF+b2iUxYFpNCpERM Leztm9Tr21N3HDuVPJ1n3MjDKYeJzSmCy28D/K/ET5zMVuVuXCc8H12wk/qiOnvb93OQT4dA X-Proofpoint-GUID: NR2zia_0B0UYxZWSluYsJEYN3CpjSybr X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-25_02,2025-07-24_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 adultscore=0 clxscore=1015 suspectscore=0 lowpriorityscore=0 bulkscore=0 spamscore=0 priorityscore=1501 phishscore=0 mlxscore=0 mlxlogscore=999 malwarescore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507250085 Content-Type: text/plain; charset="utf-8" Add a list to store allocated etr_buf. The byte-cntr functionality requires two etr_buf to receive trace data. The active etr_buf collects the trace data from source device, while the byte-cntr reading function accesses the deactivated etr_buf after is has been filled and synced, transferring data to the userspace. Signed-off-by: Jie Gan --- .../hwtracing/coresight/coresight-tmc-core.c | 1 + drivers/hwtracing/coresight/coresight-tmc.h | 19 +++++++++++++++++++ 2 files changed, 20 insertions(+) diff --git a/drivers/hwtracing/coresight/coresight-tmc-core.c b/drivers/hwt= racing/coresight/coresight-tmc-core.c index be964656be93..4d249af93097 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-core.c +++ b/drivers/hwtracing/coresight/coresight-tmc-core.c @@ -830,6 +830,7 @@ static int __tmc_probe(struct device *dev, struct resou= rce *res) idr_init(&drvdata->idr); mutex_init(&drvdata->idr_mutex); dev_list =3D &etr_devs; + INIT_LIST_HEAD(&drvdata->etr_buf_list); break; case TMC_CONFIG_TYPE_ETF: desc.groups =3D coresight_etf_groups; diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracin= g/coresight/coresight-tmc.h index 6541a27a018e..52ee5f8efe8c 100644 --- a/drivers/hwtracing/coresight/coresight-tmc.h +++ b/drivers/hwtracing/coresight/coresight-tmc.h @@ -208,6 +208,21 @@ struct tmc_resrv_buf { s64 len; }; =20 +/** + * @sysfs_buf: Allocated sysfs_buf. + * @is_free: Indicates whether the buffer is free to choose. + * @reading: Indicates whether the buffer is reading. + * @pos: Position of the buffer. + * @node: Node in etr_buf_list. + */ +struct etr_buf_node { + struct etr_buf *sysfs_buf; + bool is_free; + bool reading; + loff_t pos; + struct list_head node; +}; + /** * struct tmc_drvdata - specifics associated to an TMC component * @pclk: APB clock if present, otherwise NULL @@ -242,6 +257,8 @@ struct tmc_resrv_buf { * (after crash) by default. * @crash_mdata: Reserved memory for storing tmc crash metadata. * Used by ETR/ETF. + * @etr_buf_list: List that is used to manage allocated etr_buf. + * @reading_node: Available buffer for byte-cntr reading. */ struct tmc_drvdata { struct clk *pclk; @@ -271,6 +288,8 @@ struct tmc_drvdata { struct etr_buf *perf_buf; struct tmc_resrv_buf resrv_buf; struct tmc_resrv_buf crash_mdata; + struct list_head etr_buf_list; + struct etr_buf_node *reading_node; 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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-23fa48fd29dsm33641435ad.176.2025.07.25.03.08.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Jul 2025 03:08:30 -0700 (PDT) From: Jie Gan To: Suzuki K Poulose , Mike Leach , James Clark , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Alexander Shishkin , Tingwei Zhang , Jinlong Mao Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, Jie Gan Subject: [PATCH v4 04/10] coresight: tmc: add create/delete functions for etr_buf_node Date: Fri, 25 Jul 2025 18:08:00 +0800 Message-Id: <20250725100806.1157-5-jie.gan@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250725100806.1157-1-jie.gan@oss.qualcomm.com> References: <20250725100806.1157-1-jie.gan@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: ClzdTnKXlyQ9si4pI2ZgINN_1Ce2djDC X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzI1MDA4NSBTYWx0ZWRfXxNKT7JdePWSI CoC+lhFecqghH9kMWoCGcCgJ0334KYiuLak3DGb4kLvpif4U5ycg5MAimhXbMy9OEgMm7LEDh1p xwtCfSbr0hREkMnazfTdFqL8JO9cWOm+G+1zZu6ggkf/ddb9JIr7MnHREkGxJw6CuAiaIC9WjhM mX7TGNvvQ7+XEtAzTnVV39JFYT6mZh+/Ics8ZfdZb8HmGlp37TuKErK6S0zlKwFwV9sl1dBO8au sVUC6TbzwJTjiJksiUiYsP3dzRAnl8WfetJKm4oe/7fxcwdICRqkfBhrMZp/dBr3TgTvqmEgpRW NdBkq1INkaQgCOSbeQ6rSf+/XSOQECDlb8iCN8uivSQbtqwGcx8VlEorpznrUUGRTkMpKJex+AI F6qXvXnb3a7k+0D7weWdxugYBbxdXAVx9iVFfqxiM41PzOyPUC3WGs11K7BXCQ14leVjzP/o X-Proofpoint-GUID: ClzdTnKXlyQ9si4pI2ZgINN_1Ce2djDC X-Authority-Analysis: v=2.4 cv=S8bZwJsP c=1 sm=1 tr=0 ts=688357a0 cx=c_pps a=IZJwPbhc+fLeJZngyXXI0A==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=Wb1JkmetP80A:10 a=EUspDBNiAAAA:8 a=ILCX3kR9VMWRWyEhewYA:9 a=uG9DUKGECoFWVXl0Dc02:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-25_02,2025-07-24_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 lowpriorityscore=0 mlxlogscore=999 bulkscore=0 impostorscore=0 spamscore=0 malwarescore=0 adultscore=0 suspectscore=0 phishscore=0 priorityscore=1501 mlxscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507250085 Content-Type: text/plain; charset="utf-8" Create and insert or remove the etr_buf_node to/from the etr_buf_list. Signed-off-by: Jie Gan --- .../hwtracing/coresight/coresight-tmc-etr.c | 65 +++++++++++++++++++ drivers/hwtracing/coresight/coresight-tmc.h | 2 + 2 files changed, 67 insertions(+) diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtr= acing/coresight/coresight-tmc-etr.c index b07fcdb3fe1a..e8ecb3e087ab 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c @@ -1909,6 +1909,71 @@ const struct coresight_ops tmc_etr_cs_ops =3D { .panic_ops =3D &tmc_etr_sync_ops, }; =20 +/** + * tmc_clean_etr_buf_list - clean the etr_buf_list. + * @drvdata: driver data of the TMC device. + * + * Remove the allocated node from the list and free the extra buffer. + */ +void tmc_clean_etr_buf_list(struct tmc_drvdata *drvdata) +{ + struct etr_buf_node *nd, *next; + + list_for_each_entry_safe(nd, next, &drvdata->etr_buf_list, node) { + if (nd->sysfs_buf =3D=3D drvdata->sysfs_buf) { + list_del(&nd->node); + kfree(nd); + } else { + /* Free allocated buffers which are not utilized by ETR */ + list_del(&nd->node); + tmc_free_etr_buf(nd->sysfs_buf); + nd->sysfs_buf =3D NULL; + kfree(nd); + } + } +} +EXPORT_SYMBOL_GPL(tmc_clean_etr_buf_list); + +/** + * tmc_create_etr_buf_node - create a node to store the alloc_buf and + * insert the node to the etr_buf_list. Create a new buffer if the + * alloc_buf is NULL. + * @drvdata: driver data of the TMC device. + * @alloc_buf: the buffer that is inserted to the list. + * + * Return 0 upon success and return the error number if fail. + */ +int tmc_create_etr_buf_node(struct tmc_drvdata *drvdata, struct etr_buf *a= lloc_buf) +{ + struct etr_buf_node *sysfs_buf_node; + struct etr_buf *sysfs_buf; + + if (!alloc_buf) { + sysfs_buf =3D tmc_alloc_etr_buf(drvdata, drvdata->size, 0, cpu_to_node(0= ), NULL); + if (IS_ERR(sysfs_buf)) + return PTR_ERR(sysfs_buf); + } else + sysfs_buf =3D alloc_buf; + + sysfs_buf_node =3D kzalloc(sizeof(struct etr_buf_node), GFP_KERNEL); + if (IS_ERR(sysfs_buf_node)) { + if (!alloc_buf) + tmc_free_etr_buf(sysfs_buf); + return PTR_ERR(sysfs_buf_node); + } + + sysfs_buf_node->sysfs_buf =3D sysfs_buf; + sysfs_buf_node->reading =3D false; + if (!alloc_buf) + sysfs_buf_node->is_free =3D true; + else + sysfs_buf_node->is_free =3D false; + list_add(&sysfs_buf_node->node, &drvdata->etr_buf_list); + + return 0; +} +EXPORT_SYMBOL_GPL(tmc_create_etr_buf_node); + int tmc_read_prepare_etr(struct tmc_drvdata *drvdata) { int ret =3D 0; diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracin= g/coresight/coresight-tmc.h index 52ee5f8efe8c..3cb8ba9f88f5 100644 --- a/drivers/hwtracing/coresight/coresight-tmc.h +++ b/drivers/hwtracing/coresight/coresight-tmc.h @@ -461,5 +461,7 @@ void tmc_etr_remove_catu_ops(void); struct etr_buf *tmc_etr_get_buffer(struct coresight_device *csdev, enum cs_mode mode, void *data); extern const struct attribute_group coresight_etr_group; +void tmc_clean_etr_buf_list(struct tmc_drvdata *drvdata); +int tmc_create_etr_buf_node(struct tmc_drvdata *drvdata, struct etr_buf *a= lloc_buf); =20 #endif --=20 2.34.1 From nobody Mon Oct 6 03:15:58 2025 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A51C42E92C1 for ; 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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-23fa48fd29dsm33641435ad.176.2025.07.25.03.08.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Jul 2025 03:08:35 -0700 (PDT) From: Jie Gan To: Suzuki K Poulose , Mike Leach , James Clark , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Alexander Shishkin , Tingwei Zhang , Jinlong Mao Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, Jie Gan Subject: [PATCH v4 05/10] coresight: tmc: Introduce tmc_read_ops to wrap read operations Date: Fri, 25 Jul 2025 18:08:01 +0800 Message-Id: <20250725100806.1157-6-jie.gan@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250725100806.1157-1-jie.gan@oss.qualcomm.com> References: <20250725100806.1157-1-jie.gan@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzI1MDA4NSBTYWx0ZWRfXyv2HBS9ihMcv zFRyf2aV34LF5gB+YuOripNFfjSkRtnM+L0R1FfuP1o/KjejYxowDfcz9JW8AMrEZ8msiyPf+ru zCID/Oy3jDO5az7JmHg2qf38g1LC0r68L++No4wvVPTyOi1/XlzAs1FeXtL6HW3uEjRX/v6O5bT e6KYf8RGBQG3l42daPUb0FvWFOuaUuhB6NrndzQiu+9z5wOzdmS+AzHWKAjbRQb764qT/bgDKNs gHTFAOcua1IPhFAZyw67fwO5OJAuFF5dGpPRM5rUaercKdJEOKVqkLA9rXV/efrUrt46SWzAJ3l EnrWCmhJJwBxtNP70vYNWEitTz2szMDV/q5hUyKY8RIODsB1snOur7N2v9YwXE5wqO+xVTp0oRA hlGJeT3b5eWJxMxaBq/VUtfxBqaDqWWRINpQ6hQpl0KNDD+vyEUnCD4+mnK+xqcu5HLl4tBw X-Proofpoint-ORIG-GUID: eLTObfGHH3GJGdwEnlplSAcTCdUzp33d X-Authority-Analysis: v=2.4 cv=FcA3xI+6 c=1 sm=1 tr=0 ts=688357a5 cx=c_pps a=Oh5Dbbf/trHjhBongsHeRQ==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=Wb1JkmetP80A:10 a=EUspDBNiAAAA:8 a=1hiE41pZ4Zj50arX-_gA:9 a=_Vgx9l1VpLgwpw_dHYaR:22 X-Proofpoint-GUID: eLTObfGHH3GJGdwEnlplSAcTCdUzp33d X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-25_02,2025-07-24_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 bulkscore=0 adultscore=0 suspectscore=0 impostorscore=0 malwarescore=0 spamscore=0 lowpriorityscore=0 priorityscore=1501 mlxlogscore=999 clxscore=1015 mlxscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507250085 Content-Type: text/plain; charset="utf-8" Introduce tmc_read_ops as a wrapper, wrap read operations, for reading trace data from the TMC buffer. Signed-off-by: Jie Gan Reviewed-by: Mike Leach --- .../hwtracing/coresight/coresight-tmc-core.c | 50 +++++++++---------- drivers/hwtracing/coresight/coresight-tmc.h | 17 +++++++ 2 files changed, 40 insertions(+), 27 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-tmc-core.c b/drivers/hwt= racing/coresight/coresight-tmc-core.c index 4d249af93097..f668047c5df4 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-core.c +++ b/drivers/hwtracing/coresight/coresight-tmc-core.c @@ -232,17 +232,10 @@ static int tmc_read_prepare(struct tmc_drvdata *drvda= ta) { int ret =3D 0; =20 - switch (drvdata->config_type) { - case TMC_CONFIG_TYPE_ETB: - case TMC_CONFIG_TYPE_ETF: - ret =3D tmc_read_prepare_etb(drvdata); - break; - case TMC_CONFIG_TYPE_ETR: - ret =3D tmc_read_prepare_etr(drvdata); - break; - default: + if (drvdata->read_ops) + ret =3D drvdata->read_ops->read_prepare(drvdata); + else ret =3D -EINVAL; - } =20 if (!ret) dev_dbg(&drvdata->csdev->dev, "TMC read start\n"); @@ -254,17 +247,10 @@ static int tmc_read_unprepare(struct tmc_drvdata *drv= data) { int ret =3D 0; =20 - switch (drvdata->config_type) { - case TMC_CONFIG_TYPE_ETB: - case TMC_CONFIG_TYPE_ETF: - ret =3D tmc_read_unprepare_etb(drvdata); - break; - case TMC_CONFIG_TYPE_ETR: - ret =3D tmc_read_unprepare_etr(drvdata); - break; - default: + if (drvdata->read_ops) + ret =3D drvdata->read_ops->read_unprepare(drvdata); + else ret =3D -EINVAL; - } =20 if (!ret) dev_dbg(&drvdata->csdev->dev, "TMC read end\n"); @@ -291,13 +277,8 @@ static int tmc_open(struct inode *inode, struct file *= file) static ssize_t tmc_get_sysfs_trace(struct tmc_drvdata *drvdata, loff_t pos= , size_t len, char **bufpp) { - switch (drvdata->config_type) { - case TMC_CONFIG_TYPE_ETB: - case TMC_CONFIG_TYPE_ETF: - return tmc_etb_get_sysfs_trace(drvdata, pos, len, bufpp); - case TMC_CONFIG_TYPE_ETR: - return tmc_etr_get_sysfs_trace(drvdata, pos, len, bufpp); - } + if (drvdata->read_ops) + return drvdata->read_ops->get_trace_data(drvdata, pos, len, bufpp); =20 return -EINVAL; } @@ -769,6 +750,18 @@ static void register_crash_dev_interface(struct tmc_dr= vdata *drvdata, "Valid crash tracedata found\n"); } =20 +static const struct tmc_read_ops tmc_etb_read_ops =3D { + .read_prepare =3D tmc_read_prepare_etb, + .read_unprepare =3D tmc_read_unprepare_etb, + .get_trace_data =3D tmc_etb_get_sysfs_trace, +}; + +static const struct tmc_read_ops tmc_etr_read_ops =3D { + .read_prepare =3D tmc_read_prepare_etr, + .read_unprepare =3D tmc_read_unprepare_etr, + .get_trace_data =3D tmc_etr_get_sysfs_trace, +}; + static int __tmc_probe(struct device *dev, struct resource *res) { int ret =3D 0; @@ -818,6 +811,7 @@ static int __tmc_probe(struct device *dev, struct resou= rce *res) desc.subtype.sink_subtype =3D CORESIGHT_DEV_SUBTYPE_SINK_BUFFER; desc.ops =3D &tmc_etb_cs_ops; dev_list =3D &etb_devs; + drvdata->read_ops =3D &tmc_etb_read_ops; break; case TMC_CONFIG_TYPE_ETR: desc.groups =3D coresight_etr_groups; @@ -831,6 +825,7 @@ static int __tmc_probe(struct device *dev, struct resou= rce *res) mutex_init(&drvdata->idr_mutex); dev_list =3D &etr_devs; INIT_LIST_HEAD(&drvdata->etr_buf_list); + drvdata->read_ops =3D &tmc_etr_read_ops; break; case TMC_CONFIG_TYPE_ETF: desc.groups =3D coresight_etf_groups; @@ -839,6 +834,7 @@ static int __tmc_probe(struct device *dev, struct resou= rce *res) desc.subtype.link_subtype =3D CORESIGHT_DEV_SUBTYPE_LINK_FIFO; desc.ops =3D &tmc_etf_cs_ops; dev_list =3D &etf_devs; + drvdata->read_ops =3D &tmc_etb_read_ops; break; default: pr_err("%s: Unsupported TMC config\n", desc.name); diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracin= g/coresight/coresight-tmc.h index 3cb8ba9f88f5..2ad8e288c94b 100644 --- a/drivers/hwtracing/coresight/coresight-tmc.h +++ b/drivers/hwtracing/coresight/coresight-tmc.h @@ -223,6 +223,8 @@ struct etr_buf_node { struct list_head node; }; =20 +struct tmc_read_ops; + /** * struct tmc_drvdata - specifics associated to an TMC component * @pclk: APB clock if present, otherwise NULL @@ -259,6 +261,7 @@ struct etr_buf_node { * Used by ETR/ETF. * @etr_buf_list: List that is used to manage allocated etr_buf. * @reading_node: Available buffer for byte-cntr reading. + * @tmc_read_ops: Read operations for TMC device. */ struct tmc_drvdata { struct clk *pclk; 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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-23fa48fd29dsm33641435ad.176.2025.07.25.03.08.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Jul 2025 03:08:39 -0700 (PDT) From: Jie Gan To: Suzuki K Poulose , Mike Leach , James Clark , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Alexander Shishkin , Tingwei Zhang , Jinlong Mao Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, Jie Gan , Krzysztof Kozlowski Subject: [PATCH v4 06/10] dt-bindings: arm: add an interrupt property for Coresight CTCU Date: Fri, 25 Jul 2025 18:08:02 +0800 Message-Id: <20250725100806.1157-7-jie.gan@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250725100806.1157-1-jie.gan@oss.qualcomm.com> References: <20250725100806.1157-1-jie.gan@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Authority-Analysis: v=2.4 cv=BMKzrEQG c=1 sm=1 tr=0 ts=688357aa cx=c_pps a=IZJwPbhc+fLeJZngyXXI0A==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=Wb1JkmetP80A:10 a=KKAkSRfTAAAA:8 a=EUspDBNiAAAA:8 a=gSyxy6DGYGa4b6s9XCEA:9 a=uG9DUKGECoFWVXl0Dc02:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-ORIG-GUID: 8cNySwPYth0gPb1UH3lNpwE5f2UM66al X-Proofpoint-GUID: 8cNySwPYth0gPb1UH3lNpwE5f2UM66al X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzI1MDA4NSBTYWx0ZWRfX4KDy0Bfql3Jk FTl9ZEGLmKPUKsG87v1q4El09zog73pO93Kz0l5d2Kzj8wzTIU7B+Oowrip+QRWrrDPVcUvPWY7 b38+MgyZdlqLWx1vrS4uuJMWM73yzBQl9xaoUF4Y7kHA/Hk2AfPjIuwJtVCnzdLQlYg6SJiMWAC VveWg8iTJVT24WFzyuAPIdFy69t7+HNxXWaxiLs3ugK778hH6Bd6TNAnsdyLbuwQuMkqlXDEIxD fXCvmxXAAlDKqk5vyRshHcUqswQnf7+09j94crb6VyMWdC4XfrpyG3d8sufqumixzn3Fiv7Wkas QQUswLSfcKvvV+wxhr4LtZnklduzC6tCrja3pzhvOFOBuqHIKUiJ6S+DDWr/zNc1AI1e90NQWCU 2vt8fPFNg+dbEIpbYI4GIB4MWWB4J9qp9e59E0p+8OEWV0LkodJSWZ8YopnWQKqYigd7iBYX X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-25_02,2025-07-24_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 mlxscore=0 spamscore=0 impostorscore=0 priorityscore=1501 bulkscore=0 malwarescore=0 adultscore=0 phishscore=0 suspectscore=0 mlxlogscore=999 clxscore=1015 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507250085 Content-Type: text/plain; charset="utf-8" Add an interrupt property to CTCU device. The interrupt will be triggered when the data size in the ETR buffer exceeds the threshold of the BYTECNTRVAL register. Programming a threshold in the BYTECNTRVAL register of CTCU device will enable the interrupt. Acked-by: Krzysztof Kozlowski Signed-off-by: Jie Gan --- .../bindings/arm/qcom,coresight-ctcu.yaml | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml= b/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml index 843b52eaf872..ea05ad8f3dd3 100644 --- a/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml +++ b/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml @@ -39,6 +39,16 @@ properties: items: - const: apb =20 + interrupts: + items: + - description: Byte cntr interrupt for etr0 + - description: Byte cntr interrupt for etr1 + + interrupt-names: + items: + - const: etr0 + - const: etr1 + in-ports: $ref: /schemas/graph.yaml#/properties/ports =20 @@ -56,6 +66,8 @@ additionalProperties: false =20 examples: - | + #include + ctcu@1001000 { compatible =3D "qcom,sa8775p-ctcu"; reg =3D <0x1001000 0x1000>; @@ -63,6 +75,11 @@ examples: clocks =3D <&aoss_qmp>; clock-names =3D "apb"; =20 + interrupts =3D , + ; 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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-23fa48fd29dsm33641435ad.176.2025.07.25.03.08.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Jul 2025 03:08:44 -0700 (PDT) From: Jie Gan To: Suzuki K Poulose , Mike Leach , James Clark , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Alexander Shishkin , Tingwei Zhang , Jinlong Mao Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, Jie Gan Subject: [PATCH v4 07/10] coresight: ctcu: enable byte-cntr for TMC ETR devices Date: Fri, 25 Jul 2025 18:08:03 +0800 Message-Id: <20250725100806.1157-8-jie.gan@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250725100806.1157-1-jie.gan@oss.qualcomm.com> References: <20250725100806.1157-1-jie.gan@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-GUID: lA7XxAua-4E6_Kr7ge6QjjshERyYbKJ3 X-Proofpoint-ORIG-GUID: lA7XxAua-4E6_Kr7ge6QjjshERyYbKJ3 X-Authority-Analysis: v=2.4 cv=bKAWIO+Z c=1 sm=1 tr=0 ts=688357af cx=c_pps a=MTSHoo12Qbhz2p7MsH1ifg==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=Wb1JkmetP80A:10 a=EUspDBNiAAAA:8 a=TrPPj8Ph-2G9coJyck8A:9 a=GvdueXVYPmCkWapjIL-Q:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzI1MDA4NSBTYWx0ZWRfX09liLlyr2KDk 9HI8829Gcrfl7rueFzZj9xDb8a7mT4fF5MxXuhcwCTquENfYDOv4bV9k/fvRUCsAij2bZ7OboDL tSdcVgsq20YZPx5ZS064yznTwk+4WzfjunPJ2qhQVfJqa2Al/trkf0LH/w7PslcPAU7EaBF91Jr tgXpdVrM0O6aK2p+RVU/im8SHkBc3PjteSM157MJ4p88W2mmc2bP5+sJmemLvqhylCVFB9NLTDA 3nCs6vUvPmoA6mzwbQd4dozaPSebL3+mYQ2984HarAMgXHul6JilgRjpHoBdIZ23aBLwzppK7ws v3iDsKVoo0mD7ZQYczXUPctuWuBWMKhqucDKWOZnpguuo4u2FV2h+kTQAdJA2p9bJyh/1nAFXYb E1/kgSRr6qhyywXSNnFqNcVbIMiJrBAhVQnZO3vBtiPnxKpk/HoISmOgfD4ol7MNIQuFLqWV X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-25_02,2025-07-24_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 bulkscore=0 spamscore=0 mlxlogscore=999 clxscore=1015 phishscore=0 priorityscore=1501 lowpriorityscore=0 adultscore=0 mlxscore=0 suspectscore=0 malwarescore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507250085 Content-Type: text/plain; charset="utf-8" The byte-cntr function provided by the CTCU device is used to transfer data from the ETR buffer to the userspace. An interrupt is triggered if the data size exceeds the threshold set in the BYTECNTRVAL register. The interrupt handler counts the number of triggered interruptions and the read function will read the data from the synced ETR buffer. Switching the sysfs_buf when current buffer is full or the timeout is triggered and resets rrp and rwp registers after switched the buffer. The synced buffer will become available for reading after the switch. Signed-off-by: Jie Gan --- .../testing/sysfs-bus-coresight-devices-ctcu | 5 + drivers/hwtracing/coresight/Makefile | 2 +- .../coresight/coresight-ctcu-byte-cntr.c | 364 ++++++++++++++++++ .../hwtracing/coresight/coresight-ctcu-core.c | 94 ++++- drivers/hwtracing/coresight/coresight-ctcu.h | 60 ++- .../hwtracing/coresight/coresight-tmc-etr.c | 16 + drivers/hwtracing/coresight/coresight-tmc.h | 2 + 7 files changed, 530 insertions(+), 13 deletions(-) create mode 100644 Documentation/ABI/testing/sysfs-bus-coresight-devices-c= tcu create mode 100644 drivers/hwtracing/coresight/coresight-ctcu-byte-cntr.c diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-ctcu b/D= ocumentation/ABI/testing/sysfs-bus-coresight-devices-ctcu new file mode 100644 index 000000000000..43064bf1aac7 --- /dev/null +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-ctcu @@ -0,0 +1,5 @@ +What: /sys/bus/coresight/devices//irq_val +Date: June 2025 +KernelVersion: 6.16 +Contact: Tingwei Zhang ; Jinlong Ma= o ; Jie Gan +Description: (RW) Configure the IRQ value for byte-cntr register. diff --git a/drivers/hwtracing/coresight/Makefile b/drivers/hwtracing/cores= ight/Makefile index ab16d06783a5..821a1b06b20c 100644 --- a/drivers/hwtracing/coresight/Makefile +++ b/drivers/hwtracing/coresight/Makefile @@ -55,5 +55,5 @@ coresight-cti-y :=3D coresight-cti-core.o coresight-cti-p= latform.o \ obj-$(CONFIG_ULTRASOC_SMB) +=3D ultrasoc-smb.o obj-$(CONFIG_CORESIGHT_DUMMY) +=3D coresight-dummy.o obj-$(CONFIG_CORESIGHT_CTCU) +=3D coresight-ctcu.o -coresight-ctcu-y :=3D coresight-ctcu-core.o +coresight-ctcu-y :=3D coresight-ctcu-core.o coresight-ctcu-byte-cntr.o obj-$(CONFIG_CORESIGHT_KUNIT_TESTS) +=3D coresight-kunit-tests.o diff --git a/drivers/hwtracing/coresight/coresight-ctcu-byte-cntr.c b/drive= rs/hwtracing/coresight/coresight-ctcu-byte-cntr.c new file mode 100644 index 000000000000..83e4a17d897f --- /dev/null +++ b/drivers/hwtracing/coresight/coresight-ctcu-byte-cntr.c @@ -0,0 +1,364 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include + +#include "coresight-ctcu.h" +#include "coresight-priv.h" +#include "coresight-tmc.h" + +static irqreturn_t byte_cntr_handler(int irq, void *data) +{ + struct ctcu_byte_cntr *byte_cntr_data =3D (struct ctcu_byte_cntr *)data; + + atomic_inc(&byte_cntr_data->irq_cnt); + wake_up(&byte_cntr_data->wq); + + return IRQ_HANDLED; +} + +/* Start the byte-cntr function when the path is enabled. */ +void ctcu_byte_cntr_start(struct coresight_device *csdev, struct coresight= _path *path) +{ + struct ctcu_drvdata *drvdata =3D dev_get_drvdata(csdev->dev.parent); + struct coresight_device *sink =3D coresight_get_sink(path); + struct ctcu_byte_cntr *byte_cntr_data; + int port_num; + + if (!sink) + return; + + port_num =3D coresight_get_in_port_dest(sink, csdev); + if (port_num < 0) + return; + + byte_cntr_data =3D &drvdata->byte_cntr_data[port_num]; + /* Don't start byte-cntr function when threshold is not set. */ + if (!byte_cntr_data->thresh_val || byte_cntr_data->enable) + return; + + guard(raw_spinlock_irqsave)(&byte_cntr_data->spin_lock); + byte_cntr_data->enable =3D true; + byte_cntr_data->reading_buf =3D false; +} + +/* Stop the byte-cntr function when the path is disabled. */ +void ctcu_byte_cntr_stop(struct coresight_device *csdev, struct coresight_= path *path) +{ + struct ctcu_drvdata *drvdata =3D dev_get_drvdata(csdev->dev.parent); + struct coresight_device *sink =3D coresight_get_sink(path); + struct ctcu_byte_cntr *byte_cntr_data; + int port_num; + + if (!sink || coresight_get_mode(sink) =3D=3D CS_MODE_SYSFS) + return; + + port_num =3D coresight_get_in_port_dest(sink, csdev); + if (port_num < 0) + return; + + byte_cntr_data =3D &drvdata->byte_cntr_data[port_num]; + guard(raw_spinlock_irqsave)(&byte_cntr_data->spin_lock); + byte_cntr_data->enable =3D false; +} + +static void ctcu_reset_sysfs_buf(struct tmc_drvdata *drvdata) +{ + u32 sts; + + CS_UNLOCK(drvdata->base); + tmc_write_rrp(drvdata, drvdata->sysfs_buf->hwaddr); + tmc_write_rwp(drvdata, drvdata->sysfs_buf->hwaddr); + sts =3D readl_relaxed(drvdata->base + TMC_STS) & ~TMC_STS_FULL; + writel_relaxed(sts, drvdata->base + TMC_STS); + CS_LOCK(drvdata->base); +} + +static struct ctcu_byte_cntr *ctcu_get_byte_cntr_data(struct tmc_drvdata *= drvdata) +{ + struct ctcu_byte_cntr *byte_cntr_data; + struct ctcu_drvdata *ctcu_drvdata; + struct coresight_device *helper; + int port; + + helper =3D coresight_get_helper(drvdata->csdev, CORESIGHT_DEV_SUBTYPE_HEL= PER_CTCU); + if (!helper) + return NULL; + + port =3D coresight_get_in_port_dest(drvdata->csdev, helper); + if (port < 0) + return NULL; + + ctcu_drvdata =3D dev_get_drvdata(helper->dev.parent); + byte_cntr_data =3D &ctcu_drvdata->byte_cntr_data[port]; + return byte_cntr_data; +} + +static bool ctcu_byte_cntr_switch_buffer(struct tmc_drvdata *drvdata, + struct ctcu_byte_cntr *byte_cntr_data) +{ + struct etr_buf_node *nd, *next, *curr_node, *picked_node; + struct etr_buf *curr_buf =3D drvdata->sysfs_buf; + bool found_free_buf =3D false; + + if (WARN_ON(!drvdata || !byte_cntr_data)) + return found_free_buf; + + /* Stop the ETR before we start the switch */ + if (coresight_get_mode(drvdata->csdev) !=3D CS_MODE_DISABLED) + tmc_etr_disable_hw_before_switching(drvdata); + + list_for_each_entry_safe(nd, next, &drvdata->etr_buf_list, node) { + /* curr_buf is free for next round */ + if (nd->sysfs_buf =3D=3D curr_buf) { + nd->is_free =3D true; + curr_node =3D nd; + } + + if (!found_free_buf && nd->is_free && nd->sysfs_buf !=3D curr_buf) { + if (nd->reading) + continue; + + picked_node =3D nd; + found_free_buf =3D true; + } + } + + if (found_free_buf) { + curr_node->reading =3D true; + curr_node->pos =3D 0; + drvdata->reading_node =3D curr_node; + drvdata->sysfs_buf =3D picked_node->sysfs_buf; + drvdata->etr_buf =3D picked_node->sysfs_buf; + picked_node->is_free =3D false; + /* Reset irq_cnt for next etr_buf */ + atomic_set(&byte_cntr_data->irq_cnt, 0); + /* Reset rrp and rwp when the system has switched the buffer*/ + ctcu_reset_sysfs_buf(drvdata); + /* Restart the ETR when we find a free buffer */ + if (coresight_get_mode(drvdata->csdev) !=3D CS_MODE_DISABLED) + tmc_etr_enable_hw_after_switching(drvdata); + } + + return found_free_buf; +} + +/* + * ctcu_byte_cntr_get_data() - reads data from the deactivated and filled = buffer. + * The byte-cntr reading work reads data from the deactivated and filled b= uffer. + * The read operation waits for a buffer to become available, either fille= d or + * upon timeout, and then reads trace data from the synced buffer. + */ +static ssize_t ctcu_byte_cntr_get_data(struct tmc_drvdata *drvdata, loff_t= pos, + size_t len, char **bufpp) +{ + struct etr_buf *sysfs_buf =3D drvdata->sysfs_buf; + struct device *dev =3D &drvdata->csdev->dev; + ssize_t actual, size =3D sysfs_buf->size; + struct ctcu_byte_cntr *byte_cntr_data; + struct etr_buf_node *nd, *next; + size_t thresh_val; + atomic_t *irq_cnt; + int ret; + + byte_cntr_data =3D ctcu_get_byte_cntr_data(drvdata); + if (!byte_cntr_data) + return -EINVAL; + + thresh_val =3D byte_cntr_data->thresh_val; + irq_cnt =3D &byte_cntr_data->irq_cnt; + +wait_buffer: + if (!byte_cntr_data->reading_buf) { + ret =3D wait_event_interruptible_timeout(byte_cntr_data->wq, + ((atomic_read(irq_cnt) + 1) * thresh_val >=3D size) || + !byte_cntr_data->enable, + BYTE_CNTR_TIMEOUT); + if (ret < 0) + return ret; + /* + * The current etr_buf is almost full or timeout is triggered, + * so switch the buffer and mark the switched buffer as reading. + */ + if (byte_cntr_data->enable) { + if (!ctcu_byte_cntr_switch_buffer(drvdata, byte_cntr_data)) { + dev_err(dev, "Switch buffer failed for byte-cntr\n"); + return -EINVAL; + } + + byte_cntr_data->reading_buf =3D true; + } else { + if (!drvdata->reading_node) { + list_for_each_entry_safe(nd, next, &drvdata->etr_buf_list, node) { + if (nd->sysfs_buf =3D=3D sysfs_buf) { + nd->pos =3D 0; + drvdata->reading_node =3D nd; + break; + } + } + } + + pos =3D drvdata->reading_node->pos; + actual =3D drvdata->read_ops->get_trace_data(drvdata, pos, len, bufpp); + if (actual > 0) { + byte_cntr_data->total_size +=3D actual; + return actual; + } + + drvdata->reading_node =3D NULL; + + /* Exit byte-cntr reading */ + return -EINVAL; + } + } + + /* Check the status of current etr_buf*/ + if ((atomic_read(irq_cnt) + 1) * thresh_val >=3D size) + /* + * Unlikely to find a free buffer to switch, so just disable + * the ETR for a while. + */ + if (!ctcu_byte_cntr_switch_buffer(drvdata, byte_cntr_data)) + dev_info(dev, "No available buffer to store data, disable ETR\n"); + + pos =3D drvdata->reading_node->pos; + actual =3D drvdata->read_ops->get_trace_data(drvdata, pos, len, bufpp); + if (actual =3D=3D 0) { + /* Reading work for marked buffer has finished, reset flags */ + drvdata->reading_node->reading =3D false; + byte_cntr_data->reading_buf =3D false; + drvdata->reading_node =3D NULL; + + /* Nothing in the buffer, wait for next buffer to be filled */ + goto wait_buffer; + } + byte_cntr_data->total_size +=3D actual; + + return actual; +} + +static int ctcu_read_prepare_byte_cntr(struct tmc_drvdata *drvdata) +{ + struct ctcu_byte_cntr *byte_cntr_data; + unsigned long flags; + int ret =3D 0; + + /* config types are set a boot time and never change */ + if (WARN_ON_ONCE(drvdata->config_type !=3D TMC_CONFIG_TYPE_ETR)) + return -EINVAL; + + byte_cntr_data =3D ctcu_get_byte_cntr_data(drvdata); + if (!byte_cntr_data) + return -EINVAL; + + /* + * The threshold value must not exceed the buffer size. + * A margin should be maintained between the two values to account + * for the time gap between the interrupt and buffer switching. + */ + if (byte_cntr_data->thresh_val + SZ_16K >=3D drvdata->size) { + dev_err(&drvdata->csdev->dev, "The threshold value is too large\n"); + return -EINVAL; + } + + raw_spin_lock_irqsave(&drvdata->spinlock, flags); + if (byte_cntr_data->reading) { + ret =3D -EBUSY; + goto out_unlock; + } + + byte_cntr_data->reading =3D true; + raw_spin_unlock_irqrestore(&drvdata->spinlock, flags); + /* Insert current sysfs_buf into the list */ + ret =3D tmc_create_etr_buf_node(drvdata, drvdata->sysfs_buf); + if (!ret) { + /* + * Add one more sysfs_buf for byte-cntr function, byte-cntr always reads + * the data from the buffer which has been synced. Switch the buffer when + * the used buffer is nearly full. The used buffer will be synced and ma= de + * available for reading before switch. + */ + ret =3D tmc_create_etr_buf_node(drvdata, NULL); + if (ret) { + dev_err(&drvdata->csdev->dev, "Failed to create etr_buf_node\n"); + tmc_clean_etr_buf_list(drvdata); + byte_cntr_data->reading =3D false; + goto out; + } + } + + raw_spin_lock_irqsave(&drvdata->spinlock, flags); + atomic_set(&byte_cntr_data->irq_cnt, 0); + enable_irq(byte_cntr_data->irq_num); + enable_irq_wake(byte_cntr_data->irq_num); + byte_cntr_data->total_size =3D 0; + +out_unlock: + raw_spin_unlock_irqrestore(&drvdata->spinlock, flags); + +out: + return ret; +} + +static int ctcu_read_unprepare_byte_cntr(struct tmc_drvdata *drvdata) +{ + struct device *dev =3D &drvdata->csdev->dev; + struct ctcu_byte_cntr *byte_cntr_data; + + byte_cntr_data =3D ctcu_get_byte_cntr_data(drvdata); + if (!byte_cntr_data) + return -EINVAL; + + guard(raw_spinlock_irqsave)(&byte_cntr_data->spin_lock); + disable_irq_wake(byte_cntr_data->irq_num); + disable_irq(byte_cntr_data->irq_num); + byte_cntr_data->reading =3D false; + tmc_clean_etr_buf_list(drvdata); + dev_dbg(dev, "send data total size:%llu bytes\n", byte_cntr_data->total_s= ize); + + return 0; +} + +static const struct tmc_read_ops byte_cntr_read_ops =3D { + .read_prepare =3D ctcu_read_prepare_byte_cntr, + .read_unprepare =3D ctcu_read_unprepare_byte_cntr, + .get_trace_data =3D ctcu_byte_cntr_get_data, +}; + +void ctcu_byte_cntr_init(struct device *dev, struct ctcu_drvdata *drvdata,= int etr_num) +{ + struct ctcu_byte_cntr *byte_cntr_data; + struct device_node *nd =3D dev->of_node; + int irq_num, ret, i; + + drvdata->byte_cntr_read_ops =3D &byte_cntr_read_ops; + for (i =3D 0; i < etr_num; i++) { + byte_cntr_data =3D &drvdata->byte_cntr_data[i]; + irq_num =3D of_irq_get_byname(nd, byte_cntr_data->irq_name); + if (irq_num < 0) { + dev_err(dev, "Failed to get IRQ from DT for %s\n", + byte_cntr_data->irq_name); + continue; + } + + ret =3D devm_request_irq(dev, irq_num, byte_cntr_handler, + IRQF_TRIGGER_RISING | IRQF_SHARED, + dev_name(dev), byte_cntr_data); + if (ret) { + dev_err(dev, "Failed to register IRQ for %s\n", + byte_cntr_data->irq_name); + continue; + } + + byte_cntr_data->irq_num =3D irq_num; + disable_irq(byte_cntr_data->irq_num); + init_waitqueue_head(&byte_cntr_data->wq); + } +} diff --git a/drivers/hwtracing/coresight/coresight-ctcu-core.c b/drivers/hw= tracing/coresight/coresight-ctcu-core.c index 3bdedf041390..8fc08e42187e 100644 --- a/drivers/hwtracing/coresight/coresight-ctcu-core.c +++ b/drivers/hwtracing/coresight/coresight-ctcu-core.c @@ -15,6 +15,7 @@ #include #include #include +#include =20 #include "coresight-ctcu.h" #include "coresight-priv.h" @@ -45,17 +46,23 @@ DEFINE_CORESIGHT_DEVLIST(ctcu_devs, "ctcu"); =20 #define CTCU_ATID_REG_BIT(traceid) (traceid % 32) #define CTCU_ATID_REG_SIZE 0x10 +#define CTCU_ETR0_IRQCTRL 0x6c +#define CTCU_ETR1_IRQCTRL 0x70 #define CTCU_ETR0_ATID0 0xf8 #define CTCU_ETR1_ATID0 0x108 =20 static const struct ctcu_etr_config sa8775p_etr_cfgs[] =3D { { - .atid_offset =3D CTCU_ETR0_ATID0, - .port_num =3D 0, + .atid_offset =3D CTCU_ETR0_ATID0, + .irq_ctrl_offset =3D CTCU_ETR0_IRQCTRL, + .irq_name =3D "etr0", + .port_num =3D 0, }, { - .atid_offset =3D CTCU_ETR1_ATID0, - .port_num =3D 1, + .atid_offset =3D CTCU_ETR1_ATID0, + .irq_ctrl_offset =3D CTCU_ETR1_IRQCTRL, + .irq_name =3D "etr1", + .port_num =3D 1, }, }; =20 @@ -64,6 +71,76 @@ static const struct ctcu_config sa8775p_cfgs =3D { .num_etr_config =3D ARRAY_SIZE(sa8775p_etr_cfgs), }; =20 +static void ctcu_program_register(struct ctcu_drvdata *drvdata, u32 val, u= 32 offset) +{ + CS_UNLOCK(drvdata->base); + ctcu_writel(drvdata, val, offset); + CS_LOCK(drvdata->base); +} + +static ssize_t irq_threshold_show(struct device *dev, struct device_attrib= ute *attr, + char *buf) +{ + struct ctcu_drvdata *drvdata =3D dev_get_drvdata(dev->parent); + int i, len =3D 0; + + for (i =3D 0; i < ETR_MAX_NUM; i++) { + if (drvdata->byte_cntr_data[i].irq_ctrl_offset) + len +=3D scnprintf(buf + len, PAGE_SIZE - len, "%u ", + drvdata->byte_cntr_data[i].thresh_val); + } + + len +=3D scnprintf(buf + len, PAGE_SIZE - len, "\n"); + + return len; +} + +/* Program a valid value into IRQCTRL register will enable byte-cntr inter= rupt */ +static ssize_t irq_threshold_store(struct device *dev, struct device_attri= bute *attr, + const char *buf, size_t size) +{ + struct ctcu_drvdata *drvdata =3D dev_get_drvdata(dev->parent); + u32 thresh_vals[ETR_MAX_NUM] =3D { 0 }; + u32 irq_ctrl_offset; + int num, i; + + num =3D sscanf(buf, "%i %i", &thresh_vals[0], &thresh_vals[1]); + if (num <=3D 0 || num > ETR_MAX_NUM) + return -EINVAL; + + /* Threshold 0 disables the interruption. */ + guard(raw_spinlock_irqsave)(&drvdata->spin_lock); + for (i =3D 0; i < num; i++) { + /* A small threshold will result in a large number of interruptions */ + if (thresh_vals[i] && thresh_vals[i] < SZ_4K) + return -EINVAL; + + if (drvdata->byte_cntr_data[i].irq_ctrl_offset) { + drvdata->byte_cntr_data[i].thresh_val =3D thresh_vals[i]; + irq_ctrl_offset =3D drvdata->byte_cntr_data[i].irq_ctrl_offset; + /* A one value for IRQCTRL register represents 8 bytes */ + ctcu_program_register(drvdata, thresh_vals[i] / 8, irq_ctrl_offset); + } + } + + return size; +} +static DEVICE_ATTR_RW(irq_threshold); + +static struct attribute *ctcu_attrs[] =3D { + &dev_attr_irq_threshold.attr, + NULL, +}; + +static struct attribute_group ctcu_attr_grp =3D { + .attrs =3D ctcu_attrs, +}; + +static const struct attribute_group *ctcu_attr_grps[] =3D { + &ctcu_attr_grp, + NULL, +}; + static void ctcu_program_atid_register(struct ctcu_drvdata *drvdata, u32 r= eg_offset, u8 bit, bool enable) { @@ -143,6 +220,8 @@ static int ctcu_enable(struct coresight_device *csdev, = enum cs_mode mode, void * { struct coresight_path *path =3D (struct coresight_path *)data; =20 + ctcu_byte_cntr_start(csdev, path); + return ctcu_set_etr_traceid(csdev, path, true); } =20 @@ -150,6 +229,8 @@ static int ctcu_disable(struct coresight_device *csdev,= void *data) { struct coresight_path *path =3D (struct coresight_path *)data; =20 + ctcu_byte_cntr_stop(csdev, path); + return ctcu_set_etr_traceid(csdev, path, false); } =20 @@ -200,7 +281,11 @@ static int ctcu_probe(struct platform_device *pdev) for (i =3D 0; i < cfgs->num_etr_config; i++) { etr_cfg =3D &cfgs->etr_cfgs[i]; drvdata->atid_offset[i] =3D etr_cfg->atid_offset; + drvdata->byte_cntr_data[i].irq_name =3D etr_cfg->irq_name; + drvdata->byte_cntr_data[i].irq_ctrl_offset =3D + etr_cfg->irq_ctrl_offset; } + ctcu_byte_cntr_init(dev, drvdata, cfgs->num_etr_config); } } =20 @@ -212,6 +297,7 @@ static int ctcu_probe(struct platform_device *pdev) desc.subtype.helper_subtype =3D CORESIGHT_DEV_SUBTYPE_HELPER_CTCU; desc.pdata =3D pdata; desc.dev =3D dev; + desc.groups =3D ctcu_attr_grps; desc.ops =3D &ctcu_ops; desc.access =3D CSDEV_ACCESS_IOMEM(base); =20 diff --git a/drivers/hwtracing/coresight/coresight-ctcu.h b/drivers/hwtraci= ng/coresight/coresight-ctcu.h index e9594c38dd91..894e375277c4 100644 --- a/drivers/hwtracing/coresight/coresight-ctcu.h +++ b/drivers/hwtracing/coresight/coresight-ctcu.h @@ -5,19 +5,28 @@ =20 #ifndef _CORESIGHT_CTCU_H #define _CORESIGHT_CTCU_H + +#include #include "coresight-trace-id.h" +#include "coresight-tmc.h" =20 /* Maximum number of supported ETR devices for a single CTCU. */ #define ETR_MAX_NUM 2 =20 +#define BYTE_CNTR_TIMEOUT (5 * HZ) + /** * struct ctcu_etr_config * @atid_offset: offset to the ATID0 Register. - * @port_num: in-port number of CTCU device that connected to ETR. + * @port_num: in-port number of the CTCU device that connected to ETR. + * @irq_ctrl_offset: offset to the BYTECNTRVAL register. + * @irq_name: IRQ name in dt node. */ struct ctcu_etr_config { const u32 atid_offset; const u32 port_num; + const u32 irq_ctrl_offset; + const char *irq_name; }; =20 struct ctcu_config { @@ -25,15 +34,50 @@ struct ctcu_config { int num_etr_config; }; =20 -struct ctcu_drvdata { - void __iomem *base; - struct clk *apb_clk; - struct device *dev; - struct coresight_device *csdev; +/** + * struct ctcu_byte_cntr + * @enable: indicates that byte_cntr function is enabled or not. + * @reading: indicates that byte-cntr reading is started. + * @reading_buf: indicates that byte-cntr is reading data from the buffer. + * @thresh_val: threshold to trigger a interruption. + * @total_size: total size of transferred data. + * @irq_num: allocated number of the IRQ. + * @irq_cnt: IRQ count number for triggered interruptions. + * @wq: waitqueue for reading data from ETR buffer. + * @spin_lock: spinlock of byte_cntr_data. + * @irq_ctrl_offset: offset to the BYTECNTVAL Register. + * @irq_name: IRQ name defined in DT. + */ +struct ctcu_byte_cntr { + bool enable; + bool reading; + bool reading_buf; + u32 thresh_val; + u64 total_size; + int irq_num; + atomic_t irq_cnt; + wait_queue_head_t wq; raw_spinlock_t spin_lock; - u32 atid_offset[ETR_MAX_NUM]; + u32 irq_ctrl_offset; + const char *irq_name; +}; + +struct ctcu_drvdata { + void __iomem *base; + struct clk *apb_clk; + struct device *dev; + struct coresight_device *csdev; + struct ctcu_byte_cntr byte_cntr_data[ETR_MAX_NUM]; + raw_spinlock_t spin_lock; + u32 atid_offset[ETR_MAX_NUM]; /* refcnt for each traceid of each sink */ - u8 traceid_refcnt[ETR_MAX_NUM][CORESIGHT_TRACE_ID_RES_TOP]; + u8 traceid_refcnt[ETR_MAX_NUM][CORESIGHT_TRACE_ID_RES_TOP]; + const struct tmc_read_ops *byte_cntr_read_ops; }; =20 +/* Byte-cntr functions */ +void ctcu_byte_cntr_start(struct coresight_device *csdev, struct coresight= _path *path); +void ctcu_byte_cntr_stop(struct coresight_device *csdev, struct coresight_= path *path); +void ctcu_byte_cntr_init(struct device *dev, struct ctcu_drvdata *drvdata,= int port_num); + #endif diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtr= acing/coresight/coresight-tmc-etr.c index e8ecb3e087ab..c2a4ac3e37b3 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c @@ -1117,6 +1117,12 @@ static int __tmc_etr_enable_hw(struct tmc_drvdata *d= rvdata) return rc; } =20 +int tmc_etr_enable_hw_after_switching(struct tmc_drvdata *drvdata) +{ + return __tmc_etr_enable_hw(drvdata); +} +EXPORT_SYMBOL_GPL(tmc_etr_enable_hw_after_switching); + static int tmc_etr_enable_hw(struct tmc_drvdata *drvdata, struct etr_buf *etr_buf) { @@ -1163,6 +1169,10 @@ ssize_t tmc_etr_get_sysfs_trace(struct tmc_drvdata *= drvdata, ssize_t actual =3D len; struct etr_buf *etr_buf =3D drvdata->sysfs_buf; =20 + /* Reading the buffer from the buf_node if it exists*/ + if (drvdata->reading_node) + etr_buf =3D drvdata->reading_node->sysfs_buf; + if (pos + actual > etr_buf->len) actual =3D etr_buf->len - pos; if (actual <=3D 0) @@ -1226,6 +1236,12 @@ static void __tmc_etr_disable_hw(struct tmc_drvdata = *drvdata) =20 } =20 +void tmc_etr_disable_hw_before_switching(struct tmc_drvdata *drvdata) +{ + __tmc_etr_disable_hw(drvdata); +} +EXPORT_SYMBOL_GPL(tmc_etr_disable_hw_before_switching); + void tmc_etr_disable_hw(struct tmc_drvdata *drvdata) { __tmc_etr_disable_hw(drvdata); diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracin= g/coresight/coresight-tmc.h index 2ad8e288c94b..6f42cd392e1b 100644 --- a/drivers/hwtracing/coresight/coresight-tmc.h +++ b/drivers/hwtracing/coresight/coresight-tmc.h @@ -480,5 +480,7 @@ struct etr_buf *tmc_etr_get_buffer(struct coresight_dev= ice *csdev, extern const struct attribute_group coresight_etr_group; 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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-23fa48fd29dsm33641435ad.176.2025.07.25.03.08.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Jul 2025 03:08:49 -0700 (PDT) From: Jie Gan To: Suzuki K Poulose , Mike Leach , James Clark , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Alexander Shishkin , Tingwei Zhang , Jinlong Mao Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, Jie Gan Subject: [PATCH v4 08/10] coresight: add a new function in helper_ops Date: Fri, 25 Jul 2025 18:08:04 +0800 Message-Id: <20250725100806.1157-9-jie.gan@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250725100806.1157-1-jie.gan@oss.qualcomm.com> References: <20250725100806.1157-1-jie.gan@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: AisGdSvUuKa-7bn6xk-xLm6WQZGeq8V4 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzI1MDA4NSBTYWx0ZWRfXzDFfEH+1T29e rfsGKJwFh4h8KYicxGFfiMDNx9X5wj4DrsD6j3PT9gXApHlch2Wg8iSArq5lZdz/O/2Le5uJrCw UajxDyIQSFFjUrLAZBp6YglYENPUONZXRZKinVjqwt/8tYlSD+TfS3meJnRsctvGhoyJkB6qmkG lrl0eZxAFKoVd00zXaYesycZO++bU0wgqPcibtpU948d6/PPOvd+6CROj2HobK5201ejLxmU8bv h8AJMApzkQBPv8BNA7xIYvrQGI+HhBmqAt0zBIegBJ2EVk2oXhtfZEhwO7/jmmtv/ecEZ4QdlN0 qOpBUBi6jzZNhTEusVECa6j5RCYExWWV4HSIo/94qGupn1eYg/YJFnn7+1B/li4tAV0s4Pwt0np WWG9eeig4mHHl0ZghAY5O5UfkwEcfhgMygjrdBoz2srJubZBRNZhHF6fphKRmvlNOZ0nDtDp X-Proofpoint-GUID: AisGdSvUuKa-7bn6xk-xLm6WQZGeq8V4 X-Authority-Analysis: v=2.4 cv=S8bZwJsP c=1 sm=1 tr=0 ts=688357b4 cx=c_pps a=cmESyDAEBpBGqyK7t0alAg==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=Wb1JkmetP80A:10 a=EUspDBNiAAAA:8 a=vagHEfzm_U2ljPniXDUA:9 a=0bXxn9q0MV6snEgNplNhOjQmxlI=:19 a=1OuFwYUASf3TG4hYMiVC:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-25_02,2025-07-24_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 lowpriorityscore=0 mlxlogscore=999 bulkscore=0 impostorscore=0 spamscore=0 malwarescore=0 adultscore=0 suspectscore=0 phishscore=0 priorityscore=1501 mlxscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507250085 Content-Type: text/plain; charset="utf-8" Add a new function to identifiy whether the byte-cntr function is enabled or not in helper_ops. The byte-cntr's read_ops is expected if the byte-cntr is enabled when the user try to read trace data via sysfs node. Signed-off-by: Jie Gan --- .../hwtracing/coresight/coresight-ctcu-core.c | 35 +++++++++++++++++++ include/linux/coresight.h | 3 ++ 2 files changed, 38 insertions(+) diff --git a/drivers/hwtracing/coresight/coresight-ctcu-core.c b/drivers/hw= tracing/coresight/coresight-ctcu-core.c index 8fc08e42187e..dec911980939 100644 --- a/drivers/hwtracing/coresight/coresight-ctcu-core.c +++ b/drivers/hwtracing/coresight/coresight-ctcu-core.c @@ -234,9 +234,44 @@ static int ctcu_disable(struct coresight_device *csdev= , void *data) return ctcu_set_etr_traceid(csdev, path, false); } =20 +static bool ctcu_qcom_byte_cntr_in_use(struct coresight_device *csdev, + void **data) +{ + struct ctcu_byte_cntr *byte_cntr_data; + struct coresight_device *helper; + struct ctcu_drvdata *drvdata; + int port; + + if (!csdev) + return false; + + helper =3D coresight_get_helper(csdev, CORESIGHT_DEV_SUBTYPE_HELPER_CTCU); + if (!helper) + return false; + + port =3D coresight_get_in_port_dest(csdev, helper); + if (port < 0) + return false; + + drvdata =3D dev_get_drvdata(helper->dev.parent); + /* Something wrong when initialize byte_cntr_read_ops */ + if (!drvdata->byte_cntr_read_ops) + return false; + + byte_cntr_data =3D &drvdata->byte_cntr_data[port]; + /* Return the pointer of the ctcu_drvdata if byte-cntr has enabled */ + if (byte_cntr_data && byte_cntr_data->thresh_val) { + *data =3D (void *)drvdata->byte_cntr_read_ops; + return true; + } + + return false; +} + static const struct coresight_ops_helper ctcu_helper_ops =3D { .enable =3D ctcu_enable, .disable =3D ctcu_disable, + .qcom_byte_cntr_in_use =3D ctcu_qcom_byte_cntr_in_use, }; =20 static const struct coresight_ops ctcu_ops =3D { diff --git a/include/linux/coresight.h b/include/linux/coresight.h index 4ac65c68bbf4..b5f052854b08 100644 --- a/include/linux/coresight.h +++ b/include/linux/coresight.h @@ -419,11 +419,14 @@ struct coresight_ops_source { * * @enable : Enable the device * @disable : Disable the device + * @qcom_byte_cntr_in_use: check whether the byte-cntr is enabled. */ struct coresight_ops_helper { int (*enable)(struct coresight_device *csdev, enum cs_mode mode, void *data); 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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-23fa48fd29dsm33641435ad.176.2025.07.25.03.08.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Jul 2025 03:08:53 -0700 (PDT) From: Jie Gan To: Suzuki K Poulose , Mike Leach , James Clark , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Alexander Shishkin , Tingwei Zhang , Jinlong Mao Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, Jie Gan Subject: [PATCH v4 09/10] coresight: tmc: integrate byte-cntr's read_ops with sysfs file_ops Date: Fri, 25 Jul 2025 18:08:05 +0800 Message-Id: <20250725100806.1157-10-jie.gan@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250725100806.1157-1-jie.gan@oss.qualcomm.com> References: <20250725100806.1157-1-jie.gan@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Authority-Analysis: v=2.4 cv=BMKzrEQG c=1 sm=1 tr=0 ts=688357b8 cx=c_pps a=oF/VQ+ItUULfLr/lQ2/icg==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=Wb1JkmetP80A:10 a=EUspDBNiAAAA:8 a=Zpm-vmsZ5HaS-asNi4kA:9 a=3WC7DwWrALyhR5TkjVHa:22 X-Proofpoint-ORIG-GUID: PBNSwD8bB8JDI0kRYFZS02VRoKgYI3GL X-Proofpoint-GUID: PBNSwD8bB8JDI0kRYFZS02VRoKgYI3GL X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzI1MDA4NSBTYWx0ZWRfXy9wEyhAzhLt0 k9LZ6MgS8z4qLocgha4ZWXceQKEVrz5uGAtnl0a+Y+Mk4gj1OsaZ9LXX0GaLlLg0kyxmRRStjxB mlNhxTCK4PZYHu9QnlZY7AnMR10jYeUrEO12pxnyPPs+jtiJWwpl1aBayD28NaUs58to2IlPmCa OAPtpwxJum/B9yXlJF9SWyk/RUHRu1ktDamrusOtY7OleIoPudxly4NIlCF3FQYBfQvejnl023Z z+sdUZ11B6nH2ydrigLA/mD5sIjGFGhez1AzUc3KcDNz8NMNrHLx9imqh0hIqoHWNW78q2yImRD mOfDxWLhkDCTLKUQ75MJG4JYlnZQAbD5rNeBFsC+x04T/4JfWoOEonVWyJr/q/1gsGq+lQuTB64 mwZ53hVbEYpzqflZSY44HLcr4d91Kq2hlCisAOv3ZXEPalT+ILdrZRRweA/YdVbXZepk4yhE X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-25_02,2025-07-24_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 mlxscore=0 spamscore=0 impostorscore=0 priorityscore=1501 bulkscore=0 malwarescore=0 adultscore=0 phishscore=0 suspectscore=0 mlxlogscore=999 clxscore=1015 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507250085 Content-Type: text/plain; charset="utf-8" Add code logic to invoke byte-cntr's read_ops if the byte-cntr is enabled. Signed-off-by: Jie Gan --- .../hwtracing/coresight/coresight-tmc-core.c | 48 ++++++++++++++++++- 1 file changed, 47 insertions(+), 1 deletion(-) diff --git a/drivers/hwtracing/coresight/coresight-tmc-core.c b/drivers/hwt= racing/coresight/coresight-tmc-core.c index f668047c5df4..671ae4542f6a 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-core.c +++ b/drivers/hwtracing/coresight/coresight-tmc-core.c @@ -228,15 +228,41 @@ static int tmc_prepare_crashdata(struct tmc_drvdata *= drvdata) return 0; } =20 +static const struct tmc_read_ops *tmc_qcom_byte_cntr_in_use(struct tmc_drv= data *drvdata, + bool *in_use) +{ + struct tmc_read_ops *byte_cntr_read_ops; + struct coresight_device *helper; + + helper =3D coresight_get_helper(drvdata->csdev, CORESIGHT_DEV_SUBTYPE_HEL= PER_CTCU); + if (helper) + *in_use =3D helper_ops(helper)->qcom_byte_cntr_in_use(drvdata->csdev, + (void **)&byte_cntr_read_ops); + + if (*in_use) + return byte_cntr_read_ops; + + return NULL; +} + static int tmc_read_prepare(struct tmc_drvdata *drvdata) { + const struct tmc_read_ops *byte_cntr_read_ops; + bool in_use =3D false; int ret =3D 0; =20 + byte_cntr_read_ops =3D tmc_qcom_byte_cntr_in_use(drvdata, &in_use); + if (in_use) { + ret =3D byte_cntr_read_ops->read_prepare(drvdata); + goto out; + } + if (drvdata->read_ops) ret =3D drvdata->read_ops->read_prepare(drvdata); else ret =3D -EINVAL; =20 +out: if (!ret) dev_dbg(&drvdata->csdev->dev, "TMC read start\n"); =20 @@ -245,13 +271,22 @@ static int tmc_read_prepare(struct tmc_drvdata *drvda= ta) =20 static int tmc_read_unprepare(struct tmc_drvdata *drvdata) { + const struct tmc_read_ops *byte_cntr_read_ops; + bool in_use =3D false; int ret =3D 0; =20 + byte_cntr_read_ops =3D tmc_qcom_byte_cntr_in_use(drvdata, &in_use); + if (in_use) { + ret =3D byte_cntr_read_ops->read_unprepare(drvdata); + goto out; + } + if (drvdata->read_ops) ret =3D drvdata->read_ops->read_unprepare(drvdata); else ret =3D -EINVAL; =20 +out: if (!ret) dev_dbg(&drvdata->csdev->dev, "TMC read end\n"); =20 @@ -277,6 +312,13 @@ static int tmc_open(struct inode *inode, struct file *= file) static ssize_t tmc_get_sysfs_trace(struct tmc_drvdata *drvdata, loff_t pos= , size_t len, char **bufpp) { + const struct tmc_read_ops *byte_cntr_read_ops; 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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-23fa48fd29dsm33641435ad.176.2025.07.25.03.08.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Jul 2025 03:08:58 -0700 (PDT) From: Jie Gan To: Suzuki K Poulose , Mike Leach , James Clark , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Alexander Shishkin , Tingwei Zhang , Jinlong Mao Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, Jie Gan , Konrad Dybcio Subject: [PATCH v4 10/10] arm64: dts: qcom: sa8775p: Add interrupts to CTCU device Date: Fri, 25 Jul 2025 18:08:06 +0800 Message-Id: <20250725100806.1157-11-jie.gan@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250725100806.1157-1-jie.gan@oss.qualcomm.com> References: <20250725100806.1157-1-jie.gan@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-GUID: cPVPew-os9MqtXN3CsoW0kEKvDUWKVeV X-Proofpoint-ORIG-GUID: cPVPew-os9MqtXN3CsoW0kEKvDUWKVeV X-Authority-Analysis: v=2.4 cv=QNtoRhLL c=1 sm=1 tr=0 ts=688357bc cx=c_pps a=IZJwPbhc+fLeJZngyXXI0A==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=Wb1JkmetP80A:10 a=EUspDBNiAAAA:8 a=gBkj9RZkAcI1HbXH1KoA:9 a=uG9DUKGECoFWVXl0Dc02:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzI1MDA4NiBTYWx0ZWRfX5vXfT+SRVyAw VAVKkl+19VpXWMROfY484covGLNGEY3yk9yHu2YkAFeze/PI4iO9GSAwWyK7Kih8MrSk5+udtJJ C72KeuXS6I4dUFPEMoOStT6Kqi7eP3CnVJM41Yq80r8V7b/huMf2dAVbR1NKx27SxDw0Ua6sFvV PCRRqLMMiirscFMfsZx3yZp9ZhgcIBw8Its3xaPA0Cvs4fYpOPc9pFeQPvQyD8OlAB3ooP8dACl zxQIgPfbCav4RsmgvQM/0NwMpuLGAA+Bj6rTI94pUcQJA1XIXXIWvnC6RMTl/jAYwciYrbZ09CG 5fh9gMv3IVgr/8AwbbkZKmjSD9Nvr8b8AqgzoHPAt7oDj70ORKpBP6G7q2McW4310Hzvell5/rJ vXNPKvpDkv36FbKsVggMIaMAZRFS9juGmIc70PctrqOX+wiRrTXN8rwestFE8jarCjLxU48W X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-25_03,2025-07-24_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 mlxlogscore=824 bulkscore=0 mlxscore=0 suspectscore=0 spamscore=0 malwarescore=0 impostorscore=0 priorityscore=1501 lowpriorityscore=0 clxscore=1015 adultscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507250086 Content-Type: text/plain; charset="utf-8" Add interrupts to enable byte-cntr function for TMC ETR devices. Reviewed-by: Konrad Dybcio Signed-off-by: Jie Gan --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qc= om/sa8775p.dtsi index 9997a29901f5..4e6684a6d38e 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -2762,6 +2762,11 @@ ctcu@4001000 { clocks =3D <&aoss_qmp>; clock-names =3D "apb"; =20 + interrupts =3D , + ; + interrupt-names =3D "etr0", + "etr1"; + in-ports { #address-cells =3D <1>; #size-cells =3D <0>; --=20 2.34.1