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([178.197.203.90]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3b76fc6d1b0sm4457094f8f.18.2025.07.25.02.03.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Jul 2025 02:03:57 -0700 (PDT) From: Krzysztof Kozlowski To: Daniel Lezcano , Thomas Gleixner , Krzysztof Kozlowski , Alim Akhtar , Will McVicker , Youngmin Nam , Donghoon Yu , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org Cc: Krzysztof Kozlowski Subject: [PATCH] clocksource/drivers/exynos_mct: Revert commits causing section mismatches Date: Fri, 25 Jul 2025 11:03:50 +0200 Message-ID: <20250725090349.87730-2-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.48.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=6066; i=krzysztof.kozlowski@linaro.org; h=from:subject; bh=6vM1EJPOw6Q4Qtlb27Cb82oUvYEiD6W/XiM1RMs35fE=; b=owEBbQKS/ZANAwAKAcE3ZuaGi4PXAcsmYgBog0h1G5Uk9Pte6K2erF5TqunuTTBgTDpGsrvV8 TEOHz0s63OJAjMEAAEKAB0WIQTd0mIoPREbIztuuKjBN2bmhouD1wUCaINIdQAKCRDBN2bmhouD 1wWRD/98MncWXJ487P4kJKVuFRECgj7W6JrPbTWD1EFBGsiBhmOGCRM2RSyKQZXGViRmQsThRHa g+al4JPMNu8ZgRgoH3scYChiRxjmHMa6WjuNpLtX5V2RoH3KwZciSSpvxXJgeakJ77f5NpzwsVx rzQwovhhoLN4sbRTX5R4a+Qc7aO/U0ClyYZjPFFPc44D6XBocWK/4q3Y21WGmSXSOGbIWCwNc5/ EBZ1xXzPPQ2PyEkLQiLgkWpkoHCe+09gm0M/ACxlRm4mdiX9uNJ+4qTjSeIl04LnNX3qNQ+Lriv DLeJuuFv1Nqm7zo96pkaLRwt5itojLI/iMHiHwBjERAXVn3atyB7tsj/DZOp1hB9LXtzruJ5Kup 3/Hk+iDz2QXx8qjyvdK1r75tEg3nBBCCjLmEGbcGHHaSeU26N4auuX1FQTCqJXvV+hoTDNNhAtH ufJdEUHbyKyWQr6RyiJM3qRDjne0af36YX5iQcRJL+SAuw55jf6ITi3yIRqI/ygPC4uHNUOVOVw aU+/QY00QV0d0rrJvObAsiuj4pgMjRUgVGHLcq+J2WzDCnnr0mtqNVRGw2gmlLAN/0ZvsC7Z1PG Km9rBuMIgYmOBCqKlj/X7w5dfahbhLGiavdVXuI03ZtzHJeS5OLteenkWBtg5k3EgDcwSnrx92w Lji1FxNr7fmWU5w== X-Developer-Key: i=krzysztof.kozlowski@linaro.org; a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Commit 5d86e479193b ("clocksource/drivers/exynos_mct: Add module support") introduced section mismatch failures. Commit 7e477e9c4eb4 ("clocksource/drivers/exynos_mct: Fix section mismatch from the module conversion") replaced these to other section mismatch failures: WARNING: modpost: vmlinux: section mismatch in reference: mct_init_dt+0x1= 64 (section: .text) -> register_current_timer_delay (section: .init.text) WARNING: modpost: vmlinux: section mismatch in reference: mct_init_dt+0x2= 0c (section: .text) -> register_current_timer_delay (section: .init.text) ERROR: modpost: Section mismatches detected. No progress on real fixing of these happened (intermediary fix was still not tested), so revert both commits till the work is prepared correctly. Fixes: 7e477e9c4eb4 ("clocksource/drivers/exynos_mct: Fix section mismatch = from the module conversion") Fixes: 5d86e479193b ("clocksource/drivers/exynos_mct: Add module support") Signed-off-by: Krzysztof Kozlowski Acked-by: Daniel Lezcano --- First build failure: https://krzk.eu/#/builders/12/builds/3350 --- drivers/clocksource/Kconfig | 3 +- drivers/clocksource/exynos_mct.c | 51 ++++++-------------------------- 2 files changed, 10 insertions(+), 44 deletions(-) diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig index d657c8ddc96b..645f517a1ac2 100644 --- a/drivers/clocksource/Kconfig +++ b/drivers/clocksource/Kconfig @@ -451,8 +451,7 @@ config ATMEL_TCB_CLKSRC Support for Timer Counter Blocks on Atmel SoCs. =20 config CLKSRC_EXYNOS_MCT - tristate "Exynos multi core timer driver" if ARM64 - default y if ARCH_EXYNOS || COMPILE_TEST + bool "Exynos multi core timer driver" if COMPILE_TEST depends on ARM || ARM64 depends on ARCH_ARTPEC || ARCH_EXYNOS || COMPILE_TEST help diff --git a/drivers/clocksource/exynos_mct.c b/drivers/clocksource/exynos_= mct.c index 80d263ee046d..62febeb4e1de 100644 --- a/drivers/clocksource/exynos_mct.c +++ b/drivers/clocksource/exynos_mct.c @@ -15,11 +15,9 @@ #include #include #include -#include #include #include #include -#include #include #include =20 @@ -219,7 +217,6 @@ static struct clocksource mct_frc =3D { .mask =3D CLOCKSOURCE_MASK(32), .flags =3D CLOCK_SOURCE_IS_CONTINUOUS, .resume =3D exynos4_frc_resume, - .owner =3D THIS_MODULE, }; =20 /* @@ -244,7 +241,7 @@ static cycles_t exynos4_read_current_timer(void) } #endif =20 -static int exynos4_clocksource_init(bool frc_shared) +static int __init exynos4_clocksource_init(bool frc_shared) { /* * When the frc is shared, the main processor should have already @@ -339,7 +336,6 @@ static struct clock_event_device mct_comp_device =3D { .set_state_oneshot =3D mct_set_state_shutdown, .set_state_oneshot_stopped =3D mct_set_state_shutdown, .tick_resume =3D mct_set_state_shutdown, - .owner =3D THIS_MODULE, }; =20 static irqreturn_t exynos4_mct_comp_isr(int irq, void *dev_id) @@ -480,7 +476,6 @@ static int exynos4_mct_starting_cpu(unsigned int cpu) evt->features =3D CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERCPU; evt->rating =3D MCT_CLKEVENTS_RATING; - evt->owner =3D THIS_MODULE; =20 exynos4_mct_write(TICK_BASE_CNT, mevt->base + MCT_L_TCNTB_OFFSET); =20 @@ -516,7 +511,7 @@ static int exynos4_mct_dying_cpu(unsigned int cpu) return 0; } =20 -static int exynos4_timer_resources(struct device_node *np) +static int __init exynos4_timer_resources(struct device_node *np) { struct clk *mct_clk, *tick_clk; =20 @@ -544,7 +539,7 @@ static int exynos4_timer_resources(struct device_node *= np) * @local_idx: array mapping CPU numbers to local timer indices * @nr_local: size of @local_idx array */ -static int exynos4_timer_interrupts(struct device_node *np, +static int __init exynos4_timer_interrupts(struct device_node *np, unsigned int int_type, const u32 *local_idx, size_t nr_local) @@ -657,7 +652,7 @@ static int exynos4_timer_interrupts(struct device_node = *np, return err; } =20 -static __init_or_module int mct_init_dt(struct device_node *np, unsigned i= nt int_type) +static int __init mct_init_dt(struct device_node *np, unsigned int int_typ= e) { bool frc_shared =3D of_property_read_bool(np, "samsung,frc-shared"); u32 local_idx[MCT_NR_LOCAL] =3D {0}; @@ -705,43 +700,15 @@ static __init_or_module int mct_init_dt(struct device= _node *np, unsigned int int return exynos4_clockevent_init(); } =20 -static __init_or_module int mct_init_spi(struct device_node *np) + +static int __init mct_init_spi(struct device_node *np) { return mct_init_dt(np, MCT_INT_SPI); } =20 -static __init_or_module int mct_init_ppi(struct device_node *np) +static int __init mct_init_ppi(struct device_node *np) { return mct_init_dt(np, MCT_INT_PPI); } - -static int exynos4_mct_probe(struct platform_device *pdev) -{ - struct device *dev =3D &pdev->dev; - int (*mct_init)(struct device_node *np); - - mct_init =3D of_device_get_match_data(dev); - if (!mct_init) - return -EINVAL; - - return mct_init(dev->of_node); -} - -static const struct of_device_id exynos4_mct_match_table[] =3D { - { .compatible =3D "samsung,exynos4210-mct", .data =3D &mct_init_spi, }, - { .compatible =3D "samsung,exynos4412-mct", .data =3D &mct_init_ppi, }, - {} -}; -MODULE_DEVICE_TABLE(of, exynos4_mct_match_table); - -static struct platform_driver exynos4_mct_driver =3D { - .probe =3D exynos4_mct_probe, - .driver =3D { - .name =3D "exynos-mct", - .of_match_table =3D exynos4_mct_match_table, - }, -}; -module_platform_driver(exynos4_mct_driver); - -MODULE_DESCRIPTION("Exynos Multi Core Timer Driver"); -MODULE_LICENSE("GPL"); +TIMER_OF_DECLARE(exynos4210, "samsung,exynos4210-mct", mct_init_spi); +TIMER_OF_DECLARE(exynos4412, "samsung,exynos4412-mct", mct_init_ppi); --=20 2.48.1