From nobody Mon Oct 6 03:11:19 2025 Received: from mx08-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1F1F42D29CE; Fri, 25 Jul 2025 10:07:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=91.207.212.93 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753438027; cv=none; b=lj/8GBa142LcZr9+Jphya/ZX1b385okD3LkcRtavgPYk1pp62y+jDebSWLujfGJcVf3j9LtvaVRRPMgXFCHQD2NeAh6cktEibLZBNSfSlUcKgogmsWtlxZ2aYkwI7ybTrQIOTh2BPKbmuNLYIX3dPsMeNHOvDc2paYP3H5y8nxg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753438027; c=relaxed/simple; bh=jDv1y3xvNM+4MPGZUqc1WqBh0voHnqR3nukVHTqlDiY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=mFFIpHvGZiCpU8JtgFjgeUsGRalVddxu+Fyu5oib8aT7TbHqdxW9CWfee2FdoZg1yzDeCe/cbNx0n6RckkZ3oUiyc5x5hzIswTpLUAVMPVzwCeTMkaEfHWZtuGqp/zkkIw7D0PdTkbLYY0DYI9zTJkQ2U5B2KX9veVAVokGcOzc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com; spf=pass smtp.mailfrom=foss.st.com; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b=XvXtLSyW; arc=none smtp.client-ip=91.207.212.93 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=foss.st.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b="XvXtLSyW" Received: from pps.filterd (m0369457.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 56PA1GhX017679; Fri, 25 Jul 2025 12:06:45 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=selector1; bh= 7kI1/Vm0FjdTzeh61iWpSbcVrel0dGvQIGRs/juBqLM=; b=XvXtLSyWeMfccCnO 8fv3iummLjMtKHKPKdnqhg5eq+PGUU0i1lfVLh/ggBRDAkBIhNViKI5nkeFlqrVk DU0HlsVFmoZb+x8VfRiEf7w4T59+AmFiHrPms/kuh3rxrD5OsyAGncLQ7DpPjjbi zn4oBlrHqy8mbsUbQkdpy4lMTydSvedcSIe/6xNjpBg3acZVNATUq3rambnrSk3H ERwvccCGXMul2qnGP1Sfd3wTpjnNfYSwUmP/217IGSUWW+xXseabTWKuYSu7EZpP QSqx/K8ug5QQTQ9nexy/lC+7Zh2pXz4cUKQFIEQ1+tHeacdZHME0mJmZD3FJSP43 RkcWLA== Received: from beta.dmz-ap.st.com (beta.dmz-ap.st.com [138.198.100.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 483w3t2ftt-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 25 Jul 2025 12:06:45 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 9D3814004B; Fri, 25 Jul 2025 12:05:29 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id A904578FDA8; Fri, 25 Jul 2025 12:04:26 +0200 (CEST) Received: from localhost (10.252.19.90) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Fri, 25 Jul 2025 12:04:26 +0200 From: Raphael Gallais-Pou Date: Fri, 25 Jul 2025 12:03:53 +0200 Subject: [PATCH 01/12] dt-bindings: display: st: add new compatible to LTDC device Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250725-drm-misc-next-v1-1-a59848e62cf9@foss.st.com> References: <20250725-drm-misc-next-v1-0-a59848e62cf9@foss.st.com> In-Reply-To: <20250725-drm-misc-next-v1-0-a59848e62cf9@foss.st.com> To: Yannick Fertre , Philippe Cornu , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Catalin Marinas , Will Deacon , Christophe Roullier CC: , , , , X-Mailer: b4 0.14.2 X-ClientProxiedBy: EQNCAS1NODE3.st.com (10.75.129.80) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-25_02,2025-07-24_01,2025-03-28_01 The new STMicroelectronics SoC features a display controller similar to the one used in previous SoCs. Because there is additional registers, it is incompatible with existing IPs. Add the new name to the list of compatible string. Signed-off-by: Raphael Gallais-Pou --- .../devicetree/bindings/display/st,stm32-ltdc.yaml | 37 ++++++++++++++++++= +--- 1 file changed, 33 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/display/st,stm32-ltdc.yaml b= /Documentation/devicetree/bindings/display/st,stm32-ltdc.yaml index d6ea4d62a2cfae26353c9f20a326a4329fed3a2f..546f57cb7a402b82e868aa05f87= 4c65b8da19444 100644 --- a/Documentation/devicetree/bindings/display/st,stm32-ltdc.yaml +++ b/Documentation/devicetree/bindings/display/st,stm32-ltdc.yaml @@ -12,7 +12,9 @@ maintainers: =20 properties: compatible: - const: st,stm32-ltdc + enum: + - st,stm32-ltdc + - st,stm32mp25-ltdc =20 reg: maxItems: 1 @@ -24,11 +26,12 @@ properties: minItems: 1 =20 clocks: - maxItems: 1 + minItems: 1 + maxItems: 4 =20 clock-names: - items: - - const: lcd + minItems: 1 + maxItems: 4 =20 resets: maxItems: 1 @@ -51,6 +54,32 @@ required: - resets - port =20 +if: + properties: + compatible: + contains: + enum: + - st,stm32-ltdc +then: + properties: + clocks: + maxItems: 1 + clock-names: + maxItems: 1 + items: + - const: lcd +else: + properties: + clocks: + maxItems: 4 + clock-names: + maxItems: 4 + items: + - const: bus + - const: lcd + - const: ref + - const: lvds + additionalProperties: false =20 examples: --=20 2.25.1 From nobody Mon Oct 6 03:11:19 2025 Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 418312D9490; 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Fri, 25 Jul 2025 12:06:44 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 9D05440049; Fri, 25 Jul 2025 12:05:29 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id AD1EC76869E; Fri, 25 Jul 2025 12:04:27 +0200 (CEST) Received: from localhost (10.252.19.90) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Fri, 25 Jul 2025 12:04:27 +0200 From: Raphael Gallais-Pou Date: Fri, 25 Jul 2025 12:03:54 +0200 Subject: [PATCH 02/12] dt-bindings: display: st,stm32-ltdc: add access-controllers property Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250725-drm-misc-next-v1-2-a59848e62cf9@foss.st.com> References: <20250725-drm-misc-next-v1-0-a59848e62cf9@foss.st.com> In-Reply-To: <20250725-drm-misc-next-v1-0-a59848e62cf9@foss.st.com> To: Yannick Fertre , Philippe Cornu , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Catalin Marinas , Will Deacon , Christophe Roullier CC: , , , , X-Mailer: b4 0.14.2 X-ClientProxiedBy: EQNCAS1NODE3.st.com (10.75.129.80) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-25_02,2025-07-24_01,2025-03-28_01 access-controllers is an optional property that allows a peripheral to refer to one or more domain access controller(s). This property is added when the peripheral is under the STM32 firewall controller. It allows an accurate representation of the hardware, where the peripheral is connected to a firewall bus. The firewall can then check the peripheral accesses before allowing its device to probe. Signed-off-by: Raphael Gallais-Pou Acked-by: Rob Herring (Arm) --- Documentation/devicetree/bindings/display/st,stm32-ltdc.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/display/st,stm32-ltdc.yaml b= /Documentation/devicetree/bindings/display/st,stm32-ltdc.yaml index 546f57cb7a402b82e868aa05f874c65b8da19444..962938978d4854c68d608dad0b1= 90ef3f6a7ba63 100644 --- a/Documentation/devicetree/bindings/display/st,stm32-ltdc.yaml +++ b/Documentation/devicetree/bindings/display/st,stm32-ltdc.yaml @@ -36,6 +36,9 @@ properties: resets: maxItems: 1 =20 + access-controllers: + maxItems: 1 + port: $ref: /schemas/graph.yaml#/properties/port description: | --=20 2.25.1 From nobody Mon Oct 6 03:11:19 2025 Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 36FC62DFF33; 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Fri, 25 Jul 2025 12:06:56 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 8299640052; Fri, 25 Jul 2025 12:05:33 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id BF6A57A19C4; Fri, 25 Jul 2025 12:04:28 +0200 (CEST) Received: from localhost (10.252.19.90) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Fri, 25 Jul 2025 12:04:28 +0200 From: Raphael Gallais-Pou Date: Fri, 25 Jul 2025 12:03:55 +0200 Subject: [PATCH 03/12] dt-bindings: display: st,stm32mp25-lvds: add access-controllers property Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250725-drm-misc-next-v1-3-a59848e62cf9@foss.st.com> References: <20250725-drm-misc-next-v1-0-a59848e62cf9@foss.st.com> In-Reply-To: <20250725-drm-misc-next-v1-0-a59848e62cf9@foss.st.com> To: Yannick Fertre , Philippe Cornu , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Catalin Marinas , Will Deacon , Christophe Roullier CC: , , , , X-Mailer: b4 0.14.2 X-ClientProxiedBy: EQNCAS1NODE3.st.com (10.75.129.80) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-25_02,2025-07-24_01,2025-03-28_01 access-controllers is an optional property that allows a peripheral to refer to one or more domain access controller(s). This property is added when the peripheral is under the STM32 firewall controller. It allows an accurate representation of the hardware, where the peripheral is connected to a firewall bus. The firewall can then check the peripheral accesses before allowing its device to probe. Signed-off-by: Raphael Gallais-Pou Acked-by: Rob Herring (Arm) --- Documentation/devicetree/bindings/display/st,stm32mp25-lvds.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/display/st,stm32mp25-lvds.ya= ml b/Documentation/devicetree/bindings/display/st,stm32mp25-lvds.yaml index 6736f93256b5cebb558cda5250369ec4b1b3033c..e046c0a4fdb7f13ca5a31b14ae0= ab19f2bc486fa 100644 --- a/Documentation/devicetree/bindings/display/st,stm32mp25-lvds.yaml +++ b/Documentation/devicetree/bindings/display/st,stm32mp25-lvds.yaml @@ -54,6 +54,9 @@ properties: resets: maxItems: 1 =20 + access-controllers: + maxItems: 1 + ports: $ref: /schemas/graph.yaml#/properties/ports =20 --=20 2.25.1 From nobody Mon Oct 6 03:11:19 2025 Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8176F2D94B5; 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Fri, 25 Jul 2025 12:06:56 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 5354F40051; Fri, 25 Jul 2025 12:05:33 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id CEA1076972A; Fri, 25 Jul 2025 12:04:29 +0200 (CEST) Received: from localhost (10.252.19.90) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Fri, 25 Jul 2025 12:04:29 +0200 From: Raphael Gallais-Pou Date: Fri, 25 Jul 2025 12:03:56 +0200 Subject: [PATCH 04/12] dt-bindings: display: st,stm32mp25-lvds: add power-domains property Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250725-drm-misc-next-v1-4-a59848e62cf9@foss.st.com> References: <20250725-drm-misc-next-v1-0-a59848e62cf9@foss.st.com> In-Reply-To: <20250725-drm-misc-next-v1-0-a59848e62cf9@foss.st.com> To: Yannick Fertre , Philippe Cornu , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Catalin Marinas , Will Deacon , Christophe Roullier CC: , , , , X-Mailer: b4 0.14.2 X-ClientProxiedBy: EQNCAS1NODE3.st.com (10.75.129.80) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-25_02,2025-07-24_01,2025-03-28_01 STM32 LVDS peripheral may be in a power domain. Allow an optional single 'power-domains' entry for STM32 LVDS devices. Signed-off-by: Raphael Gallais-Pou Acked-by: Rob Herring (Arm) --- Documentation/devicetree/bindings/display/st,stm32mp25-lvds.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/display/st,stm32mp25-lvds.ya= ml b/Documentation/devicetree/bindings/display/st,stm32mp25-lvds.yaml index e046c0a4fdb7f13ca5a31b14ae0ab19f2bc486fa..0bd8e9bcd92672a996ae2f6ae17= fa6179ffca615 100644 --- a/Documentation/devicetree/bindings/display/st,stm32mp25-lvds.yaml +++ b/Documentation/devicetree/bindings/display/st,stm32mp25-lvds.yaml @@ -57,6 +57,9 @@ properties: access-controllers: maxItems: 1 =20 + power-domains: + maxItems: 1 + ports: $ref: /schemas/graph.yaml#/properties/ports =20 --=20 2.25.1 From nobody Mon Oct 6 03:11:19 2025 Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 36F532DFF13; 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Fri, 25 Jul 2025 12:06:56 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id A175D40053; Fri, 25 Jul 2025 12:05:33 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id CE4B97A19C5; Fri, 25 Jul 2025 12:04:30 +0200 (CEST) Received: from localhost (10.252.19.90) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Fri, 25 Jul 2025 12:04:30 +0200 From: Raphael Gallais-Pou Date: Fri, 25 Jul 2025 12:03:57 +0200 Subject: [PATCH 05/12] dt-bindings: arm: stm32: add required #clock-cells property Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250725-drm-misc-next-v1-5-a59848e62cf9@foss.st.com> References: <20250725-drm-misc-next-v1-0-a59848e62cf9@foss.st.com> In-Reply-To: <20250725-drm-misc-next-v1-0-a59848e62cf9@foss.st.com> To: Yannick Fertre , Philippe Cornu , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Catalin Marinas , Will Deacon , Christophe Roullier CC: , , , , X-Mailer: b4 0.14.2 X-ClientProxiedBy: EQNCAS1NODE3.st.com (10.75.129.80) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-25_02,2025-07-24_01,2025-03-28_01 On STM32MP25 SoC, the syscfg peripheral provides a clock to the display subsystem through a multiplexer. Since it only provides a single clock, the cell value is 0. Doing so allows the clock consumers to reach the peripheral and gate the clock accordingly. Signed-off-by: Raphael Gallais-Pou Reviewed-by: Rob Herring (Arm) --- .../bindings/arm/stm32/st,stm32-syscon.yaml | 31 +++++++++++++++---= ---- 1 file changed, 21 insertions(+), 10 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.ya= ml b/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml index ed97652c84922813e94b1818c07fe8714891c089..95d2319afe235fa86974d80f89c= 9deeae2275232 100644 --- a/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml +++ b/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml @@ -36,20 +36,31 @@ properties: clocks: maxItems: 1 =20 + "#clock-cells": + const: 0 + required: - compatible - reg =20 -if: - properties: - compatible: - contains: - enum: - - st,stm32mp157-syscfg - - st,stm32f4-gcan -then: - required: - - clocks +allOf: + - if: + properties: + compatible: + contains: + enum: + - st,stm32mp157-syscfg + - st,stm32f4-gcan + then: + required: + - clocks + - if: + properties: + compatible: + const: st,stm32mp25-syscfg + then: + required: + - "#clock-cells" =20 additionalProperties: false =20 --=20 2.25.1 From nobody Mon Oct 6 03:11:19 2025 Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3FD092E5411; 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Fri, 25 Jul 2025 12:07:13 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id A09064005A; Fri, 25 Jul 2025 12:05:37 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id D342D7A1765; Fri, 25 Jul 2025 12:04:31 +0200 (CEST) Received: from localhost (10.252.19.90) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Fri, 25 Jul 2025 12:04:31 +0200 From: Raphael Gallais-Pou Date: Fri, 25 Jul 2025 12:03:58 +0200 Subject: [PATCH 06/12] drm/stm: ltdc: support new hardware version for STM32MP25 SoC Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250725-drm-misc-next-v1-6-a59848e62cf9@foss.st.com> References: <20250725-drm-misc-next-v1-0-a59848e62cf9@foss.st.com> In-Reply-To: <20250725-drm-misc-next-v1-0-a59848e62cf9@foss.st.com> To: Yannick Fertre , Philippe Cornu , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Catalin Marinas , Will Deacon , Christophe Roullier CC: , , , , X-Mailer: b4 0.14.2 X-ClientProxiedBy: EQNCAS1NODE3.st.com (10.75.129.80) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-25_02,2025-07-24_01,2025-03-28_01 From: Yannick Fertre STM32MP25 SoC features a new version of the LTDC IP. Add its compatible to the list of device to probe and implement its quirks. This hardware supports a pad frequency of 150MHz and a peripheral bus clock. Signed-off-by: Yannick Fertre Signed-off-by: Raphael Gallais-Pou --- drivers/gpu/drm/stm/drv.c | 11 ++++++++++- drivers/gpu/drm/stm/ltdc.c | 37 ++++++++++++++++++++++++++++++++++--- drivers/gpu/drm/stm/ltdc.h | 5 +++++ 3 files changed, 49 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/stm/drv.c b/drivers/gpu/drm/stm/drv.c index 8ebcaf953782d806a738d5a41ff1f428b0ccff78..03e6f0f07ffefd7e80c7b24b52c= af9ece9fa4365 100644 --- a/drivers/gpu/drm/stm/drv.c +++ b/drivers/gpu/drm/stm/drv.c @@ -236,8 +236,17 @@ static void stm_drm_platform_shutdown(struct platform_= device *pdev) drm_atomic_helper_shutdown(platform_get_drvdata(pdev)); } =20 +static struct ltdc_plat_data stm_drm_plat_data =3D { + .pad_max_freq_hz =3D 90000000, +}; + +static struct ltdc_plat_data stm_drm_plat_data_mp25 =3D { + .pad_max_freq_hz =3D 150000000, +}; + static const struct of_device_id drv_dt_ids[] =3D { - { .compatible =3D "st,stm32-ltdc"}, + { .compatible =3D "st,stm32-ltdc", .data =3D &stm_drm_plat_data, }, + { .compatible =3D "st,stm32mp25-ltdc", .data =3D &stm_drm_plat_data_mp25,= }, { /* end node */ }, }; MODULE_DEVICE_TABLE(of, drv_dt_ids); diff --git a/drivers/gpu/drm/stm/ltdc.c b/drivers/gpu/drm/stm/ltdc.c index ba315c66a04d72758b9d3cfcd842432877f66d3a..2bcdef76af2e8cbe3b6030decce= fa097f28adc3a 100644 --- a/drivers/gpu/drm/stm/ltdc.c +++ b/drivers/gpu/drm/stm/ltdc.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -51,6 +52,7 @@ #define HWVER_10300 0x010300 #define HWVER_20101 0x020101 #define HWVER_40100 0x040100 +#define HWVER_40101 0x040101 =20 /* * The address of some registers depends on the HW version: such registers= have @@ -1779,6 +1781,7 @@ static int ltdc_get_caps(struct drm_device *ddev) { struct ltdc_device *ldev =3D ddev->dev_private; u32 bus_width_log2, lcr, gc2r; + const struct ltdc_plat_data *pdata =3D of_device_get_match_data(ddev->dev= ); =20 /* * at least 1 layer must be managed & the number of layers @@ -1794,6 +1797,8 @@ static int ltdc_get_caps(struct drm_device *ddev) ldev->caps.bus_width =3D 8 << bus_width_log2; regmap_read(ldev->regmap, LTDC_IDR, &ldev->caps.hw_version); =20 + ldev->caps.pad_max_freq_hz =3D pdata->pad_max_freq_hz; + switch (ldev->caps.hw_version) { case HWVER_10200: case HWVER_10300: @@ -1811,7 +1816,6 @@ static int ltdc_get_caps(struct drm_device *ddev) * does not work on 2nd layer. */ ldev->caps.non_alpha_only_l1 =3D true; - ldev->caps.pad_max_freq_hz =3D 90000000; if (ldev->caps.hw_version =3D=3D HWVER_10200) ldev->caps.pad_max_freq_hz =3D 65000000; ldev->caps.nb_irq =3D 2; @@ -1842,6 +1846,7 @@ static int ltdc_get_caps(struct drm_device *ddev) ldev->caps.fifo_threshold =3D false; break; case HWVER_40100: + case HWVER_40101: ldev->caps.layer_ofs =3D LAY_OFS_1; ldev->caps.layer_regs =3D ltdc_layer_regs_a2; ldev->caps.pix_fmt_hw =3D ltdc_pix_fmt_a2; @@ -1849,7 +1854,6 @@ static int ltdc_get_caps(struct drm_device *ddev) ldev->caps.pix_fmt_nb =3D ARRAY_SIZE(ltdc_drm_fmt_a2); ldev->caps.pix_fmt_flex =3D true; ldev->caps.non_alpha_only_l1 =3D false; - ldev->caps.pad_max_freq_hz =3D 90000000; ldev->caps.nb_irq =3D 2; ldev->caps.ycbcr_input =3D true; ldev->caps.ycbcr_output =3D true; @@ -1872,6 +1876,8 @@ void ltdc_suspend(struct drm_device *ddev) =20 DRM_DEBUG_DRIVER("\n"); clk_disable_unprepare(ldev->pixel_clk); + if (ldev->bus_clk) + clk_disable_unprepare(ldev->bus_clk); } =20 int ltdc_resume(struct drm_device *ddev) @@ -1887,7 +1893,13 @@ int ltdc_resume(struct drm_device *ddev) return ret; } =20 - return 0; + if (ldev->bus_clk) { + ret =3D clk_prepare_enable(ldev->bus_clk); + if (ret) + drm_err(ddev, "failed to enable bus clock (%d)\n", ret); + } + + return ret; } =20 int ltdc_load(struct drm_device *ddev) @@ -1922,6 +1934,19 @@ int ltdc_load(struct drm_device *ddev) return -ENODEV; } =20 + if (of_device_is_compatible(np, "st,stm32mp25-ltdc")) { + ldev->bus_clk =3D devm_clk_get(dev, "bus"); + if (IS_ERR(ldev->bus_clk)) + return dev_err_probe(dev, PTR_ERR(ldev->bus_clk), + "Unable to get bus clock\n"); + + ret =3D clk_prepare_enable(ldev->bus_clk); + if (ret) { + drm_err(ddev, "Unable to prepare bus clock\n"); + return ret; + } + } + /* Get endpoints if any */ for (i =3D 0; i < nb_endpoints; i++) { ret =3D drm_of_find_panel_or_bridge(np, 0, i, &panel, &bridge); @@ -2034,6 +2059,9 @@ int ltdc_load(struct drm_device *ddev) =20 clk_disable_unprepare(ldev->pixel_clk); =20 + if (ldev->bus_clk) + clk_disable_unprepare(ldev->bus_clk); + pinctrl_pm_select_sleep_state(ddev->dev); =20 pm_runtime_enable(ddev->dev); @@ -2042,6 +2070,9 @@ int ltdc_load(struct drm_device *ddev) err: clk_disable_unprepare(ldev->pixel_clk); =20 + if (ldev->bus_clk) + clk_disable_unprepare(ldev->bus_clk); + return ret; } =20 diff --git a/drivers/gpu/drm/stm/ltdc.h b/drivers/gpu/drm/stm/ltdc.h index 9d488043ffdbc652deeede71c9d57d45fb89d3c6..ddfa8ae61a7ba5dc446fae64756= 2d0ec8e6953e1 100644 --- a/drivers/gpu/drm/stm/ltdc.h +++ b/drivers/gpu/drm/stm/ltdc.h @@ -40,10 +40,15 @@ struct fps_info { ktime_t last_timestamp; }; =20 +struct ltdc_plat_data { + int pad_max_freq_hz; /* max frequency supported by pad */ +}; + struct ltdc_device { void __iomem *regs; struct regmap *regmap; struct clk *pixel_clk; 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The LTDC operates with multiple clock domains for register access, requiring all clocks to be provided during read/write operations. This imposes a dependency between the LVDS and LTDC to access correctly all LTDC registers. And because both IPs' pixel rates must be synchronized, the LTDC has to handle the LVDS clock. Signed-off-by: Yannick Fertre Signed-off-by: Raphael Gallais-Pou --- drivers/gpu/drm/stm/ltdc.c | 22 +++++++++++++++++++++- drivers/gpu/drm/stm/ltdc.h | 1 + 2 files changed, 22 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/stm/ltdc.c b/drivers/gpu/drm/stm/ltdc.c index 2bcdef76af2e8cbe3b6030deccefa097f28adc3a..031c561b8e780a55b77f4a4c833= 8e74b52bbbb48 100644 --- a/drivers/gpu/drm/stm/ltdc.c +++ b/drivers/gpu/drm/stm/ltdc.c @@ -837,6 +837,12 @@ ltdc_crtc_mode_valid(struct drm_crtc *crtc, int target_max =3D target + CLK_TOLERANCE_HZ; int result; =20 + if (ldev->lvds_clk) { + result =3D clk_round_rate(ldev->lvds_clk, target); + drm_dbg_driver(crtc->dev, "lvds pixclk rate target %d, available %d\n", + target, result); + } + result =3D clk_round_rate(ldev->pixel_clk, target); =20 DRM_DEBUG_DRIVER("clk rate target %d, available %d\n", target, result); @@ -1878,6 +1884,8 @@ void ltdc_suspend(struct drm_device *ddev) clk_disable_unprepare(ldev->pixel_clk); if (ldev->bus_clk) clk_disable_unprepare(ldev->bus_clk); + if (ldev->lvds_clk) + clk_disable_unprepare(ldev->lvds_clk); } =20 int ltdc_resume(struct drm_device *ddev) @@ -1895,8 +1903,16 @@ int ltdc_resume(struct drm_device *ddev) =20 if (ldev->bus_clk) { ret =3D clk_prepare_enable(ldev->bus_clk); - if (ret) + if (ret) { drm_err(ddev, "failed to enable bus clock (%d)\n", ret); + return ret; + } + } + + if (ldev->lvds_clk) { + ret =3D clk_prepare_enable(ldev->lvds_clk); + if (ret) + drm_err(ddev, "failed to prepare lvds clock\n"); } =20 return ret; @@ -1980,6 +1996,10 @@ int ltdc_load(struct drm_device *ddev) } } =20 + ldev->lvds_clk =3D devm_clk_get(dev, "lvds"); + if (IS_ERR(ldev->lvds_clk)) + ldev->lvds_clk =3D NULL; + rstc =3D devm_reset_control_get_exclusive(dev, NULL); =20 mutex_init(&ldev->err_lock); diff --git a/drivers/gpu/drm/stm/ltdc.h b/drivers/gpu/drm/stm/ltdc.h index ddfa8ae61a7ba5dc446fae647562d0ec8e6953e1..17b51a7ce28eee5de6d24ca943c= a3b1f48695dfd 100644 --- a/drivers/gpu/drm/stm/ltdc.h +++ b/drivers/gpu/drm/stm/ltdc.h @@ -48,6 +48,7 @@ struct ltdc_device { void __iomem *regs; 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Fri, 25 Jul 2025 12:05:37 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id CF8377A19CA; Fri, 25 Jul 2025 12:04:33 +0200 (CEST) Received: from localhost (10.252.19.90) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Fri, 25 Jul 2025 12:04:33 +0200 From: Raphael Gallais-Pou Date: Fri, 25 Jul 2025 12:04:00 +0200 Subject: [PATCH 08/12] arm64: dts: st: add ltdc support on stm32mp251 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250725-drm-misc-next-v1-8-a59848e62cf9@foss.st.com> References: <20250725-drm-misc-next-v1-0-a59848e62cf9@foss.st.com> In-Reply-To: <20250725-drm-misc-next-v1-0-a59848e62cf9@foss.st.com> To: Yannick Fertre , Philippe Cornu , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Catalin Marinas , Will Deacon , Christophe Roullier CC: , , , , X-Mailer: b4 0.14.2 X-ClientProxiedBy: EQNCAS1NODE3.st.com (10.75.129.80) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-25_02,2025-07-24_01,2025-03-28_01 The LCD-TFT Display Controller (LTDC) handles display composition, scaling and rotation. It provides a parallel digital RGB flow to be used by display interfaces. Add the LTDC node. Signed-off-by: Raphael Gallais-Pou --- arch/arm64/boot/dts/st/stm32mp251.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/s= t/stm32mp251.dtsi index 8d87865850a7a6e8095c36acdef83c8e3a73ae54..9698170547c13ca17f032dd714d= d4d7290a9b0e2 100644 --- a/arch/arm64/boot/dts/st/stm32mp251.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi @@ -1052,6 +1052,18 @@ dcmipp: dcmipp@48030000 { status =3D "disabled"; }; =20 + ltdc: display-controller@48010000 { + compatible =3D "st,stm32mp25-ltdc"; + reg =3D <0x48010000 0x400>; + interrupts =3D , + ; + clocks =3D <&rcc CK_BUS_LTDC>, <&rcc CK_KER_LTDC>; + clock-names =3D "bus", "lcd"; + resets =3D <&rcc LTDC_R>; + access-controllers =3D <&rifsc 80>; + status =3D "disabled"; + }; + combophy: phy@480c0000 { compatible =3D "st,stm32mp25-combophy"; reg =3D <0x480c0000 0x1000>; --=20 2.25.1 From nobody Mon Oct 6 03:11:19 2025 Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5F7B82E5411; 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Fri, 25 Jul 2025 12:07:08 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id AADE74005B; Fri, 25 Jul 2025 12:05:37 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id CF0757A19C9; Fri, 25 Jul 2025 12:04:34 +0200 (CEST) Received: from localhost (10.252.19.90) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Fri, 25 Jul 2025 12:04:34 +0200 From: Raphael Gallais-Pou Date: Fri, 25 Jul 2025 12:04:01 +0200 Subject: [PATCH 09/12] arm64: dts: st: add lvds support on stm32mp255 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250725-drm-misc-next-v1-9-a59848e62cf9@foss.st.com> References: <20250725-drm-misc-next-v1-0-a59848e62cf9@foss.st.com> In-Reply-To: <20250725-drm-misc-next-v1-0-a59848e62cf9@foss.st.com> To: Yannick Fertre , Philippe Cornu , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Catalin Marinas , Will Deacon , Christophe Roullier CC: , , , , X-Mailer: b4 0.14.2 X-ClientProxiedBy: EQNCAS1NODE3.st.com (10.75.129.80) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-25_02,2025-07-24_01,2025-03-28_01 The LVDS is used on STM32MP2 as a display interface. Add the LVDS node. Signed-off-by: Raphael Gallais-Pou --- arch/arm64/boot/dts/st/stm32mp255.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp255.dtsi b/arch/arm64/boot/dts/s= t/stm32mp255.dtsi index f689b47c5010033120146cf1954d6624c0270045..a4d965f785fa42c459749401085= 5aec7e1b9fdd1 100644 --- a/arch/arm64/boot/dts/st/stm32mp255.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp255.dtsi @@ -6,6 +6,18 @@ #include "stm32mp253.dtsi" =20 &rifsc { + lvds: lvds@48060000 { + compatible =3D "st,stm32mp25-lvds"; + #clock-cells =3D <0>; + reg =3D <0x48060000 0x2000>; + clocks =3D <&rcc CK_BUS_LVDS>, <&rcc CK_KER_LVDSPHY>; + clock-names =3D "pclk", "ref"; + resets =3D <&rcc LVDS_R>; + access-controllers =3D <&rifsc 84>; + power-domains =3D <&CLUSTER_PD>; + status =3D "disabled"; + }; + vdec: vdec@480d0000 { compatible =3D "st,stm32mp25-vdec"; reg =3D <0x480d0000 0x3c8>; --=20 2.25.1 From nobody Mon Oct 6 03:11:19 2025 Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4B9EC2E03FF; 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Fri, 25 Jul 2025 12:06:56 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 56CEA4005C; Fri, 25 Jul 2025 12:05:40 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id C7BDD7A19DB; Fri, 25 Jul 2025 12:04:35 +0200 (CEST) Received: from localhost (10.252.19.90) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Fri, 25 Jul 2025 12:04:35 +0200 From: Raphael Gallais-Pou Date: Fri, 25 Jul 2025 12:04:02 +0200 Subject: [PATCH 10/12] arm64: dts: st: add clock-cells to syscfg node on stm32mp251 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250725-drm-misc-next-v1-10-a59848e62cf9@foss.st.com> References: <20250725-drm-misc-next-v1-0-a59848e62cf9@foss.st.com> In-Reply-To: <20250725-drm-misc-next-v1-0-a59848e62cf9@foss.st.com> To: Yannick Fertre , Philippe Cornu , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Catalin Marinas , Will Deacon , Christophe Roullier CC: , , , , X-Mailer: b4 0.14.2 X-ClientProxiedBy: EQNCAS1NODE3.st.com (10.75.129.80) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-25_02,2025-07-24_01,2025-03-28_01 Make the syscfg node a clock provider so clock consumers can reach child clocks through device-tree. Signed-off-by: Raphael Gallais-Pou --- arch/arm64/boot/dts/st/stm32mp251.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/s= t/stm32mp251.dtsi index 9698170547c13ca17f032dd714dd4d7290a9b0e2..c561df51a6001004e45fb53a56d= 5d42c310e6b61 100644 --- a/arch/arm64/boot/dts/st/stm32mp251.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi @@ -1344,6 +1344,7 @@ exti1: interrupt-controller@44220000 { syscfg: syscon@44230000 { compatible =3D "st,stm32mp25-syscfg", "syscon"; reg =3D <0x44230000 0x10000>; + #clock-cells =3D <0>; }; =20 pinctrl: pinctrl@44240000 { --=20 2.25.1 From nobody Mon Oct 6 03:11:19 2025 Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5A6242DA777; Fri, 25 Jul 2025 10:07:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Fri, 25 Jul 2025 12:06:56 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 5B7464005D; Fri, 25 Jul 2025 12:05:41 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id CC12C7A19C2; Fri, 25 Jul 2025 12:04:36 +0200 (CEST) Received: from localhost (10.252.19.90) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Fri, 25 Jul 2025 12:04:36 +0200 From: Raphael Gallais-Pou Date: Fri, 25 Jul 2025 12:04:03 +0200 Subject: [PATCH 11/12] arm64: dts: st: enable display support on stm32mp257f-ev1 board Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250725-drm-misc-next-v1-11-a59848e62cf9@foss.st.com> References: <20250725-drm-misc-next-v1-0-a59848e62cf9@foss.st.com> In-Reply-To: <20250725-drm-misc-next-v1-0-a59848e62cf9@foss.st.com> To: Yannick Fertre , Philippe Cornu , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Catalin Marinas , Will Deacon , Christophe Roullier CC: , , , , X-Mailer: b4 0.14.2 X-ClientProxiedBy: EQNCAS1NODE3.st.com (10.75.129.80) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-25_02,2025-07-24_01,2025-03-28_01 Enable the following IPs on stm32mp257f-ev1 in order to get display: * LTDC * LVDS * WSVGA LVDS panel (1024x600) * Panel LVDS backlight as GPIO backlight * ILI2511 i2c touchscreen Signed-off-by: Raphael Gallais-Pou --- arch/arm64/boot/dts/st/stm32mp257f-ev1.dts | 79 ++++++++++++++++++++++++++= ++++ 1 file changed, 79 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts b/arch/arm64/boot/d= ts/st/stm32mp257f-ev1.dts index 2f561ad4066544445e93db78557bc4be1c27095a..b324b0c226ddf043e62f0124524= 0f3e8d2b0a53c 100644 --- a/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts +++ b/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts @@ -86,6 +86,43 @@ mm_ospi1: mm-ospi@60000000 { no-map; }; }; + + panel_lvds: display { + compatible =3D "edt,etml0700z9ndha", "panel-lvds"; + enable-gpios =3D <&gpiog 15 GPIO_ACTIVE_HIGH>; + backlight =3D <&panel_lvds_backlight>; + power-supply =3D <&scmi_v3v3>; + status =3D "okay"; + + width-mm =3D <156>; + height-mm =3D <92>; + data-mapping =3D "vesa-24"; + + panel-timing { + clock-frequency =3D <54000000>; + hactive =3D <1024>; + vactive =3D <600>; + hfront-porch =3D <150>; + hback-porch =3D <150>; + hsync-len =3D <21>; + vfront-porch =3D <24>; + vback-porch =3D <24>; + vsync-len =3D <21>; + }; + + port { + lvds_panel_in: endpoint { + remote-endpoint =3D <&lvds_out0>; + }; + }; + }; + + panel_lvds_backlight: backlight { + compatible =3D "gpio-backlight"; + gpios =3D <&gpioi 5 GPIO_ACTIVE_HIGH>; + default-on; + status =3D "okay"; + }; }; =20 &arm_wdt { @@ -183,6 +220,15 @@ imx335_ep: endpoint { }; }; }; + + ili2511: ili2511@41 { + compatible =3D "ilitek,ili251x"; + reg =3D <0x41>; + interrupt-parent =3D <&gpioi>; + interrupts =3D <13 IRQ_TYPE_EDGE_FALLING>; + reset-gpios =3D <&gpiog 14 GPIO_ACTIVE_LOW>; + status =3D "okay"; + }; }; =20 &i2c8 { @@ -230,6 +276,39 @@ timer { }; }; =20 +<dc { + status =3D "okay"; + + port { + ltdc_ep0_out: endpoint { + remote-endpoint =3D <&lvds_in>; + }; + }; +}; + +&lvds { + status =3D "okay"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + lvds_in: endpoint { + remote-endpoint =3D <<dc_ep0_out>; + }; + }; + + port@1 { + reg =3D <1>; + lvds_out0: endpoint { + remote-endpoint =3D <&lvds_panel_in>; + }; + }; + }; +}; + &rtc { status =3D "okay"; }; --=20 2.25.1 From nobody Mon Oct 6 03:11:19 2025 Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 47E682E5B3E; Fri, 25 Jul 2025 10:07:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.132.182.106 ARC-Seal: i=1; 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Fri, 25 Jul 2025 12:07:13 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 2A7F940060; Fri, 25 Jul 2025 12:05:45 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id CD1607A19E6; Fri, 25 Jul 2025 12:04:37 +0200 (CEST) Received: from localhost (10.252.19.90) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Fri, 25 Jul 2025 12:04:37 +0200 From: Raphael Gallais-Pou Date: Fri, 25 Jul 2025 12:04:04 +0200 Subject: [PATCH 12/12] arm64: dts: st: add loopback clocks on LTDC node Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250725-drm-misc-next-v1-12-a59848e62cf9@foss.st.com> References: <20250725-drm-misc-next-v1-0-a59848e62cf9@foss.st.com> In-Reply-To: <20250725-drm-misc-next-v1-0-a59848e62cf9@foss.st.com> To: Yannick Fertre , Philippe Cornu , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Catalin Marinas , Will Deacon , Christophe Roullier CC: , , , , X-Mailer: b4 0.14.2 X-ClientProxiedBy: EQNCAS1NODE3.st.com (10.75.129.80) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-25_02,2025-07-24_01,2025-03-28_01 ck_ker_ltdc has the CLK_SET_RATE_PARENT flag. While having this flag is semantically correct, it for now leads to an improper setting of the clock rate. The ck_ker_ltdc parent clock is the flexgen 27, which does not support changing rates yet. To overcome this issue, a fixed clock can be used for the kernel clock. Add the clocks needed for the LTDC to work. Signed-off-by: Raphael Gallais-Pou --- arch/arm64/boot/dts/st/stm32mp251.dtsi | 6 ++++++ arch/arm64/boot/dts/st/stm32mp255.dtsi | 7 ++++++- 2 files changed, 12 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/s= t/stm32mp251.dtsi index c561df51a6001004e45fb53a56d5d42c310e6b61..54dd57e0a98eabbbcfe89459e6d= 63eb287f5ca04 100644 --- a/arch/arm64/boot/dts/st/stm32mp251.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi @@ -52,6 +52,12 @@ clk_rcbsec: clk-rcbsec { compatible =3D "fixed-clock"; clock-frequency =3D <64000000>; }; + + clk_flexgen_27_fixed: clk-54000000 { + #clock-cells =3D <0>; + compatible =3D "fixed-clock"; + clock-frequency =3D <54000000>; + }; }; =20 firmware { diff --git a/arch/arm64/boot/dts/st/stm32mp255.dtsi b/arch/arm64/boot/dts/s= t/stm32mp255.dtsi index a4d965f785fa42c4597494010855aec7e1b9fdd1..82c2fa67b6b91f67d51872ed098= aea897fab0197 100644 --- a/arch/arm64/boot/dts/st/stm32mp255.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp255.dtsi @@ -5,6 +5,11 @@ */ #include "stm32mp253.dtsi" =20 +<dc { + clocks =3D <&rcc CK_BUS_LTDC>, <&clk_flexgen_27_fixed>, <&syscfg>, <&lvds= >; + clock-names =3D "bus", "lcd", "ref", "lvds"; +}; + &rifsc { lvds: lvds@48060000 { compatible =3D "st,stm32mp25-lvds"; @@ -34,4 +39,4 @@ venc: venc@480e0000 { clocks =3D <&rcc CK_BUS_VENC>; access-controllers =3D <&rifsc 90>; }; -}; \ No newline at end of file +}; --=20 2.25.1