From nobody Mon Oct 6 04:59:08 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DBBF224888C; Thu, 24 Jul 2025 20:12:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753387963; cv=none; b=VQthbrs1gDfro9OApmuyXWdBS/n+LRpdHrgDE5qHodUnj25f12wu7l7sel5IOsrMuX+oNHgTeAZ0/DhYI2d6iE9HTvAYPV2Uy/XRT1YQvuVT64wTGKJhxqKZ1kn1O0PIpjE3zPlj0ljpxC6v4WYZjfnWFrvo7xPDEMUpIbp462I= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753387963; c=relaxed/simple; bh=SVmFzM9HX1G4W1SR5ohas/J7SBbMjYe1/YYfaD8egpM=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=PVA7BljVSmIgHmlIvpqwUx7rXRGPMA/boy438xrkm8ncLlGtlFczAQXA9mieO2j3izTLsOsQdhnvBxO8kxz+ddcpi+zpeH1zXiTDgQ9yxUQ7M5nXrsXhMm9k43FlZcvOwkJRst3460t/Z6VNMtJnGkUZZ+vNsL7unVeTqmACzNY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=qKNyUqd8; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="qKNyUqd8" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1753387961; x=1784923961; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=SVmFzM9HX1G4W1SR5ohas/J7SBbMjYe1/YYfaD8egpM=; b=qKNyUqd8UiVdzIUeMk9PPaTeAnDAzjEih6VqPhpaIdo6WR2iMPPzGgag 3NLBPEQt9pp/V/Vdw93ymBVvGQKQLc6DmwqTNG0BzCQZNkLggCrifKEnD 3GY/a0AV2epy2YA17n/a1bid/36nKU5r0Mf5wfy2W8lDohYQv+I7e9K3p VqXKK69SmfkEP5XeQSRiw0MF+VHJwdGGViVgPQ8GICYOq2OstEMDBtUYl 2Nvw4KETA3cmoev0AGswM89Enr6U9ctj4uHW6Q8KOX9tWVU5jpxSmJS8M HT9F+eaX2wr9teCcfcF5OtEhUc0YZiK4Xnbrq2/N2Ow+F2fBATBy4/qHO Q==; X-CSE-ConnectionGUID: Vloo96aWRWWEYpPX1eCS2Q== X-CSE-MsgGUID: dw1dE8HlQKK+Caexc1LEXQ== X-IronPort-AV: E=Sophos;i="6.16,337,1744095600"; d="scan'208";a="211826703" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 24 Jul 2025 13:12:34 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.44; Thu, 24 Jul 2025 13:11:30 -0700 Received: from DEN-DL-M31836.microchip.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.44 via Frontend Transport; Thu, 24 Jul 2025 13:11:28 -0700 From: Horatiu Vultur To: , , , , , , , , CC: , , Horatiu Vultur Subject: [PATCH net-next v2 1/4] net: phy: micrel: Start using PHY_ID_MATCH_MODEL Date: Thu, 24 Jul 2025 22:08:23 +0200 Message-ID: <20250724200826.2662658-2-horatiu.vultur@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250724200826.2662658-1-horatiu.vultur@microchip.com> References: <20250724200826.2662658-1-horatiu.vultur@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Start using PHY_ID_MATCH_MODEL for all the drivers. While at this add also PHY_ID_KSZ8041RNLI to micrel_tbl. Signed-off-by: Horatiu Vultur --- drivers/net/phy/micrel.c | 66 ++++++++++++++++------------------------ 1 file changed, 27 insertions(+), 39 deletions(-) diff --git a/drivers/net/phy/micrel.c b/drivers/net/phy/micrel.c index f678c1bdacdf0..c6aacf7feb7b0 100644 --- a/drivers/net/phy/micrel.c +++ b/drivers/net/phy/micrel.c @@ -5643,8 +5643,7 @@ static int ksz9131_resume(struct phy_device *phydev) =20 static struct phy_driver ksphy_driver[] =3D { { - .phy_id =3D PHY_ID_KS8737, - .phy_id_mask =3D MICREL_PHY_ID_MASK, + PHY_ID_MATCH_MODEL(PHY_ID_KS8737), .name =3D "Micrel KS8737", /* PHY_BASIC_FEATURES */ .driver_data =3D &ks8737_type, @@ -5685,8 +5684,7 @@ static struct phy_driver ksphy_driver[] =3D { .suspend =3D kszphy_suspend, .resume =3D kszphy_resume, }, { - .phy_id =3D PHY_ID_KSZ8041, - .phy_id_mask =3D MICREL_PHY_ID_MASK, + PHY_ID_MATCH_MODEL(PHY_ID_KSZ8041), .name =3D "Micrel KSZ8041", /* PHY_BASIC_FEATURES */ .driver_data =3D &ksz8041_type, @@ -5701,8 +5699,7 @@ static struct phy_driver ksphy_driver[] =3D { .suspend =3D ksz8041_suspend, .resume =3D ksz8041_resume, }, { - .phy_id =3D PHY_ID_KSZ8041RNLI, - .phy_id_mask =3D MICREL_PHY_ID_MASK, + PHY_ID_MATCH_MODEL(PHY_ID_KSZ8041RNLI), .name =3D "Micrel KSZ8041RNLI", /* PHY_BASIC_FEATURES */ .driver_data =3D &ksz8041_type, @@ -5745,9 +5742,8 @@ static struct phy_driver ksphy_driver[] =3D { .suspend =3D kszphy_suspend, .resume =3D kszphy_resume, }, { - .phy_id =3D PHY_ID_KSZ8081, + PHY_ID_MATCH_MODEL(PHY_ID_KSZ8081), .name =3D "Micrel KSZ8081 or KSZ8091", - .phy_id_mask =3D MICREL_PHY_ID_MASK, .flags =3D PHY_POLL_CABLE_TEST, /* PHY_BASIC_FEATURES */ .driver_data =3D &ksz8081_type, @@ -5766,9 +5762,8 @@ static struct phy_driver ksphy_driver[] =3D { .cable_test_start =3D ksz886x_cable_test_start, .cable_test_get_status =3D ksz886x_cable_test_get_status, }, { - .phy_id =3D PHY_ID_KSZ8061, + PHY_ID_MATCH_MODEL(PHY_ID_KSZ8061), .name =3D "Micrel KSZ8061", - .phy_id_mask =3D MICREL_PHY_ID_MASK, /* PHY_BASIC_FEATURES */ .probe =3D kszphy_probe, .config_init =3D ksz8061_config_init, @@ -5796,8 +5791,7 @@ static struct phy_driver ksphy_driver[] =3D { .read_mmd =3D genphy_read_mmd_unsupported, .write_mmd =3D genphy_write_mmd_unsupported, }, { - .phy_id =3D PHY_ID_KSZ9031, - .phy_id_mask =3D MICREL_PHY_ID_MASK, + PHY_ID_MATCH_MODEL(PHY_ID_KSZ9031), .name =3D "Micrel KSZ9031 Gigabit PHY", .flags =3D PHY_POLL_CABLE_TEST, .driver_data =3D &ksz9021_type, @@ -5817,8 +5811,7 @@ static struct phy_driver ksphy_driver[] =3D { .cable_test_get_status =3D ksz9x31_cable_test_get_status, .set_loopback =3D ksz9031_set_loopback, }, { - .phy_id =3D PHY_ID_LAN8814, - .phy_id_mask =3D MICREL_PHY_ID_MASK, + PHY_ID_MATCH_MODEL(PHY_ID_LAN8814), .name =3D "Microchip INDY Gigabit Quad PHY", .flags =3D PHY_POLL_CABLE_TEST, .config_init =3D lan8814_config_init, @@ -5836,8 +5829,7 @@ static struct phy_driver ksphy_driver[] =3D { .cable_test_start =3D lan8814_cable_test_start, .cable_test_get_status =3D ksz886x_cable_test_get_status, }, { - .phy_id =3D PHY_ID_LAN8804, - .phy_id_mask =3D MICREL_PHY_ID_MASK, + PHY_ID_MATCH_MODEL(PHY_ID_LAN8804), .name =3D "Microchip LAN966X Gigabit PHY", .config_init =3D lan8804_config_init, .driver_data =3D &ksz9021_type, @@ -5852,8 +5844,7 @@ static struct phy_driver ksphy_driver[] =3D { .config_intr =3D lan8804_config_intr, .handle_interrupt =3D lan8804_handle_interrupt, }, { - .phy_id =3D PHY_ID_LAN8841, - .phy_id_mask =3D MICREL_PHY_ID_MASK, + PHY_ID_MATCH_MODEL(PHY_ID_LAN8841), .name =3D "Microchip LAN8841 Gigabit PHY", .flags =3D PHY_POLL_CABLE_TEST, .driver_data =3D &lan8841_type, @@ -5870,8 +5861,7 @@ static struct phy_driver ksphy_driver[] =3D { .cable_test_start =3D lan8814_cable_test_start, .cable_test_get_status =3D ksz886x_cable_test_get_status, }, { - .phy_id =3D PHY_ID_KSZ9131, - .phy_id_mask =3D MICREL_PHY_ID_MASK, + PHY_ID_MATCH_MODEL(PHY_ID_KSZ9131), .name =3D "Microchip KSZ9131 Gigabit PHY", /* PHY_GBIT_FEATURES */ .flags =3D PHY_POLL_CABLE_TEST, @@ -5892,8 +5882,7 @@ static struct phy_driver ksphy_driver[] =3D { .cable_test_get_status =3D ksz9x31_cable_test_get_status, .get_features =3D ksz9477_get_features, }, { - .phy_id =3D PHY_ID_KSZ8873MLL, - .phy_id_mask =3D MICREL_PHY_ID_MASK, + PHY_ID_MATCH_MODEL(PHY_ID_KSZ8873MLL), .name =3D "Micrel KSZ8873MLL Switch", /* PHY_BASIC_FEATURES */ .config_init =3D kszphy_config_init, @@ -5902,8 +5891,7 @@ static struct phy_driver ksphy_driver[] =3D { .suspend =3D genphy_suspend, .resume =3D genphy_resume, }, { - .phy_id =3D PHY_ID_KSZ886X, - .phy_id_mask =3D MICREL_PHY_ID_MASK, + PHY_ID_MATCH_MODEL(PHY_ID_KSZ886X), .name =3D "Micrel KSZ8851 Ethernet MAC or KSZ886X Switch", .driver_data =3D &ksz886x_type, /* PHY_BASIC_FEATURES */ @@ -5923,8 +5911,7 @@ static struct phy_driver ksphy_driver[] =3D { .suspend =3D genphy_suspend, .resume =3D genphy_resume, }, { - .phy_id =3D PHY_ID_KSZ9477, - .phy_id_mask =3D MICREL_PHY_ID_MASK, + PHY_ID_MATCH_MODEL(PHY_ID_KSZ9477), .name =3D "Microchip KSZ9477", .probe =3D kszphy_probe, /* PHY_GBIT_FEATURES */ @@ -5951,22 +5938,23 @@ MODULE_LICENSE("GPL"); =20 static const struct mdio_device_id __maybe_unused micrel_tbl[] =3D { { PHY_ID_KSZ9021, 0x000ffffe }, - { PHY_ID_KSZ9031, MICREL_PHY_ID_MASK }, - { PHY_ID_KSZ9131, MICREL_PHY_ID_MASK }, + { PHY_ID_MATCH_MODEL(PHY_ID_KSZ9031) }, + { PHY_ID_MATCH_MODEL(PHY_ID_KSZ9131) }, { PHY_ID_KSZ8001, 0x00fffffc }, - { PHY_ID_KS8737, MICREL_PHY_ID_MASK }, + { PHY_ID_MATCH_MODEL(PHY_ID_KS8737) }, { PHY_ID_KSZ8021, 0x00ffffff }, { PHY_ID_KSZ8031, 0x00ffffff }, - { PHY_ID_KSZ8041, MICREL_PHY_ID_MASK }, - { PHY_ID_KSZ8051, MICREL_PHY_ID_MASK }, - { PHY_ID_KSZ8061, MICREL_PHY_ID_MASK }, - { PHY_ID_KSZ8081, MICREL_PHY_ID_MASK }, - { PHY_ID_KSZ8873MLL, MICREL_PHY_ID_MASK }, - { PHY_ID_KSZ886X, MICREL_PHY_ID_MASK }, - { PHY_ID_KSZ9477, MICREL_PHY_ID_MASK }, - { PHY_ID_LAN8814, MICREL_PHY_ID_MASK }, - { PHY_ID_LAN8804, MICREL_PHY_ID_MASK }, - { PHY_ID_LAN8841, MICREL_PHY_ID_MASK }, + { PHY_ID_MATCH_MODEL(PHY_ID_KSZ8041) }, + { PHY_ID_MATCH_MODEL(PHY_ID_KSZ8041RNLI) }, + { PHY_ID_MATCH_MODEL(PHY_ID_KSZ8051) }, + { PHY_ID_MATCH_MODEL(PHY_ID_KSZ8061) }, + { PHY_ID_MATCH_MODEL(PHY_ID_KSZ8081) }, + { PHY_ID_MATCH_MODEL(PHY_ID_KSZ8873MLL) }, + { PHY_ID_MATCH_MODEL(PHY_ID_KSZ886X) }, + { PHY_ID_MATCH_MODEL(PHY_ID_KSZ9477) }, + { PHY_ID_MATCH_MODEL(PHY_ID_LAN8814) }, + { PHY_ID_MATCH_MODEL(PHY_ID_LAN8804) }, + { PHY_ID_MATCH_MODEL(PHY_ID_LAN8841) }, { } }; =20 --=20 2.34.1 From nobody Mon Oct 6 04:59:08 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1F4B022D4DE; Thu, 24 Jul 2025 20:12:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753387932; cv=none; b=NMD7z285xM2Yvudqw80fFsbfEQuxw1pjdqinxCNrb7smDazxcT/LEG93sCthoiL/F5xy8pw8KhTcht60883K4dBzv+t/7zAhtDjrzJBLbmK+8Gv6QrbhCJIOYliyw4dBYjD2mkAb8Y5lfn7UwHG/slo4J5XDgi+2vGn5vLME8eA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753387932; c=relaxed/simple; bh=nmARrY53udeSjJWuHveIype0UPUfLDn4BfiYQiZXyhI=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=YyC6LoPPoNVVao/0z15IBeCirNMwQlblIcX4kbpZy3rGAzl5b4fXxzjAfAPTTRDfZLX6ju5SNFkEVTjjsMenKa2l2QKmAh0m0FYZF2PXtavqttWHKt7VnvJ37mLz0UyqQ55BnNMuqXVO3a/cjxz45Ec/944N48jYh7chpRmi59E= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=QVey1vBX; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="QVey1vBX" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1753387931; x=1784923931; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=nmARrY53udeSjJWuHveIype0UPUfLDn4BfiYQiZXyhI=; b=QVey1vBXcESV8lZHmMOEpjq+rE2jiMOMHPBsRyCMLcvgN0hueagq0IJp s02c890favrYu9TCEmvZ0dyhpClwAEV4fvgB7GNjAc4GejhN18F6wJNnv UBxcdHor6WfW1XuYV/ViNq7leBRYW5ZPklTZiyPLHIlGj4XknnX8NZi7A w3dX218Ec3tA/ptMpCA8Rk0IygsJiewSxSe6amwakvBWIwtvRbXcb9wW2 IIRpS/AuM/RDPI61BMOAwskUyb6voJkD/b8CMIb0TYA0yoTyhw/ToCz+B bwijwSudMB4FUbGBhbRZoNryXSeXj0NN9PIp9/RMvMekKdakoLY+QhP/N Q==; X-CSE-ConnectionGUID: dPxjunYJTo2XkJR5vJWM1w== X-CSE-MsgGUID: PafZ9Xd6So6cqHGNOwe6yQ== X-IronPort-AV: E=Sophos;i="6.16,337,1744095600"; d="scan'208";a="44383321" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa3.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 24 Jul 2025 13:12:09 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.44; Thu, 24 Jul 2025 13:11:32 -0700 Received: from DEN-DL-M31836.microchip.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.44 via Frontend Transport; Thu, 24 Jul 2025 13:11:30 -0700 From: Horatiu Vultur To: , , , , , , , , CC: , , Horatiu Vultur Subject: [PATCH net-next v2 2/4] net: phy: micrel: Introduce lanphy_modify_page_reg Date: Thu, 24 Jul 2025 22:08:24 +0200 Message-ID: <20250724200826.2662658-3-horatiu.vultur@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250724200826.2662658-1-horatiu.vultur@microchip.com> References: <20250724200826.2662658-1-horatiu.vultur@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" As the name suggests this function modifies the register in an extended page. It has the same parameters as phy_modify_mmd. This function was introduce because there are many places in the code where the registers was read then the value was modified and written back. So replace all this code with this function to make it clear. Signed-off-by: Horatiu Vultur --- drivers/net/phy/micrel.c | 228 +++++++++++++++++++-------------------- 1 file changed, 113 insertions(+), 115 deletions(-) diff --git a/drivers/net/phy/micrel.c b/drivers/net/phy/micrel.c index c6aacf7feb7b0..b04c471c11a4a 100644 --- a/drivers/net/phy/micrel.c +++ b/drivers/net/phy/micrel.c @@ -2838,6 +2838,24 @@ static int lanphy_write_page_reg(struct phy_device *= phydev, int page, u16 addr, return val; } =20 +static int lanphy_modify_page_reg(struct phy_device *phydev, int page, u16= addr, + u16 mask, u16 set) +{ + int new, ret; + + ret =3D lanphy_read_page_reg(phydev, page, addr); + if (ret < 0) + return ret; + + new =3D (ret & ~mask) | set; + if (new =3D=3D ret) + return 0; + + ret =3D lanphy_write_page_reg(phydev, page, addr, new); + + return ret < 0 ? ret : 1; +} + static int lan8814_config_ts_intr(struct phy_device *phydev, bool enable) { u16 val =3D 0; @@ -2926,7 +2944,6 @@ static int lan8814_hwtstamp(struct mii_timestamper *m= ii_ts, struct lan8814_ptp_rx_ts *rx_ts, *tmp; int txcfg =3D 0, rxcfg =3D 0; int pkt_ts_enable; - int tx_mod; =20 ptp_priv->hwts_tx_type =3D config->tx_type; ptp_priv->rx_filter =3D config->rx_filter; @@ -2973,13 +2990,14 @@ static int lan8814_hwtstamp(struct mii_timestamper = *mii_ts, lanphy_write_page_reg(ptp_priv->phydev, 5, PTP_RX_TIMESTAMP_EN, pkt_ts_en= able); lanphy_write_page_reg(ptp_priv->phydev, 5, PTP_TX_TIMESTAMP_EN, pkt_ts_en= able); =20 - tx_mod =3D lanphy_read_page_reg(ptp_priv->phydev, 5, PTP_TX_MOD); if (ptp_priv->hwts_tx_type =3D=3D HWTSTAMP_TX_ONESTEP_SYNC) { - lanphy_write_page_reg(ptp_priv->phydev, 5, PTP_TX_MOD, - tx_mod | PTP_TX_MOD_TX_PTP_SYNC_TS_INSERT_); + lanphy_modify_page_reg(ptp_priv->phydev, 5, PTP_TX_MOD, + PTP_TX_MOD_TX_PTP_SYNC_TS_INSERT_, + PTP_TX_MOD_TX_PTP_SYNC_TS_INSERT_); } else if (ptp_priv->hwts_tx_type =3D=3D HWTSTAMP_TX_ON) { - lanphy_write_page_reg(ptp_priv->phydev, 5, PTP_TX_MOD, - tx_mod & ~PTP_TX_MOD_TX_PTP_SYNC_TS_INSERT_); + lanphy_modify_page_reg(ptp_priv->phydev, 5, PTP_TX_MOD, + PTP_TX_MOD_TX_PTP_SYNC_TS_INSERT_, + 0); } =20 if (config->rx_filter !=3D HWTSTAMP_FILTER_NONE) @@ -3382,73 +3400,66 @@ static void lan8814_ptp_set_reload(struct phy_devic= e *phydev, int event, static void lan8814_ptp_enable_event(struct phy_device *phydev, int event, int pulse_width) { - u16 val; - - val =3D lanphy_read_page_reg(phydev, 4, LAN8814_PTP_GENERAL_CONFIG); - /* Set the pulse width of the event */ - val &=3D ~(LAN8814_PTP_GENERAL_CONFIG_LTC_EVENT_MASK(event)); - /* Make sure that the target clock will be incremented each time when + /* Set the pulse width of the event, + * Make sure that the target clock will be incremented each time when * local time reaches or pass it + * Set the polarity high */ - val |=3D LAN8814_PTP_GENERAL_CONFIG_LTC_EVENT_SET(event, pulse_width); - val &=3D ~(LAN8814_PTP_GENERAL_CONFIG_RELOAD_ADD_X(event)); - /* Set the polarity high */ - val |=3D LAN8814_PTP_GENERAL_CONFIG_POLARITY_X(event); - lanphy_write_page_reg(phydev, 4, LAN8814_PTP_GENERAL_CONFIG, val); + lanphy_modify_page_reg(phydev, 4, LAN8814_PTP_GENERAL_CONFIG, + LAN8814_PTP_GENERAL_CONFIG_LTC_EVENT_MASK(event) | + LAN8814_PTP_GENERAL_CONFIG_LTC_EVENT_SET(event, pulse_width) | + LAN8814_PTP_GENERAL_CONFIG_RELOAD_ADD_X(event) | + LAN8814_PTP_GENERAL_CONFIG_POLARITY_X(event), + LAN8814_PTP_GENERAL_CONFIG_LTC_EVENT_SET(event, pulse_width) | + LAN8814_PTP_GENERAL_CONFIG_POLARITY_X(event)); } =20 static void lan8814_ptp_disable_event(struct phy_device *phydev, int event) { - u16 val; - /* Set target to too far in the future, effectively disabling it */ lan8814_ptp_set_target(phydev, event, 0xFFFFFFFF, 0); =20 /* And then reload once it recheas the target */ - val =3D lanphy_read_page_reg(phydev, 4, LAN8814_PTP_GENERAL_CONFIG); - val |=3D LAN8814_PTP_GENERAL_CONFIG_RELOAD_ADD_X(event); - lanphy_write_page_reg(phydev, 4, LAN8814_PTP_GENERAL_CONFIG, val); + lanphy_modify_page_reg(phydev, 4, LAN8814_PTP_GENERAL_CONFIG, + LAN8814_PTP_GENERAL_CONFIG_RELOAD_ADD_X(event), + LAN8814_PTP_GENERAL_CONFIG_RELOAD_ADD_X(event)); } =20 static void lan8814_ptp_perout_off(struct phy_device *phydev, int pin) { - u16 val; - /* Disable gpio alternate function, * 1: select as gpio, * 0: select alt func */ - val =3D lanphy_read_page_reg(phydev, 4, LAN8814_GPIO_EN_ADDR(pin)); - val |=3D LAN8814_GPIO_EN_BIT(pin); - lanphy_write_page_reg(phydev, 4, LAN8814_GPIO_EN_ADDR(pin), val); + lanphy_modify_page_reg(phydev, 4, LAN8814_GPIO_EN_ADDR(pin), + LAN8814_GPIO_EN_BIT(pin), + LAN8814_GPIO_EN_BIT(pin)); =20 - val =3D lanphy_read_page_reg(phydev, 4, LAN8814_GPIO_DIR_ADDR(pin)); - val &=3D ~LAN8814_GPIO_DIR_BIT(pin); - lanphy_write_page_reg(phydev, 4, LAN8814_GPIO_DIR_ADDR(pin), val); + lanphy_modify_page_reg(phydev, 4, LAN8814_GPIO_DIR_ADDR(pin), + LAN8814_GPIO_DIR_BIT(pin), + 0); =20 - val =3D lanphy_read_page_reg(phydev, 4, LAN8814_GPIO_BUF_ADDR(pin)); - val &=3D ~LAN8814_GPIO_BUF_BIT(pin); - lanphy_write_page_reg(phydev, 4, LAN8814_GPIO_BUF_ADDR(pin), val); + lanphy_modify_page_reg(phydev, 4, LAN8814_GPIO_BUF_ADDR(pin), + LAN8814_GPIO_BUF_BIT(pin), + 0); } =20 static void lan8814_ptp_perout_on(struct phy_device *phydev, int pin) { - int val; - /* Set as gpio output */ - val =3D lanphy_read_page_reg(phydev, 4, LAN8814_GPIO_DIR_ADDR(pin)); - val |=3D LAN8814_GPIO_DIR_BIT(pin); - lanphy_write_page_reg(phydev, 4, LAN8814_GPIO_DIR_ADDR(pin), val); + lanphy_modify_page_reg(phydev, 4, LAN8814_GPIO_DIR_ADDR(pin), + LAN8814_GPIO_DIR_BIT(pin), + LAN8814_GPIO_DIR_BIT(pin)); =20 /* Enable gpio 0:for alternate function, 1:gpio */ - val =3D lanphy_read_page_reg(phydev, 4, LAN8814_GPIO_EN_ADDR(pin)); - val &=3D ~LAN8814_GPIO_EN_BIT(pin); - lanphy_write_page_reg(phydev, 4, LAN8814_GPIO_EN_ADDR(pin), val); + lanphy_modify_page_reg(phydev, 4, LAN8814_GPIO_EN_ADDR(pin), + LAN8814_GPIO_EN_BIT(pin), + 0); =20 /* Set buffer type to push pull */ - val =3D lanphy_read_page_reg(phydev, 4, LAN8814_GPIO_BUF_ADDR(pin)); - val |=3D LAN8814_GPIO_BUF_BIT(pin); - lanphy_write_page_reg(phydev, 4, LAN8814_GPIO_BUF_ADDR(pin), val); + lanphy_modify_page_reg(phydev, 4, LAN8814_GPIO_BUF_ADDR(pin), + LAN8814_GPIO_BUF_BIT(pin), + LAN8814_GPIO_BUF_BIT(pin)); } =20 static int lan8814_ptp_perout(struct ptp_clock_info *ptpci, @@ -3563,61 +3574,59 @@ static int lan8814_ptp_perout(struct ptp_clock_info= *ptpci, =20 static void lan8814_ptp_extts_on(struct phy_device *phydev, int pin, u32 f= lags) { - u16 tmp; - /* Set as gpio input */ - tmp =3D lanphy_read_page_reg(phydev, 4, LAN8814_GPIO_DIR_ADDR(pin)); - tmp &=3D ~LAN8814_GPIO_DIR_BIT(pin); - lanphy_write_page_reg(phydev, 4, LAN8814_GPIO_DIR_ADDR(pin), tmp); + lanphy_modify_page_reg(phydev, 4, LAN8814_GPIO_DIR_ADDR(pin), + LAN8814_GPIO_DIR_BIT(pin), + 0); =20 /* Map the pin to ltc pin 0 of the capture map registers */ - tmp =3D lanphy_read_page_reg(phydev, 4, PTP_GPIO_CAP_MAP_LO); - tmp |=3D pin; - lanphy_write_page_reg(phydev, 4, PTP_GPIO_CAP_MAP_LO, tmp); + lanphy_modify_page_reg(phydev, 4, PTP_GPIO_CAP_MAP_LO, + pin, + pin); =20 /* Enable capture on the edges of the ltc pin */ - tmp =3D lanphy_read_page_reg(phydev, 4, PTP_GPIO_CAP_EN); if (flags & PTP_RISING_EDGE) - tmp |=3D PTP_GPIO_CAP_EN_GPIO_RE_CAPTURE_ENABLE(0); + lanphy_modify_page_reg(phydev, 4, PTP_GPIO_CAP_EN, + PTP_GPIO_CAP_EN_GPIO_RE_CAPTURE_ENABLE(0), + PTP_GPIO_CAP_EN_GPIO_RE_CAPTURE_ENABLE(0)); if (flags & PTP_FALLING_EDGE) - tmp |=3D PTP_GPIO_CAP_EN_GPIO_FE_CAPTURE_ENABLE(0); - lanphy_write_page_reg(phydev, 4, PTP_GPIO_CAP_EN, tmp); + lanphy_modify_page_reg(phydev, 4, PTP_GPIO_CAP_EN, + PTP_GPIO_CAP_EN_GPIO_FE_CAPTURE_ENABLE(0), + PTP_GPIO_CAP_EN_GPIO_FE_CAPTURE_ENABLE(0)); =20 /* Enable interrupt top interrupt */ - tmp =3D lanphy_read_page_reg(phydev, 4, PTP_COMMON_INT_ENA); - tmp |=3D PTP_COMMON_INT_ENA_GPIO_CAP_EN; - lanphy_write_page_reg(phydev, 4, PTP_COMMON_INT_ENA, tmp); + lanphy_modify_page_reg(phydev, 4, PTP_COMMON_INT_ENA, + PTP_COMMON_INT_ENA_GPIO_CAP_EN, + PTP_COMMON_INT_ENA_GPIO_CAP_EN); } =20 static void lan8814_ptp_extts_off(struct phy_device *phydev, int pin) { - u16 tmp; - /* Set as gpio out */ - tmp =3D lanphy_read_page_reg(phydev, 4, LAN8814_GPIO_DIR_ADDR(pin)); - tmp |=3D LAN8814_GPIO_DIR_BIT(pin); - lanphy_write_page_reg(phydev, 4, LAN8814_GPIO_DIR_ADDR(pin), tmp); + lanphy_modify_page_reg(phydev, 4, LAN8814_GPIO_DIR_ADDR(pin), + LAN8814_GPIO_DIR_BIT(pin), + LAN8814_GPIO_DIR_BIT(pin)); =20 /* Enable alternate, 0:for alternate function, 1:gpio */ - tmp =3D lanphy_read_page_reg(phydev, 4, LAN8814_GPIO_EN_ADDR(pin)); - tmp &=3D ~LAN8814_GPIO_EN_BIT(pin); - lanphy_write_page_reg(phydev, 4, LAN8814_GPIO_EN_ADDR(pin), tmp); + lanphy_modify_page_reg(phydev, 4, LAN8814_GPIO_EN_ADDR(pin), + LAN8814_GPIO_EN_BIT(pin), + 0); =20 /* Clear the mapping of pin to registers 0 of the capture registers */ - tmp =3D lanphy_read_page_reg(phydev, 4, PTP_GPIO_CAP_MAP_LO); - tmp &=3D ~GENMASK(3, 0); - lanphy_write_page_reg(phydev, 4, PTP_GPIO_CAP_MAP_LO, tmp); + lanphy_modify_page_reg(phydev, 4, PTP_GPIO_CAP_MAP_LO, + GENMASK(3, 0), + 0); =20 /* Disable capture on both of the edges */ - tmp =3D lanphy_read_page_reg(phydev, 4, PTP_GPIO_CAP_EN); - tmp &=3D ~PTP_GPIO_CAP_EN_GPIO_RE_CAPTURE_ENABLE(pin); - tmp &=3D ~PTP_GPIO_CAP_EN_GPIO_FE_CAPTURE_ENABLE(pin); - lanphy_write_page_reg(phydev, 4, PTP_GPIO_CAP_EN, tmp); + lanphy_modify_page_reg(phydev, 4, PTP_GPIO_CAP_EN, + PTP_GPIO_CAP_EN_GPIO_RE_CAPTURE_ENABLE(pin) | + PTP_GPIO_CAP_EN_GPIO_FE_CAPTURE_ENABLE(pin), + 0); =20 /* Disable interrupt top interrupt */ - tmp =3D lanphy_read_page_reg(phydev, 4, PTP_COMMON_INT_ENA); - tmp &=3D ~PTP_COMMON_INT_ENA_GPIO_CAP_EN; - lanphy_write_page_reg(phydev, 4, PTP_COMMON_INT_ENA, tmp); + lanphy_modify_page_reg(phydev, 4, PTP_COMMON_INT_ENA, + PTP_COMMON_INT_ENA_GPIO_CAP_EN, + 0); } =20 static int lan8814_ptp_extts(struct ptp_clock_info *ptpci, @@ -3857,9 +3866,9 @@ static int lan8814_gpio_process_cap(struct lan8814_sh= ared_priv *shared) /* This is 0 because whatever was the input pin it was mapped it to * ltc gpio pin 0 */ - tmp =3D lanphy_read_page_reg(phydev, 4, PTP_GPIO_SEL); - tmp |=3D PTP_GPIO_SEL_GPIO_SEL(0); - lanphy_write_page_reg(phydev, 4, PTP_GPIO_SEL, tmp); + lanphy_modify_page_reg(phydev, 4, PTP_GPIO_SEL, + PTP_GPIO_SEL_GPIO_SEL(0), + PTP_GPIO_SEL_GPIO_SEL(0)); =20 tmp =3D lanphy_read_page_reg(phydev, 4, PTP_GPIO_CAP_STS); if (!(tmp & PTP_GPIO_CAP_STS_PTP_GPIO_RE_STS(0)) && @@ -3906,13 +3915,10 @@ static int lan8814_handle_gpio_interrupt(struct phy= _device *phydev, u16 status) =20 static int lan8804_config_init(struct phy_device *phydev) { - int val; - /* MDI-X setting for swap A,B transmit */ - val =3D lanphy_read_page_reg(phydev, 2, LAN8804_ALIGN_SWAP); - val &=3D ~LAN8804_ALIGN_TX_A_B_SWAP_MASK; - val |=3D LAN8804_ALIGN_TX_A_B_SWAP; - lanphy_write_page_reg(phydev, 2, LAN8804_ALIGN_SWAP, val); + lanphy_modify_page_reg(phydev, 2, LAN8804_ALIGN_SWAP, + LAN8804_ALIGN_TX_A_B_SWAP_MASK, + LAN8804_ALIGN_TX_A_B_SWAP); =20 /* Make sure that the PHY will not stop generating the clock when the * link partner goes down @@ -4054,7 +4060,6 @@ static void lan8814_ptp_init(struct phy_device *phyde= v) { struct kszphy_priv *priv =3D phydev->priv; struct kszphy_ptp_priv *ptp_priv =3D &priv->ptp_priv; - u32 temp; =20 if (!IS_ENABLED(CONFIG_PTP_1588_CLOCK) || !IS_ENABLED(CONFIG_NETWORK_PHY_TIMESTAMPING)) @@ -4062,13 +4067,13 @@ static void lan8814_ptp_init(struct phy_device *phy= dev) =20 lanphy_write_page_reg(phydev, 5, TSU_HARD_RESET, TSU_HARD_RESET_); =20 - temp =3D lanphy_read_page_reg(phydev, 5, PTP_TX_MOD); - temp |=3D PTP_TX_MOD_BAD_UDPV4_CHKSUM_FORCE_FCS_DIS_; - lanphy_write_page_reg(phydev, 5, PTP_TX_MOD, temp); + lanphy_modify_page_reg(phydev, 5, PTP_TX_MOD, + PTP_TX_MOD_BAD_UDPV4_CHKSUM_FORCE_FCS_DIS_, + PTP_TX_MOD_BAD_UDPV4_CHKSUM_FORCE_FCS_DIS_); =20 - temp =3D lanphy_read_page_reg(phydev, 5, PTP_RX_MOD); - temp |=3D PTP_RX_MOD_BAD_UDPV4_CHKSUM_FORCE_FCS_DIS_; - lanphy_write_page_reg(phydev, 5, PTP_RX_MOD, temp); + lanphy_modify_page_reg(phydev, 5, PTP_RX_MOD, + PTP_RX_MOD_BAD_UDPV4_CHKSUM_FORCE_FCS_DIS_, + PTP_RX_MOD_BAD_UDPV4_CHKSUM_FORCE_FCS_DIS_); =20 lanphy_write_page_reg(phydev, 5, PTP_RX_PARSE_CONFIG, 0); lanphy_write_page_reg(phydev, 5, PTP_TX_PARSE_CONFIG, 0); @@ -4194,23 +4199,21 @@ static void lan8814_setup_led(struct phy_device *ph= ydev, int val) static int lan8814_config_init(struct phy_device *phydev) { struct kszphy_priv *lan8814 =3D phydev->priv; - int val; =20 /* Reset the PHY */ - val =3D lanphy_read_page_reg(phydev, 4, LAN8814_QSGMII_SOFT_RESET); - val |=3D LAN8814_QSGMII_SOFT_RESET_BIT; - lanphy_write_page_reg(phydev, 4, LAN8814_QSGMII_SOFT_RESET, val); + lanphy_modify_page_reg(phydev, 4, LAN8814_QSGMII_SOFT_RESET, + LAN8814_QSGMII_SOFT_RESET_BIT, + LAN8814_QSGMII_SOFT_RESET_BIT); =20 /* Disable ANEG with QSGMII PCS Host side */ - val =3D lanphy_read_page_reg(phydev, 5, LAN8814_QSGMII_PCS1G_ANEG_CONFIG); - val &=3D ~LAN8814_QSGMII_PCS1G_ANEG_CONFIG_ANEG_ENA; - lanphy_write_page_reg(phydev, 5, LAN8814_QSGMII_PCS1G_ANEG_CONFIG, val); + lanphy_modify_page_reg(phydev, 4, LAN8814_QSGMII_PCS1G_ANEG_CONFIG, + LAN8814_QSGMII_PCS1G_ANEG_CONFIG_ANEG_ENA, + 0); =20 /* MDI-X setting for swap A,B transmit */ - val =3D lanphy_read_page_reg(phydev, 2, LAN8814_ALIGN_SWAP); - val &=3D ~LAN8814_ALIGN_TX_A_B_SWAP_MASK; - val |=3D LAN8814_ALIGN_TX_A_B_SWAP; - lanphy_write_page_reg(phydev, 2, LAN8814_ALIGN_SWAP, val); + lanphy_modify_page_reg(phydev, 2, LAN8814_ALIGN_SWAP, + LAN8814_ALIGN_TX_A_B_SWAP_MASK, + LAN8814_ALIGN_TX_A_B_SWAP); =20 if (lan8814->led_mode >=3D 0) lan8814_setup_led(phydev, lan8814->led_mode); @@ -4241,29 +4244,24 @@ static int lan8814_release_coma_mode(struct phy_dev= ice *phydev) =20 static void lan8814_clear_2psp_bit(struct phy_device *phydev) { - u16 val; - /* It was noticed that when traffic is passing through the PHY and the * cable is removed then the LED was still one even though there is no * link */ - val =3D lanphy_read_page_reg(phydev, 2, LAN8814_EEE_STATE); - val &=3D ~LAN8814_EEE_STATE_MASK2P5P; - lanphy_write_page_reg(phydev, 2, LAN8814_EEE_STATE, val); + lanphy_modify_page_reg(phydev, 2, LAN8814_EEE_STATE, + LAN8814_EEE_STATE_MASK2P5P, + 0); } =20 static void lan8814_update_meas_time(struct phy_device *phydev) { - u16 val; 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In all the functions the page was hardcoded. Replace the hardcoded values with defines to make it more clear what are those parameters. Signed-off-by: Horatiu Vultur --- drivers/net/phy/micrel.c | 291 +++++++++++++++++++++++++-------------- 1 file changed, 185 insertions(+), 106 deletions(-) diff --git a/drivers/net/phy/micrel.c b/drivers/net/phy/micrel.c index b04c471c11a4a..d20f028106b7d 100644 --- a/drivers/net/phy/micrel.c +++ b/drivers/net/phy/micrel.c @@ -2788,6 +2788,13 @@ static int ksz886x_cable_test_get_status(struct phy_= device *phydev, return ret; } =20 +#define LAN_EXT_PAGE_0 0 +#define LAN_EXT_PAGE_1 1 +#define LAN_EXT_PAGE_2 2 +#define LAN_EXT_PAGE_4 4 +#define LAN_EXT_PAGE_5 5 +#define LAN_EXT_PAGE_31 31 + #define LAN_EXT_PAGE_ACCESS_CONTROL 0x16 #define LAN_EXT_PAGE_ACCESS_ADDRESS_DATA 0x17 #define LAN_EXT_PAGE_ACCESS_CTRL_EP_FUNC 0x4000 @@ -2866,35 +2873,46 @@ static int lan8814_config_ts_intr(struct phy_device= *phydev, bool enable) PTP_TSU_INT_EN_PTP_RX_TS_EN_ | PTP_TSU_INT_EN_PTP_RX_TS_OVRFL_EN_; =20 - return lanphy_write_page_reg(phydev, 5, PTP_TSU_INT_EN, val); + return lanphy_write_page_reg(phydev, LAN_EXT_PAGE_5, PTP_TSU_INT_EN, + val); } =20 static void lan8814_ptp_rx_ts_get(struct phy_device *phydev, u32 *seconds, u32 *nano_seconds, u16 *seq_id) { - *seconds =3D lanphy_read_page_reg(phydev, 5, PTP_RX_INGRESS_SEC_HI); + *seconds =3D lanphy_read_page_reg(phydev, LAN_EXT_PAGE_5, + PTP_RX_INGRESS_SEC_HI); *seconds =3D (*seconds << 16) | - lanphy_read_page_reg(phydev, 5, PTP_RX_INGRESS_SEC_LO); + lanphy_read_page_reg(phydev, LAN_EXT_PAGE_5, + PTP_RX_INGRESS_SEC_LO); =20 - *nano_seconds =3D lanphy_read_page_reg(phydev, 5, PTP_RX_INGRESS_NS_HI); + *nano_seconds =3D lanphy_read_page_reg(phydev, LAN_EXT_PAGE_5 + , PTP_RX_INGRESS_NS_HI); *nano_seconds =3D ((*nano_seconds & 0x3fff) << 16) | - lanphy_read_page_reg(phydev, 5, PTP_RX_INGRESS_NS_LO); + lanphy_read_page_reg(phydev, LAN_EXT_PAGE_5, + PTP_RX_INGRESS_NS_LO); =20 - *seq_id =3D lanphy_read_page_reg(phydev, 5, PTP_RX_MSG_HEADER2); + *seq_id =3D lanphy_read_page_reg(phydev, LAN_EXT_PAGE_5, + PTP_RX_MSG_HEADER2); } =20 static void lan8814_ptp_tx_ts_get(struct phy_device *phydev, u32 *seconds, u32 *nano_seconds, u16 *seq_id) { - *seconds =3D lanphy_read_page_reg(phydev, 5, PTP_TX_EGRESS_SEC_HI); + *seconds =3D lanphy_read_page_reg(phydev, LAN_EXT_PAGE_5, + PTP_TX_EGRESS_SEC_HI); *seconds =3D *seconds << 16 | - lanphy_read_page_reg(phydev, 5, PTP_TX_EGRESS_SEC_LO); + lanphy_read_page_reg(phydev, LAN_EXT_PAGE_5, + PTP_TX_EGRESS_SEC_LO); =20 - *nano_seconds =3D lanphy_read_page_reg(phydev, 5, PTP_TX_EGRESS_NS_HI); + *nano_seconds =3D lanphy_read_page_reg(phydev, LAN_EXT_PAGE_5, + PTP_TX_EGRESS_NS_HI); *nano_seconds =3D ((*nano_seconds & 0x3fff) << 16) | - lanphy_read_page_reg(phydev, 5, PTP_TX_EGRESS_NS_LO); + lanphy_read_page_reg(phydev, LAN_EXT_PAGE_5, + PTP_TX_EGRESS_NS_LO); =20 - *seq_id =3D lanphy_read_page_reg(phydev, 5, PTP_TX_MSG_HEADER2); + *seq_id =3D lanphy_read_page_reg(phydev, LAN_EXT_PAGE_5, + PTP_TX_MSG_HEADER2); } =20 static int lan8814_ts_info(struct mii_timestamper *mii_ts, struct kernel_e= thtool_ts_info *info) @@ -2928,11 +2946,11 @@ static void lan8814_flush_fifo(struct phy_device *p= hydev, bool egress) int i; =20 for (i =3D 0; i < FIFO_SIZE; ++i) - lanphy_read_page_reg(phydev, 5, + lanphy_read_page_reg(phydev, LAN_EXT_PAGE_5, egress ? PTP_TX_MSG_HEADER2 : PTP_RX_MSG_HEADER2); =20 /* Read to clear overflow status bit */ - lanphy_read_page_reg(phydev, 5, PTP_TSU_INT_STS); + lanphy_read_page_reg(phydev, LAN_EXT_PAGE_5, PTP_TSU_INT_STS); } =20 static int lan8814_hwtstamp(struct mii_timestamper *mii_ts, @@ -2982,20 +3000,26 @@ static int lan8814_hwtstamp(struct mii_timestamper = *mii_ts, rxcfg |=3D PTP_RX_PARSE_CONFIG_IPV4_EN_ | PTP_RX_PARSE_CONFIG_IPV6_EN_; txcfg |=3D PTP_TX_PARSE_CONFIG_IPV4_EN_ | PTP_TX_PARSE_CONFIG_IPV6_EN_; } - lanphy_write_page_reg(ptp_priv->phydev, 5, PTP_RX_PARSE_CONFIG, rxcfg); - lanphy_write_page_reg(ptp_priv->phydev, 5, PTP_TX_PARSE_CONFIG, txcfg); + lanphy_write_page_reg(ptp_priv->phydev, LAN_EXT_PAGE_5, + PTP_RX_PARSE_CONFIG, rxcfg); + lanphy_write_page_reg(ptp_priv->phydev, LAN_EXT_PAGE_5, + PTP_TX_PARSE_CONFIG, txcfg); =20 pkt_ts_enable =3D PTP_TIMESTAMP_EN_SYNC_ | PTP_TIMESTAMP_EN_DREQ_ | PTP_TIMESTAMP_EN_PDREQ_ | PTP_TIMESTAMP_EN_PDRES_; - lanphy_write_page_reg(ptp_priv->phydev, 5, PTP_RX_TIMESTAMP_EN, pkt_ts_en= able); - lanphy_write_page_reg(ptp_priv->phydev, 5, PTP_TX_TIMESTAMP_EN, pkt_ts_en= able); + lanphy_write_page_reg(ptp_priv->phydev, LAN_EXT_PAGE_5, + PTP_RX_TIMESTAMP_EN, pkt_ts_enable); + lanphy_write_page_reg(ptp_priv->phydev, LAN_EXT_PAGE_5, + PTP_TX_TIMESTAMP_EN, pkt_ts_enable); =20 if (ptp_priv->hwts_tx_type =3D=3D HWTSTAMP_TX_ONESTEP_SYNC) { - lanphy_modify_page_reg(ptp_priv->phydev, 5, PTP_TX_MOD, + lanphy_modify_page_reg(ptp_priv->phydev, LAN_EXT_PAGE_5, + PTP_TX_MOD, PTP_TX_MOD_TX_PTP_SYNC_TS_INSERT_, PTP_TX_MOD_TX_PTP_SYNC_TS_INSERT_); } else if (ptp_priv->hwts_tx_type =3D=3D HWTSTAMP_TX_ON) { - lanphy_modify_page_reg(ptp_priv->phydev, 5, PTP_TX_MOD, + lanphy_modify_page_reg(ptp_priv->phydev, LAN_EXT_PAGE_5, + PTP_TX_MOD, PTP_TX_MOD_TX_PTP_SYNC_TS_INSERT_, 0); } @@ -3119,29 +3143,41 @@ static bool lan8814_rxtstamp(struct mii_timestamper= *mii_ts, struct sk_buff *skb static void lan8814_ptp_clock_set(struct phy_device *phydev, time64_t sec, u32 nsec) { - lanphy_write_page_reg(phydev, 4, PTP_CLOCK_SET_SEC_LO, lower_16_bits(sec)= ); - lanphy_write_page_reg(phydev, 4, PTP_CLOCK_SET_SEC_MID, upper_16_bits(sec= )); - lanphy_write_page_reg(phydev, 4, PTP_CLOCK_SET_SEC_HI, upper_32_bits(sec)= ); - lanphy_write_page_reg(phydev, 4, PTP_CLOCK_SET_NS_LO, lower_16_bits(nsec)= ); - lanphy_write_page_reg(phydev, 4, PTP_CLOCK_SET_NS_HI, upper_16_bits(nsec)= ); + lanphy_write_page_reg(phydev, LAN_EXT_PAGE_4, PTP_CLOCK_SET_SEC_LO, + lower_16_bits(sec)); + lanphy_write_page_reg(phydev, LAN_EXT_PAGE_4, PTP_CLOCK_SET_SEC_MID, + upper_16_bits(sec)); + lanphy_write_page_reg(phydev, LAN_EXT_PAGE_4, PTP_CLOCK_SET_SEC_HI, + upper_32_bits(sec)); + lanphy_write_page_reg(phydev, LAN_EXT_PAGE_4, PTP_CLOCK_SET_NS_LO, + lower_16_bits(nsec)); + lanphy_write_page_reg(phydev, LAN_EXT_PAGE_4, PTP_CLOCK_SET_NS_HI, + upper_16_bits(nsec)); =20 - lanphy_write_page_reg(phydev, 4, PTP_CMD_CTL, PTP_CMD_CTL_PTP_CLOCK_LOAD_= ); + lanphy_write_page_reg(phydev, LAN_EXT_PAGE_4, PTP_CMD_CTL, + PTP_CMD_CTL_PTP_CLOCK_LOAD_); } =20 static void lan8814_ptp_clock_get(struct phy_device *phydev, time64_t *sec, u32 *nsec) { - lanphy_write_page_reg(phydev, 4, PTP_CMD_CTL, PTP_CMD_CTL_PTP_CLOCK_READ_= ); + lanphy_write_page_reg(phydev, LAN_EXT_PAGE_4, PTP_CMD_CTL, + PTP_CMD_CTL_PTP_CLOCK_READ_); =20 - *sec =3D lanphy_read_page_reg(phydev, 4, PTP_CLOCK_READ_SEC_HI); + *sec =3D lanphy_read_page_reg(phydev, LAN_EXT_PAGE_4, + PTP_CLOCK_READ_SEC_HI); *sec <<=3D 16; - *sec |=3D lanphy_read_page_reg(phydev, 4, PTP_CLOCK_READ_SEC_MID); + *sec |=3D lanphy_read_page_reg(phydev, LAN_EXT_PAGE_4, + PTP_CLOCK_READ_SEC_MID); *sec <<=3D 16; - *sec |=3D lanphy_read_page_reg(phydev, 4, PTP_CLOCK_READ_SEC_LO); + *sec |=3D lanphy_read_page_reg(phydev, LAN_EXT_PAGE_4, + PTP_CLOCK_READ_SEC_LO); =20 - *nsec =3D lanphy_read_page_reg(phydev, 4, PTP_CLOCK_READ_NS_HI); + *nsec =3D lanphy_read_page_reg(phydev, LAN_EXT_PAGE_4, + PTP_CLOCK_READ_NS_HI); *nsec <<=3D 16; - *nsec |=3D lanphy_read_page_reg(phydev, 4, PTP_CLOCK_READ_NS_LO); + *nsec |=3D lanphy_read_page_reg(phydev, LAN_EXT_PAGE_4, + PTP_CLOCK_READ_NS_LO); } =20 static int lan8814_ptpci_gettime64(struct ptp_clock_info *ptpci, @@ -3180,14 +3216,18 @@ static void lan8814_ptp_set_target(struct phy_devic= e *phydev, int event, s64 start_sec, u32 start_nsec) { /* Set the start time */ - lanphy_write_page_reg(phydev, 4, LAN8814_PTP_CLOCK_TARGET_SEC_LO(event), + lanphy_write_page_reg(phydev, LAN_EXT_PAGE_4, + LAN8814_PTP_CLOCK_TARGET_SEC_LO(event), lower_16_bits(start_sec)); - lanphy_write_page_reg(phydev, 4, LAN8814_PTP_CLOCK_TARGET_SEC_HI(event), + lanphy_write_page_reg(phydev, LAN_EXT_PAGE_4, + LAN8814_PTP_CLOCK_TARGET_SEC_HI(event), upper_16_bits(start_sec)); =20 - lanphy_write_page_reg(phydev, 4, LAN8814_PTP_CLOCK_TARGET_NS_LO(event), + lanphy_write_page_reg(phydev, LAN_EXT_PAGE_4, + LAN8814_PTP_CLOCK_TARGET_NS_LO(event), lower_16_bits(start_nsec)); - lanphy_write_page_reg(phydev, 4, LAN8814_PTP_CLOCK_TARGET_NS_HI(event), + lanphy_write_page_reg(phydev, LAN_EXT_PAGE_4, + LAN8814_PTP_CLOCK_TARGET_NS_HI(event), upper_16_bits(start_nsec) & 0x3fff); } =20 @@ -3285,9 +3325,11 @@ static void lan8814_ptp_clock_step(struct phy_device= *phydev, adjustment_value_lo =3D adjustment_value & 0xffff; adjustment_value_hi =3D (adjustment_value >> 16) & 0x3fff; =20 - lanphy_write_page_reg(phydev, 4, PTP_LTC_STEP_ADJ_LO, + lanphy_write_page_reg(phydev, LAN_EXT_PAGE_4, + PTP_LTC_STEP_ADJ_LO, adjustment_value_lo); - lanphy_write_page_reg(phydev, 4, PTP_LTC_STEP_ADJ_HI, + lanphy_write_page_reg(phydev, LAN_EXT_PAGE_4, + PTP_LTC_STEP_ADJ_HI, PTP_LTC_STEP_ADJ_DIR_ | adjustment_value_hi); seconds -=3D ((s32)adjustment_value); @@ -3305,9 +3347,11 @@ static void lan8814_ptp_clock_step(struct phy_device= *phydev, adjustment_value_lo =3D adjustment_value & 0xffff; adjustment_value_hi =3D (adjustment_value >> 16) & 0x3fff; =20 - lanphy_write_page_reg(phydev, 4, PTP_LTC_STEP_ADJ_LO, + lanphy_write_page_reg(phydev, LAN_EXT_PAGE_4, + PTP_LTC_STEP_ADJ_LO, adjustment_value_lo); - lanphy_write_page_reg(phydev, 4, PTP_LTC_STEP_ADJ_HI, + lanphy_write_page_reg(phydev, LAN_EXT_PAGE_4, + PTP_LTC_STEP_ADJ_HI, adjustment_value_hi); seconds +=3D ((s32)adjustment_value); =20 @@ -3315,7 +3359,7 @@ static void lan8814_ptp_clock_step(struct phy_device = *phydev, set_seconds +=3D adjustment_value; lan8814_ptp_update_target(phydev, set_seconds); } - lanphy_write_page_reg(phydev, 4, PTP_CMD_CTL, + lanphy_write_page_reg(phydev, LAN_EXT_PAGE_4, PTP_CMD_CTL, PTP_CMD_CTL_PTP_LTC_STEP_SEC_); } if (nano_seconds) { @@ -3325,12 +3369,14 @@ static void lan8814_ptp_clock_step(struct phy_devic= e *phydev, nano_seconds_lo =3D nano_seconds & 0xffff; nano_seconds_hi =3D (nano_seconds >> 16) & 0x3fff; =20 - lanphy_write_page_reg(phydev, 4, PTP_LTC_STEP_ADJ_LO, + lanphy_write_page_reg(phydev, LAN_EXT_PAGE_4, + PTP_LTC_STEP_ADJ_LO, nano_seconds_lo); - lanphy_write_page_reg(phydev, 4, PTP_LTC_STEP_ADJ_HI, + lanphy_write_page_reg(phydev, LAN_EXT_PAGE_4, + PTP_LTC_STEP_ADJ_HI, PTP_LTC_STEP_ADJ_DIR_ | nano_seconds_hi); - lanphy_write_page_reg(phydev, 4, PTP_CMD_CTL, + lanphy_write_page_reg(phydev, LAN_EXT_PAGE_4, PTP_CMD_CTL, PTP_CMD_CTL_PTP_LTC_STEP_NSEC_); } } @@ -3372,8 +3418,10 @@ static int lan8814_ptpci_adjfine(struct ptp_clock_in= fo *ptpci, long scaled_ppm) kszphy_rate_adj_hi |=3D PTP_CLOCK_RATE_ADJ_DIR_; =20 mutex_lock(&shared->shared_lock); - lanphy_write_page_reg(phydev, 4, PTP_CLOCK_RATE_ADJ_HI, kszphy_rate_adj_h= i); - lanphy_write_page_reg(phydev, 4, PTP_CLOCK_RATE_ADJ_LO, kszphy_rate_adj_l= o); + lanphy_write_page_reg(phydev, LAN_EXT_PAGE_4, PTP_CLOCK_RATE_ADJ_HI, + kszphy_rate_adj_hi); + lanphy_write_page_reg(phydev, LAN_EXT_PAGE_4, PTP_CLOCK_RATE_ADJ_LO, + kszphy_rate_adj_lo); mutex_unlock(&shared->shared_lock); =20 return 0; @@ -3382,17 +3430,17 @@ static int lan8814_ptpci_adjfine(struct ptp_clock_i= nfo *ptpci, long scaled_ppm) static void lan8814_ptp_set_reload(struct phy_device *phydev, int event, s64 period_sec, u32 period_nsec) { - lanphy_write_page_reg(phydev, 4, + lanphy_write_page_reg(phydev, LAN_EXT_PAGE_4, LAN8814_PTP_CLOCK_TARGET_RELOAD_SEC_LO(event), lower_16_bits(period_sec)); - lanphy_write_page_reg(phydev, 4, + lanphy_write_page_reg(phydev, LAN_EXT_PAGE_4, LAN8814_PTP_CLOCK_TARGET_RELOAD_SEC_HI(event), upper_16_bits(period_sec)); =20 - lanphy_write_page_reg(phydev, 4, + lanphy_write_page_reg(phydev, LAN_EXT_PAGE_4, LAN8814_PTP_CLOCK_TARGET_RELOAD_NS_LO(event), lower_16_bits(period_nsec)); - lanphy_write_page_reg(phydev, 4, + lanphy_write_page_reg(phydev, LAN_EXT_PAGE_4, LAN8814_PTP_CLOCK_TARGET_RELOAD_NS_HI(event), upper_16_bits(period_nsec) & 0x3fff); } @@ -3405,7 +3453,7 @@ static void lan8814_ptp_enable_event(struct phy_devic= e *phydev, int event, * local time reaches or pass it * Set the polarity high */ - lanphy_modify_page_reg(phydev, 4, LAN8814_PTP_GENERAL_CONFIG, + lanphy_modify_page_reg(phydev, LAN_EXT_PAGE_4, LAN8814_PTP_GENERAL_CONFIG, LAN8814_PTP_GENERAL_CONFIG_LTC_EVENT_MASK(event) | LAN8814_PTP_GENERAL_CONFIG_LTC_EVENT_SET(event, pulse_width) | LAN8814_PTP_GENERAL_CONFIG_RELOAD_ADD_X(event) | @@ -3420,7 +3468,7 @@ static void lan8814_ptp_disable_event(struct phy_devi= ce *phydev, int event) lan8814_ptp_set_target(phydev, event, 0xFFFFFFFF, 0); =20 /* And then reload once it recheas the target */ - lanphy_modify_page_reg(phydev, 4, LAN8814_PTP_GENERAL_CONFIG, + lanphy_modify_page_reg(phydev, LAN_EXT_PAGE_4, LAN8814_PTP_GENERAL_CONFIG, LAN8814_PTP_GENERAL_CONFIG_RELOAD_ADD_X(event), LAN8814_PTP_GENERAL_CONFIG_RELOAD_ADD_X(event)); } @@ -3431,15 +3479,18 @@ static void lan8814_ptp_perout_off(struct phy_devic= e *phydev, int pin) * 1: select as gpio, * 0: select alt func */ - lanphy_modify_page_reg(phydev, 4, LAN8814_GPIO_EN_ADDR(pin), + lanphy_modify_page_reg(phydev, LAN_EXT_PAGE_4, + LAN8814_GPIO_EN_ADDR(pin), LAN8814_GPIO_EN_BIT(pin), LAN8814_GPIO_EN_BIT(pin)); =20 - lanphy_modify_page_reg(phydev, 4, LAN8814_GPIO_DIR_ADDR(pin), + lanphy_modify_page_reg(phydev, LAN_EXT_PAGE_4, + LAN8814_GPIO_DIR_ADDR(pin), LAN8814_GPIO_DIR_BIT(pin), 0); =20 - lanphy_modify_page_reg(phydev, 4, LAN8814_GPIO_BUF_ADDR(pin), + lanphy_modify_page_reg(phydev, LAN_EXT_PAGE_4, + LAN8814_GPIO_BUF_ADDR(pin), LAN8814_GPIO_BUF_BIT(pin), 0); } @@ -3447,17 +3498,20 @@ static void lan8814_ptp_perout_off(struct phy_devic= e *phydev, int pin) static void lan8814_ptp_perout_on(struct phy_device *phydev, int pin) { /* Set as gpio output */ - lanphy_modify_page_reg(phydev, 4, LAN8814_GPIO_DIR_ADDR(pin), + lanphy_modify_page_reg(phydev, LAN_EXT_PAGE_4, + LAN8814_GPIO_DIR_ADDR(pin), LAN8814_GPIO_DIR_BIT(pin), LAN8814_GPIO_DIR_BIT(pin)); =20 /* Enable gpio 0:for alternate function, 1:gpio */ - lanphy_modify_page_reg(phydev, 4, LAN8814_GPIO_EN_ADDR(pin), + lanphy_modify_page_reg(phydev, LAN_EXT_PAGE_4, + LAN8814_GPIO_EN_ADDR(pin), LAN8814_GPIO_EN_BIT(pin), 0); =20 /* Set buffer type to push pull */ - lanphy_modify_page_reg(phydev, 4, LAN8814_GPIO_BUF_ADDR(pin), + lanphy_modify_page_reg(phydev, LAN_EXT_PAGE_4, + LAN8814_GPIO_BUF_ADDR(pin), LAN8814_GPIO_BUF_BIT(pin), LAN8814_GPIO_BUF_BIT(pin)); } @@ -3575,27 +3629,28 @@ static int lan8814_ptp_perout(struct ptp_clock_info= *ptpci, static void lan8814_ptp_extts_on(struct phy_device *phydev, int pin, u32 f= lags) { /* Set as gpio input */ - lanphy_modify_page_reg(phydev, 4, LAN8814_GPIO_DIR_ADDR(pin), + lanphy_modify_page_reg(phydev, LAN_EXT_PAGE_4, + LAN8814_GPIO_DIR_ADDR(pin), LAN8814_GPIO_DIR_BIT(pin), 0); =20 /* Map the pin to ltc pin 0 of the capture map registers */ - lanphy_modify_page_reg(phydev, 4, PTP_GPIO_CAP_MAP_LO, + lanphy_modify_page_reg(phydev, LAN_EXT_PAGE_4, PTP_GPIO_CAP_MAP_LO, pin, pin); =20 /* Enable capture on the edges of the ltc pin */ if (flags & PTP_RISING_EDGE) - lanphy_modify_page_reg(phydev, 4, PTP_GPIO_CAP_EN, + lanphy_modify_page_reg(phydev, LAN_EXT_PAGE_4, PTP_GPIO_CAP_EN, PTP_GPIO_CAP_EN_GPIO_RE_CAPTURE_ENABLE(0), PTP_GPIO_CAP_EN_GPIO_RE_CAPTURE_ENABLE(0)); if (flags & PTP_FALLING_EDGE) - lanphy_modify_page_reg(phydev, 4, PTP_GPIO_CAP_EN, + lanphy_modify_page_reg(phydev, LAN_EXT_PAGE_4, PTP_GPIO_CAP_EN, PTP_GPIO_CAP_EN_GPIO_FE_CAPTURE_ENABLE(0), PTP_GPIO_CAP_EN_GPIO_FE_CAPTURE_ENABLE(0)); =20 /* Enable interrupt top interrupt */ - lanphy_modify_page_reg(phydev, 4, PTP_COMMON_INT_ENA, + lanphy_modify_page_reg(phydev, LAN_EXT_PAGE_4, PTP_COMMON_INT_ENA, PTP_COMMON_INT_ENA_GPIO_CAP_EN, PTP_COMMON_INT_ENA_GPIO_CAP_EN); } @@ -3603,28 +3658,31 @@ static void lan8814_ptp_extts_on(struct phy_device = *phydev, int pin, u32 flags) static void lan8814_ptp_extts_off(struct phy_device *phydev, int pin) { /* Set as gpio out */ - lanphy_modify_page_reg(phydev, 4, LAN8814_GPIO_DIR_ADDR(pin), + lanphy_modify_page_reg(phydev, LAN_EXT_PAGE_4, + LAN8814_GPIO_DIR_ADDR(pin), LAN8814_GPIO_DIR_BIT(pin), LAN8814_GPIO_DIR_BIT(pin)); =20 /* Enable alternate, 0:for alternate function, 1:gpio */ - lanphy_modify_page_reg(phydev, 4, LAN8814_GPIO_EN_ADDR(pin), + lanphy_modify_page_reg(phydev, LAN_EXT_PAGE_4, + LAN8814_GPIO_EN_ADDR(pin), LAN8814_GPIO_EN_BIT(pin), 0); =20 /* Clear the mapping of pin to registers 0 of the capture registers */ - lanphy_modify_page_reg(phydev, 4, PTP_GPIO_CAP_MAP_LO, + lanphy_modify_page_reg(phydev, LAN_EXT_PAGE_4, + PTP_GPIO_CAP_MAP_LO, GENMASK(3, 0), 0); =20 /* Disable capture on both of the edges */ - lanphy_modify_page_reg(phydev, 4, PTP_GPIO_CAP_EN, + lanphy_modify_page_reg(phydev, LAN_EXT_PAGE_4, PTP_GPIO_CAP_EN, PTP_GPIO_CAP_EN_GPIO_RE_CAPTURE_ENABLE(pin) | PTP_GPIO_CAP_EN_GPIO_FE_CAPTURE_ENABLE(pin), 0); =20 /* Disable interrupt top interrupt */ - lanphy_modify_page_reg(phydev, 4, PTP_COMMON_INT_ENA, + lanphy_modify_page_reg(phydev, LAN_EXT_PAGE_4, PTP_COMMON_INT_ENA, PTP_COMMON_INT_ENA_GPIO_CAP_EN, 0); } @@ -3756,7 +3814,8 @@ static void lan8814_get_tx_ts(struct kszphy_ptp_priv = *ptp_priv) /* If other timestamps are available in the FIFO, * process them. */ - reg =3D lanphy_read_page_reg(phydev, 5, PTP_CAP_INFO); + reg =3D lanphy_read_page_reg(phydev, LAN_EXT_PAGE_5, + PTP_CAP_INFO); } while (PTP_CAP_INFO_TX_TS_CNT_GET_(reg) > 0); } =20 @@ -3829,7 +3888,8 @@ static void lan8814_get_rx_ts(struct kszphy_ptp_priv = *ptp_priv) /* If other timestamps are available in the FIFO, * process them. */ - reg =3D lanphy_read_page_reg(phydev, 5, PTP_CAP_INFO); + reg =3D lanphy_read_page_reg(phydev, LAN_EXT_PAGE_5, + PTP_CAP_INFO); } while (PTP_CAP_INFO_RX_TS_CNT_GET_(reg) > 0); } =20 @@ -3866,31 +3926,39 @@ static int lan8814_gpio_process_cap(struct lan8814_= shared_priv *shared) /* This is 0 because whatever was the input pin it was mapped it to * ltc gpio pin 0 */ - lanphy_modify_page_reg(phydev, 4, PTP_GPIO_SEL, + lanphy_modify_page_reg(phydev, LAN_EXT_PAGE_4, PTP_GPIO_SEL, PTP_GPIO_SEL_GPIO_SEL(0), PTP_GPIO_SEL_GPIO_SEL(0)); =20 - tmp =3D lanphy_read_page_reg(phydev, 4, PTP_GPIO_CAP_STS); + tmp =3D lanphy_read_page_reg(phydev, LAN_EXT_PAGE_4, PTP_GPIO_CAP_STS); if (!(tmp & PTP_GPIO_CAP_STS_PTP_GPIO_RE_STS(0)) && !(tmp & PTP_GPIO_CAP_STS_PTP_GPIO_FE_STS(0))) return -1; =20 if (tmp & BIT(0)) { - sec =3D lanphy_read_page_reg(phydev, 4, PTP_GPIO_RE_LTC_SEC_HI_CAP); + sec =3D lanphy_read_page_reg(phydev, LAN_EXT_PAGE_4, + PTP_GPIO_RE_LTC_SEC_HI_CAP); sec <<=3D 16; - sec |=3D lanphy_read_page_reg(phydev, 4, PTP_GPIO_RE_LTC_SEC_LO_CAP); + sec |=3D lanphy_read_page_reg(phydev, LAN_EXT_PAGE_4, + PTP_GPIO_RE_LTC_SEC_LO_CAP); =20 - nsec =3D lanphy_read_page_reg(phydev, 4, PTP_GPIO_RE_LTC_NS_HI_CAP) & 0x= 3fff; + nsec =3D lanphy_read_page_reg(phydev, LAN_EXT_PAGE_4, + PTP_GPIO_RE_LTC_NS_HI_CAP) & 0x3fff; nsec <<=3D 16; - nsec |=3D lanphy_read_page_reg(phydev, 4, PTP_GPIO_RE_LTC_NS_LO_CAP); + nsec |=3D lanphy_read_page_reg(phydev, LAN_EXT_PAGE_4, + PTP_GPIO_RE_LTC_NS_LO_CAP); } else { - sec =3D lanphy_read_page_reg(phydev, 4, PTP_GPIO_FE_LTC_SEC_HI_CAP); + sec =3D lanphy_read_page_reg(phydev, LAN_EXT_PAGE_4, + PTP_GPIO_FE_LTC_SEC_HI_CAP); sec <<=3D 16; - sec |=3D lanphy_read_page_reg(phydev, 4, PTP_GPIO_FE_LTC_SEC_LO_CAP); + sec |=3D lanphy_read_page_reg(phydev, LAN_EXT_PAGE_4, + PTP_GPIO_FE_LTC_SEC_LO_CAP); =20 - nsec =3D lanphy_read_page_reg(phydev, 4, PTP_GPIO_FE_LTC_NS_HI_CAP) & 0x= 3fff; + nsec =3D lanphy_read_page_reg(phydev, LAN_EXT_PAGE_4, + PTP_GPIO_FE_LTC_NS_HI_CAP) & 0x3fff; nsec <<=3D 16; - nsec |=3D lanphy_read_page_reg(phydev, 4, PTP_GPIO_RE_LTC_NS_LO_CAP); + nsec |=3D lanphy_read_page_reg(phydev, LAN_EXT_PAGE_4, + PTP_GPIO_RE_LTC_NS_LO_CAP); } =20 ptp_event.index =3D 0; @@ -3916,15 +3984,16 @@ static int lan8814_handle_gpio_interrupt(struct phy= _device *phydev, u16 status) static int lan8804_config_init(struct phy_device *phydev) { /* MDI-X setting for swap A,B transmit */ - lanphy_modify_page_reg(phydev, 2, LAN8804_ALIGN_SWAP, + lanphy_modify_page_reg(phydev, LAN_EXT_PAGE_2, LAN8804_ALIGN_SWAP, LAN8804_ALIGN_TX_A_B_SWAP_MASK, LAN8804_ALIGN_TX_A_B_SWAP); =20 /* Make sure that the PHY will not stop generating the clock when the * link partner goes down */ - lanphy_write_page_reg(phydev, 31, LAN8814_CLOCK_MANAGEMENT, 0x27e); - lanphy_read_page_reg(phydev, 1, LAN8814_LINK_QUALITY); + lanphy_write_page_reg(phydev, LAN_EXT_PAGE_31, + LAN8814_CLOCK_MANAGEMENT, 0x27e); + lanphy_read_page_reg(phydev, LAN_EXT_PAGE_1, LAN8814_LINK_QUALITY); =20 return 0; } @@ -4006,7 +4075,8 @@ static irqreturn_t lan8814_handle_interrupt(struct ph= y_device *phydev) } =20 while (true) { - irq_status =3D lanphy_read_page_reg(phydev, 5, PTP_TSU_INT_STS); + irq_status =3D lanphy_read_page_reg(phydev, LAN_EXT_PAGE_5, + PTP_TSU_INT_STS); if (!irq_status) break; =20 @@ -4034,7 +4104,7 @@ static int lan8814_config_intr(struct phy_device *phy= dev) { int err; =20 - lanphy_write_page_reg(phydev, 4, LAN8814_INTR_CTRL_REG, + lanphy_write_page_reg(phydev, LAN_EXT_PAGE_4, LAN8814_INTR_CTRL_REG, LAN8814_INTR_CTRL_REG_POLARITY | LAN8814_INTR_CTRL_REG_INTR_ENABLE); =20 @@ -4065,29 +4135,34 @@ static void lan8814_ptp_init(struct phy_device *phy= dev) !IS_ENABLED(CONFIG_NETWORK_PHY_TIMESTAMPING)) return; =20 - lanphy_write_page_reg(phydev, 5, TSU_HARD_RESET, TSU_HARD_RESET_); + lanphy_write_page_reg(phydev, LAN_EXT_PAGE_5, + TSU_HARD_RESET, TSU_HARD_RESET_); =20 - lanphy_modify_page_reg(phydev, 5, PTP_TX_MOD, + lanphy_modify_page_reg(phydev, LAN_EXT_PAGE_5, PTP_TX_MOD, PTP_TX_MOD_BAD_UDPV4_CHKSUM_FORCE_FCS_DIS_, PTP_TX_MOD_BAD_UDPV4_CHKSUM_FORCE_FCS_DIS_); =20 - lanphy_modify_page_reg(phydev, 5, PTP_RX_MOD, + lanphy_modify_page_reg(phydev, LAN_EXT_PAGE_5, PTP_RX_MOD, PTP_RX_MOD_BAD_UDPV4_CHKSUM_FORCE_FCS_DIS_, PTP_RX_MOD_BAD_UDPV4_CHKSUM_FORCE_FCS_DIS_); =20 - lanphy_write_page_reg(phydev, 5, PTP_RX_PARSE_CONFIG, 0); - lanphy_write_page_reg(phydev, 5, PTP_TX_PARSE_CONFIG, 0); + lanphy_write_page_reg(phydev, LAN_EXT_PAGE_5, PTP_RX_PARSE_CONFIG, 0); + lanphy_write_page_reg(phydev, LAN_EXT_PAGE_5, PTP_TX_PARSE_CONFIG, 0); =20 /* Removing default registers configs related to L2 and IP */ - lanphy_write_page_reg(phydev, 5, PTP_TX_PARSE_L2_ADDR_EN, 0); - lanphy_write_page_reg(phydev, 5, PTP_RX_PARSE_L2_ADDR_EN, 0); - lanphy_write_page_reg(phydev, 5, PTP_TX_PARSE_IP_ADDR_EN, 0); - lanphy_write_page_reg(phydev, 5, PTP_RX_PARSE_IP_ADDR_EN, 0); + lanphy_write_page_reg(phydev, LAN_EXT_PAGE_5, + PTP_TX_PARSE_L2_ADDR_EN, 0); + lanphy_write_page_reg(phydev, LAN_EXT_PAGE_5, + PTP_RX_PARSE_L2_ADDR_EN, 0); + lanphy_write_page_reg(phydev, LAN_EXT_PAGE_5, + PTP_TX_PARSE_IP_ADDR_EN, 0); + lanphy_write_page_reg(phydev, LAN_EXT_PAGE_5, + PTP_RX_PARSE_IP_ADDR_EN, 0); =20 /* Disable checking for minorVersionPTP field */ - lanphy_write_page_reg(phydev, 5, PTP_RX_VERSION, + lanphy_write_page_reg(phydev, LAN_EXT_PAGE_5, PTP_RX_VERSION, PTP_MAX_VERSION(0xff) | PTP_MIN_VERSION(0x0)); - lanphy_write_page_reg(phydev, 5, PTP_TX_VERSION, + lanphy_write_page_reg(phydev, LAN_EXT_PAGE_5, PTP_TX_VERSION, PTP_MAX_VERSION(0xff) | PTP_MIN_VERSION(0x0)); =20 skb_queue_head_init(&ptp_priv->tx_queue); @@ -4172,12 +4247,14 @@ static int lan8814_ptp_probe_once(struct phy_device= *phydev) /* The EP.4 is shared between all the PHYs in the package and also it * can be accessed by any of the PHYs */ - lanphy_write_page_reg(phydev, 4, LTC_HARD_RESET, LTC_HARD_RESET_); - lanphy_write_page_reg(phydev, 4, PTP_OPERATING_MODE, + lanphy_write_page_reg(phydev, LAN_EXT_PAGE_4, + LTC_HARD_RESET, LTC_HARD_RESET_); + lanphy_write_page_reg(phydev, LAN_EXT_PAGE_4, PTP_OPERATING_MODE, PTP_OPERATING_MODE_STANDALONE_); =20 /* Enable ptp to run LTC clock for ptp and gpio 1PPS operation */ - lanphy_write_page_reg(phydev, 4, PTP_CMD_CTL, PTP_CMD_CTL_PTP_ENABLE_); + lanphy_write_page_reg(phydev, LAN_EXT_PAGE_4, PTP_CMD_CTL, + PTP_CMD_CTL_PTP_ENABLE_); =20 return 0; } @@ -4186,14 +4263,14 @@ static void lan8814_setup_led(struct phy_device *ph= ydev, int val) { int temp; =20 - temp =3D lanphy_read_page_reg(phydev, 5, LAN8814_LED_CTRL_1); + temp =3D lanphy_read_page_reg(phydev, LAN_EXT_PAGE_5, LAN8814_LED_CTRL_1); =20 if (val) temp |=3D LAN8814_LED_CTRL_1_KSZ9031_LED_MODE_; else temp &=3D ~LAN8814_LED_CTRL_1_KSZ9031_LED_MODE_; =20 - lanphy_write_page_reg(phydev, 5, LAN8814_LED_CTRL_1, temp); + lanphy_write_page_reg(phydev, LAN_EXT_PAGE_5, LAN8814_LED_CTRL_1, temp); } =20 static int lan8814_config_init(struct phy_device *phydev) @@ -4201,17 +4278,19 @@ static int lan8814_config_init(struct phy_device *p= hydev) struct kszphy_priv *lan8814 =3D phydev->priv; =20 /* Reset the PHY */ - lanphy_modify_page_reg(phydev, 4, LAN8814_QSGMII_SOFT_RESET, + lanphy_modify_page_reg(phydev, LAN_EXT_PAGE_4, + LAN8814_QSGMII_SOFT_RESET, LAN8814_QSGMII_SOFT_RESET_BIT, LAN8814_QSGMII_SOFT_RESET_BIT); =20 /* Disable ANEG with QSGMII PCS Host side */ - lanphy_modify_page_reg(phydev, 4, LAN8814_QSGMII_PCS1G_ANEG_CONFIG, + lanphy_modify_page_reg(phydev, LAN_EXT_PAGE_4, + LAN8814_QSGMII_PCS1G_ANEG_CONFIG, LAN8814_QSGMII_PCS1G_ANEG_CONFIG_ANEG_ENA, 0); =20 /* MDI-X setting for swap A,B transmit */ - lanphy_modify_page_reg(phydev, 2, LAN8814_ALIGN_SWAP, + lanphy_modify_page_reg(phydev, LAN_EXT_PAGE_2, LAN8814_ALIGN_SWAP, LAN8814_ALIGN_TX_A_B_SWAP_MASK, LAN8814_ALIGN_TX_A_B_SWAP); =20 @@ -4248,7 +4327,7 @@ static void lan8814_clear_2psp_bit(struct phy_device = *phydev) * cable is removed then the LED was still one even though there is no * link */ - lanphy_modify_page_reg(phydev, 2, LAN8814_EEE_STATE, + lanphy_modify_page_reg(phydev, LAN_EXT_PAGE_2, LAN8814_EEE_STATE, LAN8814_EEE_STATE_MASK2P5P, 0); } @@ -4259,7 +4338,7 @@ static void lan8814_update_meas_time(struct phy_devic= e *phydev) * longer than 100m to be used. This configuration can be used * regardless of the mode of operation of the PHY */ - lanphy_modify_page_reg(phydev, 1, LAN8814_PD_CONTROLS, + lanphy_modify_page_reg(phydev, LAN_EXT_PAGE_1, LAN8814_PD_CONTROLS, LAN8814_PD_CONTROLS_PD_MEAS_TIME_MASK, LAN8814_PD_CONTROLS_PD_MEAS_TIME_VAL); } @@ -4284,7 +4363,7 @@ static int lan8814_probe(struct phy_device *phydev) /* Strap-in value for PHY address, below register read gives starting * phy address value */ - addr =3D lanphy_read_page_reg(phydev, 4, 0) & 0x1F; + addr =3D lanphy_read_page_reg(phydev, LAN_EXT_PAGE_4, 0) & 0x1F; devm_phy_package_join(&phydev->mdio.dev, phydev, addr, sizeof(struct lan8814_shared_priv)); =20 --=20 2.34.1 From nobody Mon Oct 6 04:59:09 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2EA99239581; Thu, 24 Jul 2025 20:12:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753387934; cv=none; b=htyMFL9qk4NH7Tuu0+cekTHWTpHxtB+ne+p93+0pgruhbdPpefjPuIgf++7grkWHkFG4hdeqKR2NpnGDyQIrrXGyM1NYzi6B2VuDVn2wduyR23g0EW5zNNjbWTUsbn3MsUQ1eZ5myiwjju5bQcr+0LepDUbHps3NFzm5k3Pz2oY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753387934; c=relaxed/simple; bh=pUAqg/uKxaVXamSlKodRXwwjXO4TngzCIQoeMPyrq8A=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=aYFE4khE9TtgCKZ89zb5xDx9an/6yh0d4cbqn/BeAxaO13bEx74FWRGdrBeWcfVt9T/et2JqBpSn9V0J6POBn3OT61oSLrt7NhrGPsJkkpVJctKsE1dYDAwGn3+bvjRVy4gFVsecaT3BQA93kKncxjKW7XwEWV6Hh7in9cnu3kY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=JTTnNvVL; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="JTTnNvVL" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1753387933; x=1784923933; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=pUAqg/uKxaVXamSlKodRXwwjXO4TngzCIQoeMPyrq8A=; b=JTTnNvVLQf1+JFE1l6JHECjWTmSLW2deSTL4WDb80y8RAuFQQIWm6Xdh lziyAGc6BqO/Q35S23XbJhE3RpKPk+/9QEZMl4kVwg7Fc7JsP8ejk/PbZ 0k01a/pQei9zPjw5+uNcsRV0vndtKh6jklKaj05ZMDrdG8gXvN03Cukdl THi8MtnFhfswXu00jsHGuxECk+NeNthb7oKW4hPEgkAjQ7JQaKixa9v9P iC5JuQ5XzvTttP0JO2W8E8C8vwubyAHfD5mHpFtqIy6AlXL7Xk6q/RX5I ihia1f9qikn4zzNrSYbAH5KCeMR4UE5PpXHluIlVAaGSUF9kQR58O7sah Q==; X-CSE-ConnectionGUID: dPxjunYJTo2XkJR5vJWM1w== X-CSE-MsgGUID: tl/UWdpRQMK7w5K+pyCskw== X-IronPort-AV: E=Sophos;i="6.16,337,1744095600"; d="scan'208";a="44383323" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa3.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 24 Jul 2025 13:12:10 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.44; Thu, 24 Jul 2025 13:11:37 -0700 Received: from DEN-DL-M31836.microchip.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.44 via Frontend Transport; Thu, 24 Jul 2025 13:11:35 -0700 From: Horatiu Vultur To: , , , , , , , , CC: , , Horatiu Vultur Subject: [PATCH net-next v2 4/4] net: phy: micrel: Add support for lan8842 Date: Thu, 24 Jul 2025 22:08:26 +0200 Message-ID: <20250724200826.2662658-5-horatiu.vultur@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250724200826.2662658-1-horatiu.vultur@microchip.com> References: <20250724200826.2662658-1-horatiu.vultur@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The LAN8842 is a low-power, single port triple-speed (10BASE-T/ 100BASE-TX/ 1000BASE-T) ethernet physical layer transceiver (PHY) that supports transmission and reception of data on standard CAT-5, as well as CAT-5e and CAT-6, Unshielded Twisted Pair (UTP) cables. The LAN8842 supports industry-standard SGMII (Serial Gigabit Media Independent Interface) providing chip-to-chip connection to a Gigabit Ethernet MAC using a single serialized link (differential pair) in each direction. There are 2 variants of the lan8842. The one that supports timestamping (lan8842) and one that doesn't have timestamping (lan8832). Signed-off-by: Horatiu Vultur --- drivers/net/phy/micrel.c | 200 +++++++++++++++++++++++++++++++++++++ include/linux/micrel_phy.h | 1 + 2 files changed, 201 insertions(+) diff --git a/drivers/net/phy/micrel.c b/drivers/net/phy/micrel.c index d20f028106b7d..da39d9a1b251a 100644 --- a/drivers/net/phy/micrel.c +++ b/drivers/net/phy/micrel.c @@ -448,6 +448,17 @@ struct kszphy_priv { struct kszphy_phy_stats phy_stats; }; =20 +struct lan8842_phy_stats { + u64 rx_packets; + u64 rx_errors; + u64 tx_packets; + u64 tx_errors; +}; + +struct lan8842_priv { + struct lan8842_phy_stats phy_stats; +}; + static const struct kszphy_type lan8814_type =3D { .led_mode_reg =3D ~LAN8814_LED_CTRL_1, .cable_diag_reg =3D LAN8814_CABLE_DIAG, @@ -5718,6 +5729,181 @@ static int ksz9131_resume(struct phy_device *phydev) return kszphy_resume(phydev); } =20 +#define LAN8842_SELF_TEST 14 /* 0x0e */ +#define LAN8842_SELF_TEST_RX_CNT_ENA BIT(8) +#define LAN8842_SELF_TEST_TX_CNT_ENA BIT(4) + +static int lan8842_probe(struct phy_device *phydev) +{ + struct lan8842_priv *priv; + int ret; + + priv =3D devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + phydev->priv =3D priv; + + /* Similar to lan8814 this PHY has a pin which needs to be pulled down + * to enable to pass any traffic through it. Therefore use the same + * function as lan8814 + */ + ret =3D lan8814_release_coma_mode(phydev); + if (ret) + return ret; + + /* Enable to count the RX and TX packets */ + lanphy_write_page_reg(phydev, LAN_EXT_PAGE_2, + LAN8842_SELF_TEST, + LAN8842_SELF_TEST_RX_CNT_ENA | + LAN8842_SELF_TEST_TX_CNT_ENA); + + return 0; +} + +#define LAN8842_SGMII_AUTO_ANEG_ENA 69 /* 0x45 */ +#define LAN8842_FLF 15 /* 0x0e */ +#define LAN8842_FLF_ENA BIT(1) +#define LAN8842_FLF_ENA_LINK_DOWN BIT(0) + +static int lan8842_config_init(struct phy_device *phydev) +{ + int ret; + + /* Reset the PHY */ + ret =3D lanphy_modify_page_reg(phydev, LAN_EXT_PAGE_4, + LAN8814_QSGMII_SOFT_RESET, + LAN8814_QSGMII_SOFT_RESET_BIT, + LAN8814_QSGMII_SOFT_RESET_BIT); + if (ret < 0) + return ret; + + /* Disable ANEG with QSGMII PCS Host side + * It has the same address as lan8814 + */ + ret =3D lanphy_modify_page_reg(phydev, LAN_EXT_PAGE_5, + LAN8814_QSGMII_PCS1G_ANEG_CONFIG, + LAN8814_QSGMII_PCS1G_ANEG_CONFIG_ANEG_ENA, + 0); + if (ret < 0) + return ret; + + /* Disable also the SGMII_AUTO_ANEG_ENA, this will determine what is the + * PHY autoneg with the other end and then will update the host side + */ + ret =3D lanphy_write_page_reg(phydev, LAN_EXT_PAGE_4, + LAN8842_SGMII_AUTO_ANEG_ENA, 0); + if (ret < 0) + return ret; + + /* To allow the PHY to control the LEDs the GPIOs of the PHY should have + * a function mode and not the GPIO. Apparently by default the value is + * GPIO and not function even though the datasheet it says that it is + * function. Therefore set this value. + */ + return lanphy_write_page_reg(phydev, LAN_EXT_PAGE_4, + LAN8814_GPIO_EN2, 0); +} + +#define LAN8842_INTR_CTRL_REG 52 /* 0x34 */ + +static int lan8842_config_intr(struct phy_device *phydev) +{ + int err; + + lanphy_write_page_reg(phydev, LAN_EXT_PAGE_4, + LAN8842_INTR_CTRL_REG, + LAN8814_INTR_CTRL_REG_INTR_ENABLE); + + /* enable / disable interrupts */ + if (phydev->interrupts =3D=3D PHY_INTERRUPT_ENABLED) { + err =3D lan8814_ack_interrupt(phydev); + if (err) + return err; + + err =3D phy_write(phydev, LAN8814_INTC, LAN8814_INT_LINK); + } else { + err =3D phy_write(phydev, LAN8814_INTC, 0); + if (err) + return err; + + err =3D lan8814_ack_interrupt(phydev); + } + + return err; +} + +static irqreturn_t lan8842_handle_interrupt(struct phy_device *phydev) +{ + int ret =3D IRQ_NONE; + int irq_status; + + irq_status =3D phy_read(phydev, LAN8814_INTS); + if (irq_status < 0) { + phy_error(phydev); + return IRQ_NONE; + } + + if (irq_status & LAN8814_INT_LINK) { + phy_trigger_machine(phydev); + ret =3D IRQ_HANDLED; + } + + return ret; +} + +static u64 lan8842_get_stat(struct phy_device *phydev, int count, int *reg= s) +{ + int val; + u64 ret =3D 0; + + for (int j =3D 0; j < count; ++j) { + val =3D lanphy_read_page_reg(phydev, LAN_EXT_PAGE_2, regs[j]); + if (val < 0) + return U64_MAX; + + ret <<=3D 16; + ret +=3D val; + } + return ret; +} + +static int lan8842_update_stats(struct phy_device *phydev) +{ + struct lan8842_priv *priv =3D phydev->priv; + int rx_packets_regs[] =3D {88, 61, 60}; + int rx_errors_regs[] =3D {63, 62}; + int tx_packets_regs[] =3D {89, 85, 84}; + int tx_errors_regs[] =3D {87, 86}; + + priv->phy_stats.rx_packets =3D lan8842_get_stat(phydev, + ARRAY_SIZE(rx_packets_regs), + rx_packets_regs); + priv->phy_stats.rx_errors =3D lan8842_get_stat(phydev, + ARRAY_SIZE(rx_errors_regs), + rx_errors_regs); + priv->phy_stats.tx_packets =3D lan8842_get_stat(phydev, + ARRAY_SIZE(tx_packets_regs), + tx_packets_regs); + priv->phy_stats.tx_errors =3D lan8842_get_stat(phydev, + ARRAY_SIZE(tx_errors_regs), + tx_errors_regs); + + return 0; +} + +static void lan8842_get_phy_stats(struct phy_device *phydev, + struct ethtool_eth_phy_stats *eth_stats, + struct ethtool_phy_stats *stats) +{ + struct lan8842_priv *priv =3D phydev->priv; + + stats->rx_packets =3D priv->phy_stats.rx_packets; + stats->rx_errors =3D priv->phy_stats.rx_errors; + stats->tx_packets =3D priv->phy_stats.tx_packets; + stats->tx_errors =3D priv->phy_stats.rx_errors; +} + static struct phy_driver ksphy_driver[] =3D { { PHY_ID_MATCH_MODEL(PHY_ID_KS8737), @@ -5937,6 +6123,19 @@ static struct phy_driver ksphy_driver[] =3D { .resume =3D lan8841_resume, .cable_test_start =3D lan8814_cable_test_start, .cable_test_get_status =3D ksz886x_cable_test_get_status, +}, { + PHY_ID_MATCH_MODEL(PHY_ID_LAN8842), + .name =3D "Microchip LAN8842 Gigabit PHY", + .flags =3D PHY_POLL_CABLE_TEST, + .driver_data =3D &lan8814_type, + .probe =3D lan8842_probe, + .config_init =3D lan8842_config_init, + .config_intr =3D lan8842_config_intr, + .handle_interrupt =3D lan8842_handle_interrupt, + .get_phy_stats =3D lan8842_get_phy_stats, + .update_stats =3D lan8842_update_stats, + .cable_test_start =3D lan8814_cable_test_start, + .cable_test_get_status =3D ksz886x_cable_test_get_status, }, { PHY_ID_MATCH_MODEL(PHY_ID_KSZ9131), .name =3D "Microchip KSZ9131 Gigabit PHY", @@ -6032,6 +6231,7 @@ static const struct mdio_device_id __maybe_unused mic= rel_tbl[] =3D { { PHY_ID_MATCH_MODEL(PHY_ID_LAN8814) }, { PHY_ID_MATCH_MODEL(PHY_ID_LAN8804) }, { PHY_ID_MATCH_MODEL(PHY_ID_LAN8841) }, + { PHY_ID_MATCH_MODEL(PHY_ID_LAN8842) }, { } }; =20 diff --git a/include/linux/micrel_phy.h b/include/linux/micrel_phy.h index 9af01bdd86d26..ca691641788b8 100644 --- a/include/linux/micrel_phy.h +++ b/include/linux/micrel_phy.h @@ -32,6 +32,7 @@ #define PHY_ID_LAN8814 0x00221660 #define PHY_ID_LAN8804 0x00221670 #define PHY_ID_LAN8841 0x00221650 +#define PHY_ID_LAN8842 0x002216C0 =20 #define PHY_ID_KSZ886X 0x00221430 #define PHY_ID_KSZ8863 0x00221435 --=20 2.34.1