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charset="utf-8" Add compatible string for the Altera Agilex5 variant of the Synopsys DWC XGMAC IP version 2.10. Signed-off-by: Matthew Gerlach Reviewed-by: Rob Herring (Arm) --- v2: - Remove generic compatible string for Agilex5. --- .../devicetree/bindings/net/altr,socfpga-stmmac.yaml | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/net/altr,socfpga-stmmac.yaml= b/Documentation/devicetree/bindings/net/altr,socfpga-stmmac.yaml index ec34daff2aa0..3a22d35db778 100644 --- a/Documentation/devicetree/bindings/net/altr,socfpga-stmmac.yaml +++ b/Documentation/devicetree/bindings/net/altr,socfpga-stmmac.yaml @@ -11,8 +11,8 @@ maintainers: =20 description: This binding describes the Altera SOCFPGA SoC implementation of the - Synopsys DWMAC for the Cyclone5, Arria5, Stratix10, and Agilex7 families - of chips. + Synopsys DWMAC for the Cyclone5, Arria5, Stratix10, Agilex5 and Agilex7 + families of chips. # TODO: Determine how to handle the Arria10 reset-name, stmmaceth-ocp, t= hat # does not validate against net/snps,dwmac.yaml. =20 @@ -23,6 +23,7 @@ select: enum: - altr,socfpga-stmmac - altr,socfpga-stmmac-a10-s10 + - altr,socfpga-stmmac-agilex5 =20 required: - compatible @@ -42,6 +43,9 @@ properties: - const: altr,socfpga-stmmac-a10-s10 - const: snps,dwmac-3.74a - const: snps,dwmac + - items: + - const: altr,socfpga-stmmac-agilex5 + - const: snps,dwxgmac-2.10 =20 clocks: minItems: 1 --=20 2.35.3 From nobody Mon Oct 6 04:56:02 2025 Received: from CY4PR05CU001.outbound.protection.outlook.com (mail-westcentralusazon11010011.outbound.protection.outlook.com [40.93.198.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7D6392EA754; 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Received: from BYAPR03MB3461.namprd03.prod.outlook.com (2603:10b6:a02:b4::23) by SA6PR03MB7735.namprd03.prod.outlook.com (2603:10b6:806:43c::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8964.21; Thu, 24 Jul 2025 15:42:50 +0000 Received: from BYAPR03MB3461.namprd03.prod.outlook.com ([fe80::706b:dd15:bc81:313c]) by BYAPR03MB3461.namprd03.prod.outlook.com ([fe80::706b:dd15:bc81:313c%6]) with mapi id 15.20.8943.029; Thu, 24 Jul 2025 15:42:49 +0000 From: Matthew Gerlach To: andrew+netdev@lunn.ch, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, mcoquelin.stm32@gmail.com, alexandre.torgue@foss.st.com, dinguyen@kernel.org, maxime.chevallier@bootlin.com, richardcochran@gmail.com, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Mun Yew Tham , Matthew Gerlach Subject: [PATCH v2 2/4] arm64: dts: Agilex5 Add gmac nodes to DTSI for Agilex5 Date: Thu, 24 Jul 2025 08:40:49 -0700 Message-ID: <20250724154052.205706-3-matthew.gerlach@altera.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250724154052.205706-1-matthew.gerlach@altera.com> References: <20250724154052.205706-1-matthew.gerlach@altera.com> Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SJ0PR05CA0094.namprd05.prod.outlook.com (2603:10b6:a03:334::9) To BYAPR03MB3461.namprd03.prod.outlook.com (2603:10b6:a02:b4::23) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BYAPR03MB3461:EE_|SA6PR03MB7735:EE_ X-MS-Office365-Filtering-Correlation-Id: e511c696-d84e-448a-d14c-08ddcac8be85 X-MS-Exchange-AtpMessageProperties: SA X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|366016|376014|1800799024|921020; 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charset="utf-8" From: Mun Yew Tham Add the base device tree nodes for gmac0, gmac1, and gmac2 to the DTSI for the Agilex5 SOCFPGA. Agilex5 has three Ethernet controllers based on Synopsys DWC XGMAC IP version 2.10. Signed-off-by: Mun Yew Tham Signed-off-by: Matthew Gerlach --- v2: - Remove generic compatible string for Agilex5. --- .../arm64/boot/dts/intel/socfpga_agilex5.dtsi | 336 ++++++++++++++++++ 1 file changed, 336 insertions(+) diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/bo= ot/dts/intel/socfpga_agilex5.dtsi index 7d9394a04302..04e99cd7e74b 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi @@ -486,5 +486,341 @@ qspi: spi@108d2000 { clocks =3D <&qspi_clk>; status =3D "disabled"; }; + + gmac0: ethernet@10810000 { + compatible =3D "altr,socfpga-stmmac-agilex5", + "snps,dwxgmac-2.10"; + reg =3D <0x10810000 0x3500>; + interrupts =3D ; + interrupt-names =3D "macirq"; + resets =3D <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>; + reset-names =3D "stmmaceth", "ahb"; + clocks =3D <&clkmgr AGILEX5_EMAC0_CLK>, + <&clkmgr AGILEX5_EMAC_PTP_CLK>; + clock-names =3D "stmmaceth", "ptp_ref"; + mac-address =3D [00 00 00 00 00 00]; + tx-fifo-depth =3D <32768>; + rx-fifo-depth =3D <16384>; + snps,multicast-filter-bins =3D <64>; + snps,perfect-filter-entries =3D <64>; + snps,axi-config =3D <&stmmac_axi_emac0_setup>; + snps,mtl-rx-config =3D <&mtl_rx_emac0_setup>; + snps,mtl-tx-config =3D <&mtl_tx_emac0_setup>; + snps,pbl =3D <32>; + snps,tso; + altr,sysmgr-syscon =3D <&sysmgr 0x44 0>; + snps,clk-csr =3D <0>; + status =3D "disabled"; + + stmmac_axi_emac0_setup: stmmac-axi-config { + snps,wr_osr_lmt =3D <31>; + snps,rd_osr_lmt =3D <31>; + snps,blen =3D <0 0 0 32 16 8 4>; + }; + + mtl_rx_emac0_setup: rx-queues-config { + snps,rx-queues-to-use =3D <8>; + snps,rx-sched-sp; + queue0 { + snps,dcb-algorithm; + snps,map-to-dma-channel =3D <0x0>; + }; + queue1 { + snps,dcb-algorithm; + snps,map-to-dma-channel =3D <0x1>; + }; + queue2 { + snps,dcb-algorithm; + snps,map-to-dma-channel =3D <0x2>; + }; + queue3 { + snps,dcb-algorithm; + snps,map-to-dma-channel =3D <0x3>; + }; + queue4 { + snps,dcb-algorithm; + snps,map-to-dma-channel =3D <0x4>; + }; + queue5 { + snps,dcb-algorithm; + snps,map-to-dma-channel =3D <0x5>; + }; + queue6 { + snps,dcb-algorithm; + snps,map-to-dma-channel =3D <0x6>; + }; + queue7 { + snps,dcb-algorithm; + snps,map-to-dma-channel =3D <0x7>; + }; + }; + + mtl_tx_emac0_setup: tx-queues-config { + snps,tx-queues-to-use =3D <8>; + snps,tx-sched-wrr; + queue0 { + snps,weight =3D <0x09>; + snps,dcb-algorithm; + }; + queue1 { + snps,weight =3D <0x0A>; + snps,dcb-algorithm; + }; + queue2 { + snps,weight =3D <0x0B>; + snps,coe-unsupported; + snps,dcb-algorithm; + }; + queue3 { + snps,weight =3D <0x0C>; + snps,coe-unsupported; + snps,dcb-algorithm; + }; + queue4 { + snps,weight =3D <0x0D>; + snps,coe-unsupported; + snps,dcb-algorithm; + }; + queue5 { + snps,weight =3D <0x0E>; + snps,coe-unsupported; + snps,dcb-algorithm; + }; + queue6 { + snps,weight =3D <0x0F>; + snps,coe-unsupported; + snps,dcb-algorithm; + }; + queue7 { + snps,weight =3D <0x10>; + snps,coe-unsupported; + snps,dcb-algorithm; + }; + }; + }; + + gmac1: ethernet@10820000 { + compatible =3D "altr,socfpga-stmmac-agilex5", + "snps,dwxgmac-2.10"; + reg =3D <0x10820000 0x3500>; + interrupts =3D ; + interrupt-names =3D "macirq"; + resets =3D <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>; + reset-names =3D "stmmaceth", "ahb"; + clocks =3D <&clkmgr AGILEX5_EMAC1_CLK>, + <&clkmgr AGILEX5_EMAC_PTP_CLK>; + clock-names =3D "stmmaceth", "ptp_ref"; + mac-address =3D [00 00 00 00 00 00]; + tx-fifo-depth =3D <32768>; + rx-fifo-depth =3D <16384>; + snps,multicast-filter-bins =3D <64>; + snps,perfect-filter-entries =3D <64>; + snps,axi-config =3D <&stmmac_axi_emac1_setup>; + snps,mtl-rx-config =3D <&mtl_rx_emac1_setup>; + snps,mtl-tx-config =3D <&mtl_tx_emac1_setup>; + snps,pbl =3D <32>; + snps,tso; + altr,sysmgr-syscon =3D <&sysmgr 0x48 0>; + snps,clk-csr =3D <0>; + status =3D "disabled"; + + stmmac_axi_emac1_setup: stmmac-axi-config { + snps,wr_osr_lmt =3D <31>; + snps,rd_osr_lmt =3D <31>; + snps,blen =3D <0 0 0 32 16 8 4>; + }; + + mtl_rx_emac1_setup: rx-queues-config { + snps,rx-queues-to-use =3D <8>; + snps,rx-sched-sp; + queue0 { + snps,dcb-algorithm; + snps,map-to-dma-channel =3D <0x0>; + }; + queue1 { + snps,dcb-algorithm; + snps,map-to-dma-channel =3D <0x1>; + }; + queue2 { + snps,dcb-algorithm; + snps,map-to-dma-channel =3D <0x2>; + }; + queue3 { + snps,dcb-algorithm; + snps,map-to-dma-channel =3D <0x3>; + }; + queue4 { + snps,dcb-algorithm; + snps,map-to-dma-channel =3D <0x4>; + }; + queue5 { + snps,dcb-algorithm; + snps,map-to-dma-channel =3D <0x5>; + }; + queue6 { + snps,dcb-algorithm; + snps,map-to-dma-channel =3D <0x6>; + }; + queue7 { + snps,dcb-algorithm; + snps,map-to-dma-channel =3D <0x7>; + }; + }; + + mtl_tx_emac1_setup: tx-queues-config { + snps,tx-queues-to-use =3D <8>; + snps,tx-sched-wrr; + queue0 { + snps,weight =3D <0x09>; + snps,dcb-algorithm; + }; + queue1 { + snps,weight =3D <0x0A>; + snps,dcb-algorithm; + }; + queue2 { + snps,weight =3D <0x0B>; + snps,coe-unsupported; + snps,dcb-algorithm; + }; + queue3 { + snps,weight =3D <0x0C>; + snps,coe-unsupported; + snps,dcb-algorithm; + }; + queue4 { + snps,weight =3D <0x0D>; + snps,coe-unsupported; + snps,dcb-algorithm; + }; + queue5 { + snps,weight =3D <0x0E>; + snps,coe-unsupported; + snps,dcb-algorithm; + }; + queue6 { + snps,weight =3D <0x0F>; + snps,coe-unsupported; + snps,dcb-algorithm; + }; + queue7 { + snps,weight =3D <0x10>; + snps,coe-unsupported; + snps,dcb-algorithm; + }; + }; + }; + + gmac2: ethernet@10830000 { + compatible =3D "altr,socfpga-stmmac-agilex5", + "snps,dwxgmac-2.10"; + reg =3D <0x10830000 0x3500>; + interrupts =3D ; + interrupt-names =3D "macirq"; + resets =3D <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>; + reset-names =3D "stmmaceth", "ahb"; + clocks =3D <&clkmgr AGILEX5_EMAC2_CLK>, + <&clkmgr AGILEX5_EMAC_PTP_CLK>; + clock-names =3D "stmmaceth", "ptp_ref"; + mac-address =3D [00 00 00 00 00 00]; + tx-fifo-depth =3D <32768>; + rx-fifo-depth =3D <16384>; + snps,multicast-filter-bins =3D <64>; + snps,perfect-filter-entries =3D <64>; + snps,axi-config =3D <&stmmac_axi_emac2_setup>; + snps,mtl-rx-config =3D <&mtl_rx_emac2_setup>; + snps,mtl-tx-config =3D <&mtl_tx_emac2_setup>; + snps,pbl =3D <32>; + snps,tso; + altr,sysmgr-syscon =3D <&sysmgr 0x4c 0>; + snps,clk-csr =3D <0>; + status =3D "disabled"; + + stmmac_axi_emac2_setup: stmmac-axi-config { + snps,wr_osr_lmt =3D <31>; + snps,rd_osr_lmt =3D <31>; + snps,blen =3D <0 0 0 32 16 8 4>; + }; + + mtl_rx_emac2_setup: rx-queues-config { + snps,rx-queues-to-use =3D <8>; + snps,rx-sched-sp; + queue0 { + snps,dcb-algorithm; + snps,map-to-dma-channel =3D <0x0>; + }; + queue1 { + snps,dcb-algorithm; + snps,map-to-dma-channel =3D <0x1>; + }; + queue2 { + snps,dcb-algorithm; + snps,map-to-dma-channel =3D <0x2>; + }; + queue3 { + snps,dcb-algorithm; + snps,map-to-dma-channel =3D <0x3>; + }; + queue4 { + snps,dcb-algorithm; + snps,map-to-dma-channel =3D <0x4>; + }; + queue5 { + snps,dcb-algorithm; + snps,map-to-dma-channel =3D <0x5>; + }; + queue6 { + snps,dcb-algorithm; + snps,map-to-dma-channel =3D <0x6>; + }; + queue7 { + snps,dcb-algorithm; + snps,map-to-dma-channel =3D <0x7>; + }; + }; + + mtl_tx_emac2_setup: tx-queues-config { + snps,tx-queues-to-use =3D <8>; + snps,tx-sched-wrr; + queue0 { + snps,weight =3D <0x09>; + snps,dcb-algorithm; + }; + queue1 { + snps,weight =3D <0x0A>; + snps,dcb-algorithm; + }; + queue2 { + snps,weight =3D <0x0B>; + snps,coe-unsupported; + snps,dcb-algorithm; + }; + queue3 { + snps,weight =3D <0x0C>; + snps,coe-unsupported; + snps,dcb-algorithm; + }; + queue4 { + snps,weight =3D <0x0D>; + snps,coe-unsupported; + snps,dcb-algorithm; + }; + queue5 { + snps,weight =3D <0x0E>; + snps,coe-unsupported; + snps,dcb-algorithm; + }; + queue6 { + snps,weight =3D <0x0F>; + snps,coe-unsupported; + snps,dcb-algorithm; + }; + queue7 { + snps,weight =3D <0x10>; + snps,coe-unsupported; + snps,dcb-algorithm; + }; + }; + }; }; }; --=20 2.35.3 From nobody Mon Oct 6 04:56:02 2025 Received: from NAM11-BN8-obe.outbound.protection.outlook.com (mail-bn8nam11on2054.outbound.protection.outlook.com [40.107.236.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7A0E52EB5C4; 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charset="utf-8" Enable gmac2 on the Agilex5 SOCFGPA Development Kit. The MAC is connected to a RGMII PHY on a daughter card. There are no RGMII clock delays implemented the on PCB. Signed-off-by: Matthew Gerlach --- v2: - change phy-mode to "rgmii-id" - add newline before inner device tree nodes --- .../boot/dts/intel/socfpga_agilex5_socdk.dts | 20 +++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts b/arch/arm= 64/boot/dts/intel/socfpga_agilex5_socdk.dts index d3b913b7902c..e9776e1cdc9a 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts @@ -10,6 +10,9 @@ / { =20 aliases { serial0 =3D &uart0; + ethernet0 =3D &gmac0; + ethernet1 =3D &gmac1; + ethernet2 =3D &gmac2; }; =20 chosen { @@ -37,6 +40,23 @@ &gpio0 { status =3D "okay"; }; =20 +&gmac2 { + status =3D "okay"; + phy-mode =3D "rgmii-id"; + phy-handle =3D <&emac2_phy0>; + max-frame-size =3D <9000>; + + mdio0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + compatible =3D "snps,dwmac-mdio"; + + emac2_phy0: ethernet-phy@0 { + reg =3D <0>; + }; + }; +}; + &gpio1 { status =3D "okay"; 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charset="utf-8" From: Mun Yew Tham Add support for Agilex5 compatible value. Signed-off-by: Mun Yew Tham Signed-off-by: Matthew Gerlach --- drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c b/drivers/= net/ethernet/stmicro/stmmac/dwmac-socfpga.c index 72b50f6d72f4..01dd0cf0923c 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c @@ -515,6 +515,7 @@ static const struct socfpga_dwmac_ops socfpga_gen10_ops= =3D { static const struct of_device_id socfpga_dwmac_match[] =3D { { .compatible =3D "altr,socfpga-stmmac", .data =3D &socfpga_gen5_ops }, { .compatible =3D "altr,socfpga-stmmac-a10-s10", .data =3D &socfpga_gen10= _ops }, + { .compatible =3D "altr,socfpga-stmmac-agilex5", .data =3D &socfpga_gen10= _ops }, { } }; MODULE_DEVICE_TABLE(of, socfpga_dwmac_match); --=20 2.35.3