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charset="utf-8" From: Sricharan Ramabadhran Add the qfprom, cpu clocks, A53 PLL and cpu-opp-table required for CPU clock scaling. Signed-off-by: Sricharan Ramabadhran [ Added interconnect related entries, fix dt-bindings errors ] Signed-off-by: Varadarajan Narayanan --- v3: Remove L3_CORE_CLK from cpu node as it comes through icc-clk v2: Add 'interconnects' to cpu nodes Add 'opp-peak-kBps' to opp table Add '#interconnect-cells' to apss_clk Remove unnecessary comment Fix dt-binding-errors in qfprom node --- arch/arm64/boot/dts/qcom/ipq5424.dtsi | 61 +++++++++++++++++++++++++++ 1 file changed, 61 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq5424.dtsi b/arch/arm64/boot/dts/qc= om/ipq5424.dtsi index 2eea8a078595..74ef7d4b8f9a 100644 --- a/arch/arm64/boot/dts/qcom/ipq5424.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5424.dtsi @@ -7,6 +7,7 @@ */ =20 #include +#include #include #include #include @@ -52,6 +53,11 @@ cpu0: cpu@0 { reg =3D <0x0>; enable-method =3D "psci"; next-level-cache =3D <&l2_0>; + clocks =3D <&apss_clk APSS_SILVER_CORE_CLK>; + clock-names =3D "cpu"; + operating-points-v2 =3D <&cpu_opp_table>; + interconnects =3D <&apss_clk MASTER_CPU &apss_clk SLAVE_L3>; + l2_0: l2-cache { compatible =3D "cache"; cache-level =3D <2>; @@ -72,6 +78,10 @@ cpu1: cpu@100 { enable-method =3D "psci"; reg =3D <0x100>; next-level-cache =3D <&l2_100>; + clocks =3D <&apss_clk APSS_SILVER_CORE_CLK>; + clock-names =3D "cpu"; + operating-points-v2 =3D <&cpu_opp_table>; + interconnects =3D <&apss_clk MASTER_CPU &apss_clk SLAVE_L3>; =20 l2_100: l2-cache { compatible =3D "cache"; @@ -87,6 +97,10 @@ cpu2: cpu@200 { enable-method =3D "psci"; reg =3D <0x200>; next-level-cache =3D <&l2_200>; + clocks =3D <&apss_clk APSS_SILVER_CORE_CLK>; + clock-names =3D "cpu"; + operating-points-v2 =3D <&cpu_opp_table>; + interconnects =3D <&apss_clk MASTER_CPU &apss_clk SLAVE_L3>; =20 l2_200: l2-cache { compatible =3D "cache"; @@ -102,6 +116,10 @@ cpu3: cpu@300 { enable-method =3D "psci"; reg =3D <0x300>; next-level-cache =3D <&l2_300>; + clocks =3D <&apss_clk APSS_SILVER_CORE_CLK>; + clock-names =3D "cpu"; + operating-points-v2 =3D <&cpu_opp_table>; + interconnects =3D <&apss_clk MASTER_CPU &apss_clk SLAVE_L3>; =20 l2_300: l2-cache { compatible =3D "cache"; @@ -119,6 +137,28 @@ scm { }; }; =20 + cpu_opp_table: opp-table-cpu { + compatible =3D "operating-points-v2-kryo-cpu"; + opp-shared; + nvmem-cells =3D <&cpu_speed_bin>; + + opp-1416000000 { + opp-hz =3D /bits/ 64 <1416000000>; + opp-microvolt =3D <1>; + opp-supported-hw =3D <0x3>; + clock-latency-ns =3D <200000>; + opp-peak-kBps =3D <984000>; + }; + + opp-1800000000 { + opp-hz =3D /bits/ 64 <1800000000>; + opp-microvolt =3D <2>; + opp-supported-hw =3D <0x1>; + clock-latency-ns =3D <200000>; + opp-peak-kBps =3D <1272000>; + }; + }; + memory@80000000 { device_type =3D "memory"; /* We expect the bootloader to fill in the size */ @@ -388,6 +428,18 @@ system-cache-controller@800000 { interrupts =3D ; }; =20 + qfprom@a6000 { + compatible =3D "qcom,ipq5424-qfprom", "qcom,qfprom"; + reg =3D <0x0 0x000a6000 0x0 0x1000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + + cpu_speed_bin: cpu-speed-bin@234 { + reg =3D <0x234 0x1>; + bits =3D <0 8>; + }; + }; + tlmm: pinctrl@1000000 { compatible =3D "qcom,ipq5424-tlmm"; reg =3D <0 0x01000000 0 0x300000>; @@ -730,6 +782,15 @@ frame@f42d000 { }; }; =20 + apss_clk: apss-clock@fa80000 { + compatible =3D "qcom,ipq5424-apss-clk"; + reg =3D <0x0 0x0fa80000 0x0 0x20000>; + clocks =3D <&xo_board>, <&gcc GPLL0>; + clock-names =3D "xo", "gpll0"; + #clock-cells =3D <1>; + #interconnect-cells =3D <1>; + }; + pcie3: pcie@40000000 { compatible =3D "qcom,pcie-ipq5424", "qcom,pcie-ipq9574"; reg =3D <0x0 0x40000000 0x0 0xf1c>, --=20 2.34.1