From nobody Mon Oct 6 08:25:35 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1F39F2749C3; Thu, 24 Jul 2025 08:03:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.10 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753344228; cv=none; b=oeV8D9/wDEHnM49ThgHirSDueXf1hTW8ABXoFGg3rNhkS5GUVXbal+tv48L8fd3FkG/q70F3dU/BEYYmcrYOQaPKMuydT2uzccR1V8NrqN7b9DjSbbRBrh1vhXZn9c0SJRDjLof6vn1TD6AkeIeIuNvaizXhVvjzaAMtlslICCI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753344228; c=relaxed/simple; bh=p3OfQo+a9uQB6l65p1mAORFqE3su7GRtll6CjNHX3NQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=mlrvwF7Jx6D+mmcGS+w0xgjSv3Chu6s1waaloPU8ufDuFTTPuxks24vbreIR+RaXpSk5cIXFCXLVzNOjAZOMvzc9D07BKbyS4rU389+f0+NGD01HUGtyqBAf0cxv/JAmMBkTb/nA29SLmg0xcDYcLOheAorYjxBg/cBR1JaJnqM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=h9i6kDz5; arc=none smtp.client-ip=192.198.163.10 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="h9i6kDz5" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1753344227; x=1784880227; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=p3OfQo+a9uQB6l65p1mAORFqE3su7GRtll6CjNHX3NQ=; b=h9i6kDz5C1ATmAUlJFPXjvjliT/vL5/dTU2DDWuVUTin/Gja8h+cb7t+ Ap0qXwufsXBNuYszTl/lAVtLM1ZsEbx9KyOfZ8hcK0oxwKu/nw0XUBqLC Qw/H9VwswbZcnEk1Q0Ur4qIXU/elieY/PesJkoxdcGeq+hlWwy1gvjo98 lSVIWCQpcIyxkph/kgUAvusnZhabXBctOLlTgT5iU/Ma+RUwTW8YTCcmn LpOM0VIlJ4DFm9Wb5xS3aL8UGAyzah2kEBIGX+ZpXlm5wKHN8cnjER4ux FzF5QqNDMdYXWkMor10qHQEBdYGIPgIQv0domlAkFmmQUZjQgCxhghTKZ A==; X-CSE-ConnectionGUID: wc1U3MAlQSKmvexilRjLiA== X-CSE-MsgGUID: lBqlpDrESGymZTZZqxHpuQ== X-IronPort-AV: E=McAfee;i="6800,10657,11501"; a="66991959" X-IronPort-AV: E=Sophos;i="6.16,336,1744095600"; d="scan'208";a="66991959" Received: from fmviesa009.fm.intel.com ([10.60.135.149]) by fmvoesa104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Jul 2025 01:03:47 -0700 X-CSE-ConnectionGUID: +tsMuZF5TlKnaFSn7WiXMw== X-CSE-MsgGUID: ZkVZ0zwIR5KJ241Dzd+UJw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,336,1744095600"; d="scan'208";a="160341579" Received: from savramon-mobl1 (HELO eresheto-mobl3.ger.corp.intel.com) ([10.245.244.60]) by fmviesa009-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Jul 2025 01:03:42 -0700 From: Elena Reshetova To: dave.hansen@intel.com Cc: jarkko@kernel.org, seanjc@google.com, kai.huang@intel.com, mingo@kernel.org, linux-sgx@vger.kernel.org, linux-kernel@vger.kernel.org, x86@kernel.org, asit.k.mallick@intel.com, vincent.r.scarlata@intel.com, chongc@google.com, erdemaktas@google.com, vannapurve@google.com, bondarn@google.com, scott.raynor@intel.com, Elena Reshetova Subject: [PATCH v9 3/6] x86/cpufeatures: Add X86_FEATURE_SGX_EUPDATESVN feature flag Date: Thu, 24 Jul 2025 11:02:12 +0300 Message-ID: <20250724080313.605676-4-elena.reshetova@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250724080313.605676-1-elena.reshetova@intel.com> References: <20250724080313.605676-1-elena.reshetova@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add a flag indicating whenever ENCLS[EUPDATESVN] SGX instruction is supported. This will be used by SGX driver to perform CPU SVN updates. Signed-off-by: Elena Reshetova --- arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/kernel/cpu/cpuid-deps.c | 1 + arch/x86/kernel/cpu/scattered.c | 1 + tools/arch/x86/include/asm/cpufeatures.h | 1 + 4 files changed, 4 insertions(+) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpuf= eatures.h index 602957dd2609..830d24ff1ada 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -494,6 +494,7 @@ #define X86_FEATURE_TSA_SQ_NO (21*32+11) /* AMD CPU not vulnerable to TSA= -SQ */ #define X86_FEATURE_TSA_L1_NO (21*32+12) /* AMD CPU not vulnerable to TSA= -L1 */ #define X86_FEATURE_CLEAR_CPU_BUF_VM (21*32+13) /* Clear CPU buffers using= VERW before VMRUN */ +#define X86_FEATURE_SGX_EUPDATESVN (21*32+14) /* Support for ENCLS[EUPDATE= SVN] instruction */ =20 /* * BUG word(s) diff --git a/arch/x86/kernel/cpu/cpuid-deps.c b/arch/x86/kernel/cpu/cpuid-d= eps.c index 46efcbd6afa4..3d9f49ad0efd 100644 --- a/arch/x86/kernel/cpu/cpuid-deps.c +++ b/arch/x86/kernel/cpu/cpuid-deps.c @@ -79,6 +79,7 @@ static const struct cpuid_dep cpuid_deps[] =3D { { X86_FEATURE_SGX_LC, X86_FEATURE_SGX }, { X86_FEATURE_SGX1, X86_FEATURE_SGX }, { X86_FEATURE_SGX2, X86_FEATURE_SGX1 }, + { X86_FEATURE_SGX_EUPDATESVN, X86_FEATURE_SGX1 }, { X86_FEATURE_SGX_EDECCSSA, X86_FEATURE_SGX1 }, { X86_FEATURE_XFD, X86_FEATURE_XSAVES }, { X86_FEATURE_XFD, X86_FEATURE_XGETBV1 }, diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattere= d.c index b4a1f6732a3a..d13444d11ba0 100644 --- a/arch/x86/kernel/cpu/scattered.c +++ b/arch/x86/kernel/cpu/scattered.c @@ -42,6 +42,7 @@ static const struct cpuid_bit cpuid_bits[] =3D { { X86_FEATURE_PER_THREAD_MBA, CPUID_ECX, 0, 0x00000010, 3 }, { X86_FEATURE_SGX1, CPUID_EAX, 0, 0x00000012, 0 }, { X86_FEATURE_SGX2, CPUID_EAX, 1, 0x00000012, 0 }, + { X86_FEATURE_SGX_EUPDATESVN, CPUID_EAX, 10, 0x00000012, 0 }, { X86_FEATURE_SGX_EDECCSSA, CPUID_EAX, 11, 0x00000012, 0 }, { X86_FEATURE_HW_PSTATE, CPUID_EDX, 7, 0x80000007, 0 }, { X86_FEATURE_CPB, CPUID_EDX, 9, 0x80000007, 0 }, diff --git a/tools/arch/x86/include/asm/cpufeatures.h b/tools/arch/x86/incl= ude/asm/cpufeatures.h index ee176236c2be..78c3894c17c1 100644 --- a/tools/arch/x86/include/asm/cpufeatures.h +++ b/tools/arch/x86/include/asm/cpufeatures.h @@ -487,6 +487,7 @@ #define X86_FEATURE_PREFER_YMM (21*32+ 8) /* Avoid ZMM registers due to d= ownclocking */ #define X86_FEATURE_APX (21*32+ 9) /* Advanced Performance Extensions */ #define X86_FEATURE_INDIRECT_THUNK_ITS (21*32+10) /* Use thunk for indirec= t branches in lower half of cacheline */ +#define X86_FEATURE_SGX_EUPDATESVN (21*32+14) /* Support for ENCLS[EUPDATE= SVN] instruction */ =20 /* * BUG word(s) --=20 2.45.2