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Thu, 24 Jul 2025 02:29:37 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEUnZ+FdV8B68R/9Vy+pkhhd2kJ0k5uDXNRNy/JfjQ0HCxuulHG3A/9D4Vd/nuHaXer+bLGjg== X-Received: by 2002:a17:902:e84e:b0:234:c8f6:1b17 with SMTP id d9443c01a7336-23f981b3991mr105315745ad.38.1753349377091; Thu, 24 Jul 2025 02:29:37 -0700 (PDT) Received: from hu-tdas-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-23fa475f8a0sm11276505ad.24.2025.07.24.02.29.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Jul 2025 02:29:36 -0700 (PDT) From: Taniya Das Date: Thu, 24 Jul 2025 14:59:13 +0530 Subject: [PATCH v2 5/7] clk: qcom: clk-alpha-pll: Add support for Taycan EKO_T PLL Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250724-glymur_clock_controllers-v2-5-ab95c07002b4@oss.qualcomm.com> References: <20250724-glymur_clock_controllers-v2-0-ab95c07002b4@oss.qualcomm.com> In-Reply-To: <20250724-glymur_clock_controllers-v2-0-ab95c07002b4@oss.qualcomm.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Taniya Das , Dmitry Baryshkov X-Mailer: b4 0.15-dev-aa3f6 X-Proofpoint-GUID: 84hKGc6s76757IF-vnigXgwkSgBVmePG X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzI0MDA2OCBTYWx0ZWRfX3k2Rw9srqls6 m51Tl7WPhikH5sIfg32PCsyF4FrtMG7TReJltNYQJVYj5UisiSvAW+4euVHcCra1o4s5IxZls1m VsNtP4ZTLXDOh9RXLocUD3Tww0y+oc36F/P2xI3wXwiSJ9xPY6thN13dX1B202RlRDcPvGVDSeC NrKIG1PCX6y2B0yYHS87eYItiy1hirtPzvTj+pjmqnGCHmVa3B7ccYZUY5pLuDDNp2sJkgOqL0m +89YCRar+Bz6puiIzsBlUM49b2bVmDZpEDPwwT43686j7PjYORnz4BWWDHvPpsbLQb7oxAu51DJ YiPaorLT18aaCeXfCQ+EWpKbHq+u/unju6JKGmZew4mGHunmW0u6jZ+83iKMUizM/LUoC9yOfKW Ekrkn9zoznF+Q2UtCyteFgG7JNa+6Esd0XVwQ5umNzW8I7O9WWZqBsIN3c+5xnWIvUBWeXdG X-Authority-Analysis: v=2.4 cv=E8/Npbdl c=1 sm=1 tr=0 ts=6881fd02 cx=c_pps a=cmESyDAEBpBGqyK7t0alAg==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=Wb1JkmetP80A:10 a=EUspDBNiAAAA:8 a=9yNAuCQw4ehsCnPPvT8A:9 a=QEXdDO2ut3YA:10 a=1OuFwYUASf3TG4hYMiVC:22 X-Proofpoint-ORIG-GUID: 84hKGc6s76757IF-vnigXgwkSgBVmePG X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-24_01,2025-07-23_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 malwarescore=0 spamscore=0 bulkscore=0 lowpriorityscore=0 priorityscore=1501 adultscore=0 suspectscore=0 clxscore=1015 phishscore=0 mlxlogscore=999 mlxscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507240068 Add clock operations and register offsets to enable control of the Taycan EKO_T PLL, allowing for proper configuration and management of the PLL. Reviewed-by: Dmitry Baryshkov Signed-off-by: Taniya Das --- drivers/clk/qcom/clk-alpha-pll.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-= pll.h index ff41aeab0ab9844cd4e43c9b8e1ba0b50205e48e..0903a05b18ccc68c9f8de5c7405= bb197bf8d3d1d 100644 --- a/drivers/clk/qcom/clk-alpha-pll.h +++ b/drivers/clk/qcom/clk-alpha-pll.h @@ -29,6 +29,7 @@ enum { CLK_ALPHA_PLL_TYPE_LUCID_OLE, CLK_ALPHA_PLL_TYPE_PONGO_ELU, CLK_ALPHA_PLL_TYPE_TAYCAN_ELU, + CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T =3D CLK_ALPHA_PLL_TYPE_TAYCAN_ELU, CLK_ALPHA_PLL_TYPE_RIVIAN_EVO, CLK_ALPHA_PLL_TYPE_DEFAULT_EVO, CLK_ALPHA_PLL_TYPE_BRAMMO_EVO, @@ -192,14 +193,17 @@ extern const struct clk_ops clk_alpha_pll_zonda_ops; =20 extern const struct clk_ops clk_alpha_pll_lucid_evo_ops; #define clk_alpha_pll_taycan_elu_ops clk_alpha_pll_lucid_evo_ops +#define clk_alpha_pll_taycan_eko_t_ops clk_alpha_pll_lucid_evo_ops extern const struct clk_ops clk_alpha_pll_reset_lucid_evo_ops; #define clk_alpha_pll_reset_lucid_ole_ops clk_alpha_pll_reset_lucid_evo_ops extern const struct clk_ops clk_alpha_pll_fixed_lucid_evo_ops; #define clk_alpha_pll_fixed_lucid_ole_ops clk_alpha_pll_fixed_lucid_evo_ops #define clk_alpha_pll_fixed_taycan_elu_ops clk_alpha_pll_fixed_lucid_evo_o= ps +#define clk_alpha_pll_fixed_taycan_eko_t_ops clk_alpha_pll_fixed_lucid_evo= _ops extern const struct clk_ops clk_alpha_pll_postdiv_lucid_evo_ops; #define clk_alpha_pll_postdiv_lucid_ole_ops clk_alpha_pll_postdiv_lucid_ev= o_ops #define clk_alpha_pll_postdiv_taycan_elu_ops clk_alpha_pll_postdiv_lucid_e= vo_ops +#define clk_alpha_pll_postdiv_taycan_eko_t_ops clk_alpha_pll_postdiv_lucid= _evo_ops =20 extern const struct clk_ops clk_alpha_pll_pongo_elu_ops; extern const struct clk_ops clk_alpha_pll_rivian_evo_ops; @@ -233,6 +237,8 @@ void clk_pongo_elu_pll_configure(struct clk_alpha_pll *= pll, struct regmap *regma const struct alpha_pll_config *config); #define clk_taycan_elu_pll_configure(pll, regmap, config) \ clk_lucid_evo_pll_configure(pll, regmap, config) +#define clk_taycan_eko_t_pll_configure(pll, regmap, config) \ + clk_lucid_evo_pll_configure(pll, regmap, config) =20 void clk_rivian_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap= *regmap, const struct alpha_pll_config *config); --=20 2.34.1