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[76.133.73.115]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-23fa48bc6fbsm1260765ad.120.2025.07.23.16.30.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Jul 2025 16:30:32 -0700 (PDT) From: rentao.bupt@gmail.com To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , Andrew Jeffery , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-aspeed@lists.ozlabs.org, linux-kernel@vger.kernel.org, Andrew Lunn , Tao Ren Cc: Tao Ren Subject: [PATCH v3 08/13] ARM: dts: aspeed: wedge400: Include wedge400-data64.dts Date: Wed, 23 Jul 2025 16:30:04 -0700 Message-ID: <20250723233013.142337-9-rentao.bupt@gmail.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20250723233013.142337-1-rentao.bupt@gmail.com> References: <20250723233013.142337-1-rentao.bupt@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Tao Ren Include "wedge400-data64.dts" in wedge400 dts to avoid duplicated code. Wedge400-data64 and Wedge400 are identical except the BMC flash layout. Signed-off-by: Tao Ren --- Changes in v3: - None (the patch is introduced in v3). .../aspeed/aspeed-bmc-facebook-wedge400.dts | 366 +----------------- 1 file changed, 2 insertions(+), 364 deletions(-) diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-wedge400.dts b/ar= ch/arm/boot/dts/aspeed/aspeed-bmc-facebook-wedge400.dts index 3e4d30f0884d..ef0cfc51cda4 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-wedge400.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-wedge400.dts @@ -1,376 +1,14 @@ // SPDX-License-Identifier: GPL-2.0+ // Copyright (c) 2019 Facebook Inc. -/dts-v1/; =20 -#include -#include "ast2500-facebook-netbmc-common.dtsi" +#include "aspeed-bmc-facebook-wedge400-data64.dts" =20 / { model =3D "Facebook Wedge 400 BMC"; compatible =3D "facebook,wedge400-bmc", "aspeed,ast2500"; - - aliases { - /* - * PCA9548 (2-0070) provides 8 channels connecting to - * SCM (System Controller Module). - */ - i2c16 =3D &imux16; - i2c17 =3D &imux17; - i2c18 =3D &imux18; - i2c19 =3D &imux19; - i2c20 =3D &imux20; - i2c21 =3D &imux21; - i2c22 =3D &imux22; - i2c23 =3D &imux23; - - /* - * PCA9548 (8-0070) provides 8 channels connecting to - * SMB (Switch Main Board). - */ - i2c24 =3D &imux24; - i2c25 =3D &imux25; - i2c26 =3D &imux26; - i2c27 =3D &imux27; - i2c28 =3D &imux28; - i2c29 =3D &imux29; - i2c30 =3D &imux30; - i2c31 =3D &imux31; - - /* - * PCA9548 (11-0076) provides 8 channels connecting to - * FCM (Fan Controller Module). - */ - i2c32 =3D &imux32; - i2c33 =3D &imux33; - i2c34 =3D &imux34; - i2c35 =3D &imux35; - i2c36 =3D &imux36; - i2c37 =3D &imux37; - i2c38 =3D &imux38; - i2c39 =3D &imux39; - - spi2 =3D &spi_gpio; - }; - - chosen { - stdout-path =3D &uart1; - bootargs =3D "console=3DttyS0,9600n8 root=3D/dev/ram rw"; - }; - - ast-adc-hwmon { - compatible =3D "iio-hwmon"; - io-channels =3D <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, <&adc 4>, - <&adc 5>, <&adc 6>, <&adc 7>, <&adc 8>; - }; - - /* - * GPIO-based SPI Master is required to access SPI TPM, because - * full-duplex SPI transactions are not supported by ASPEED SPI - * Controllers. - */ - spi_gpio: spi { - status =3D "okay"; - compatible =3D "spi-gpio"; - #address-cells =3D <1>; - #size-cells =3D <0>; - - cs-gpios =3D <&gpio ASPEED_GPIO(R, 2) GPIO_ACTIVE_LOW>; - sck-gpios =3D <&gpio ASPEED_GPIO(R, 3) GPIO_ACTIVE_HIGH>; - mosi-gpios =3D <&gpio ASPEED_GPIO(R, 4) GPIO_ACTIVE_HIGH>; - miso-gpios =3D <&gpio ASPEED_GPIO(R, 5) GPIO_ACTIVE_HIGH>; - num-chipselects =3D <1>; - - tpm@0 { - compatible =3D "infineon,slb9670", "tcg,tpm_tis-spi"; - spi-max-frequency =3D <33000000>; - reg =3D <0>; - }; - }; }; =20 -/* - * Both firmware flashes are 128MB on Wedge400 BMC. - */ &fmc_flash0 { + /delete-node/partitions; #include "facebook-bmc-flash-layout-128.dtsi" }; - -&fmc_flash1 { - partitions { - compatible =3D "fixed-partitions"; - #address-cells =3D <1>; - #size-cells =3D <1>; - - flash1@0 { - reg =3D <0x0 0x8000000>; - label =3D "flash1"; - }; - }; -}; - -&uart2 { - status =3D "okay"; - pinctrl-names =3D "default"; - pinctrl-0 =3D <&pinctrl_txd2_default - &pinctrl_rxd2_default>; -}; - -&uart4 { - status =3D "okay"; - pinctrl-names =3D "default"; - pinctrl-0 =3D <&pinctrl_txd4_default - &pinctrl_rxd4_default>; -}; - -/* - * I2C bus #0 is multi-master environment dedicated for BMC and Bridge IC - * communication. - */ -&i2c0 { - status =3D "okay"; - multi-master; - bus-frequency =3D <1000000>; -}; - -&i2c1 { - status =3D "okay"; -}; - -&i2c2 { - status =3D "okay"; - - i2c-mux@70 { - compatible =3D "nxp,pca9548"; - #address-cells =3D <1>; - #size-cells =3D <0>; - reg =3D <0x70>; - i2c-mux-idle-disconnect; - - imux16: i2c@0 { - #address-cells =3D <1>; - #size-cells =3D <0>; - reg =3D <0>; - }; - - imux17: i2c@1 { - #address-cells =3D <1>; - #size-cells =3D <0>; - reg =3D <1>; - }; - - imux18: i2c@2 { - #address-cells =3D <1>; - #size-cells =3D <0>; - reg =3D <2>; - }; - - imux19: i2c@3 { - #address-cells =3D <1>; - #size-cells =3D <0>; - reg =3D <3>; - }; - - imux20: i2c@4 { - #address-cells =3D <1>; - #size-cells =3D <0>; - reg =3D <4>; - }; - - imux21: i2c@5 { - #address-cells =3D <1>; - #size-cells =3D <0>; - reg =3D <5>; - }; - - imux22: i2c@6 { - #address-cells =3D <1>; - #size-cells =3D <0>; - reg =3D <6>; - }; - - imux23: i2c@7 { - #address-cells =3D <1>; - #size-cells =3D <0>; - reg =3D <7>; - }; - }; -}; - -&i2c3 { - status =3D "okay"; -}; - -&i2c4 { - status =3D "okay"; -}; - -&i2c5 { - status =3D "okay"; -}; - -&i2c6 { - status =3D "okay"; -}; - -&i2c7 { - status =3D "okay"; -}; - -&i2c8 { - status =3D "okay"; - - i2c-mux@70 { - compatible =3D "nxp,pca9548"; - #address-cells =3D <1>; - #size-cells =3D <0>; - reg =3D <0x70>; - i2c-mux-idle-disconnect; - - imux24: i2c@0 { - #address-cells =3D <1>; - #size-cells =3D <0>; - reg =3D <0>; - }; - - imux25: i2c@1 { - #address-cells =3D <1>; - #size-cells =3D <0>; - reg =3D <1>; - }; - - imux26: i2c@2 { - #address-cells =3D <1>; - #size-cells =3D <0>; - reg =3D <2>; - }; - - imux27: i2c@3 { - #address-cells =3D <1>; - #size-cells =3D <0>; - reg =3D <3>; - }; - - imux28: i2c@4 { - #address-cells =3D <1>; - #size-cells =3D <0>; - reg =3D <4>; - }; - - imux29: i2c@5 { - #address-cells =3D <1>; - #size-cells =3D <0>; - reg =3D <5>; - }; - - imux30: i2c@6 { - #address-cells =3D <1>; - #size-cells =3D <0>; - reg =3D <6>; - }; - - imux31: i2c@7 { - #address-cells =3D <1>; - #size-cells =3D <0>; - reg =3D <7>; - }; - - }; -}; - -&i2c9 { - status =3D "okay"; -}; - -&i2c10 { - status =3D "okay"; -}; - -&i2c11 { - status =3D "okay"; - - i2c-mux@76 { - compatible =3D "nxp,pca9548"; - #address-cells =3D <1>; - #size-cells =3D <0>; - reg =3D <0x76>; - i2c-mux-idle-disconnect; - - imux32: i2c@0 { - #address-cells =3D <1>; - #size-cells =3D <0>; - reg =3D <0>; - }; - - imux33: i2c@1 { - #address-cells =3D <1>; - #size-cells =3D <0>; - reg =3D <1>; - }; - - imux34: i2c@2 { - #address-cells =3D <1>; - #size-cells =3D <0>; - reg =3D <2>; - }; - - imux35: i2c@3 { - #address-cells =3D <1>; - #size-cells =3D <0>; - reg =3D <3>; - }; - - imux36: i2c@4 { - #address-cells =3D <1>; - #size-cells =3D <0>; - reg =3D <4>; - }; - - imux37: i2c@5 { - #address-cells =3D <1>; - #size-cells =3D <0>; - reg =3D <5>; - }; - - imux38: i2c@6 { - #address-cells =3D <1>; - #size-cells =3D <0>; - reg =3D <6>; - }; - - imux39: i2c@7 { - #address-cells =3D <1>; - #size-cells =3D <0>; - reg =3D <7>; - }; - - }; -}; - -&i2c12 { - status =3D "okay"; -}; - -&i2c13 { - status =3D "okay"; -}; - -&adc { - status =3D "okay"; -}; - -&ehci1 { - status =3D "okay"; -}; - -&uhci { - status =3D "okay"; -}; - -&sdhci1 { - max-frequency =3D <25000000>; - /* - * DMA mode needs to be disabled to avoid conflicts with UHCI - * Controller in AST2500 SoC. - */ - sdhci-caps-mask =3D <0x0 0x580000>; -}; --=20 2.47.3