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Wed, 23 Jul 2025 15:23:53 -0700 From: Donald Shannon To: , , CC: , , , , , , , Donald Shannon Subject: [PATCH v7 1/2] dt-bindings: arm: aspeed: Add NVIDIA GB200-UT3.0b board Date: Wed, 23 Jul 2025 15:23:49 -0700 Message-ID: <20250723222350.200094-2-donalds@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250723222350.200094-1-donalds@nvidia.com> References: <20250723222350.200094-1-donalds@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000066ED:EE_|DM4PR12MB6087:EE_ X-MS-Office365-Filtering-Correlation-Id: f8bd7142-178f-45cc-537f-08ddca37a426 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|7416014|36860700013|376014|1800799024; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?ygGTckY4NrN4szaudb5Jx7W/0bN1nR2h9Z8gRFOZXKDEHVTa6qMFMC4EhfPG?= =?us-ascii?Q?3/B0WRphZONMhVLD4BqZ2dIy4gSwlB0fumeFUMJAHRl6m4KrcGWIlCVbkWP+?= =?us-ascii?Q?DXQt1SepZEZWq8fglXY8IaRRSm7c8tBPaoqwls5Q0p7zrDC4SYsPDgaCbgOs?= =?us-ascii?Q?UmuKXKAxMPQOUUysewrxhZCHVWZm/ROYizvTwHZB0+mpdQlOjW3rusNhnXTo?= =?us-ascii?Q?Q36xXDXv2EJDmQFyDU4GTITw3vBteJhxHWHj4v2sHpeeG5nWHOhff6WtZjwk?= =?us-ascii?Q?aGrQXyB/MKgfEaK3xgLULrNW8MfpF07Njwvj2dWokZiJBESPLwLx4NLLoGm7?= =?us-ascii?Q?20oCsQu4A6x+x5OAq4+msq/ef5X2UQ9ewHvcFJDKSKTDdqzrnjMBJwGNngEr?= =?us-ascii?Q?fMCgWffNwHGz2WiSn81YmxQjOKQMEMzkujv30L78PKTsxPHE5UH0B/4buomH?= =?us-ascii?Q?/HolMvcF0ZFdm2ZA6nC9sT+Z/xJ93Y38PlqcbRK6raWwkk0Atm+R5E6uTR/l?= =?us-ascii?Q?Bjfpul/XhM9jS8rmUN52FnUlP5OQ7CNXLI4wUH5/U6e38l0quLmgdpJ5ONFs?= =?us-ascii?Q?oxL5EAqnno3rCh4AZO9rmRjMVG36bl6DAGfhIIiShF+/+HOyWmuAhIgCvWTa?= =?us-ascii?Q?p5Avot81rxT65vLp0kC7Zs2Iuo7py+xvsGLQYnWBa006En/rZs7AcVg4jn9t?= =?us-ascii?Q?KHWUZ7A7sd+qphrZhiY7+WU7tMwR/Np8gz+jwsf32dIRoayhee7Gn+2fHY1k?= =?us-ascii?Q?Hu4st8mbhyPBL8GJdWxS1bBccJvZJNTrHSwh1SlVBz5p/ugwleXHpQlXxlpP?= =?us-ascii?Q?5zj6hODu2P9saOY9i8LeGxRoXkGRBMHOgVpMtXELOquR+P7C5Khg+FJwDf6y?= =?us-ascii?Q?Z2YLOFtUR3aobMRitmW7fPhujJPkGKnVyNSNfW3aq4brU6FgF7c1vIHiXbYp?= =?us-ascii?Q?7Z0IPZ3lpwtAZ71yNtgFP9Xlx0ZkprZ8SaAogsvvW9iMjSNhjYtKZ8l1+r3a?= =?us-ascii?Q?Err1EPbwd0DWF2nDDB8mxFYevGBDn5D84Q3eabB742z/8cuHH6Z21LbMqQC0?= =?us-ascii?Q?RqIytn3nA5sMycUOKMVmAvwBtgA69VMBSrNg0bt1XLNTYL4QM3C6WTdsYcaW?= =?us-ascii?Q?CIWNRCyXuT/nZ2hRYiVzYXWu3FlxtffloqHifvBCIPrJ5UaznK3KmqV2G4IT?= =?us-ascii?Q?SkmdZbjX4rp3RYFNcNE8KOCKdILfwbVNuIkK0/KD0dkDeqH/Eh/ORtlZ9fBx?= =?us-ascii?Q?4RJ+011LSEFlL1NEgp+n09yeftgR6U7QS1KfjdFjvKgxAkcrZcaMqpIhMhyq?= =?us-ascii?Q?VyJxZq7ty2Ki2kDP4Gd4X2FyBox5NKNbDlQ3e7lp/gpGH7UaQ6zdj9bqYXtp?= =?us-ascii?Q?X8v5FmwX8kzevylyEIhVsFXzJQnidV+uS3iDeyVmVXDlNyKJytdLEa1n8n5X?= =?us-ascii?Q?uM82sGQ9Bhf9i8V6KvjDZVxBUra2YNHfdQkWUz95IUFVw3pEE31OLkjEp+ZE?= =?us-ascii?Q?SSTTzRvrnVRgC5NKexY/rtI6l9YG8j6+v5XO?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(7416014)(36860700013)(376014)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Jul 2025 22:24:08.1430 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f8bd7142-178f-45cc-537f-08ddca37a426 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000066ED.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB6087 Content-Type: text/plain; charset="utf-8" This is an Aspeed AST2600 based unit testing platform for GB200. UT3.0b is different than nvidia-gb200nvl-bmc due to networking topology differences, additional gpio expanders, and voltage regulator gating some devices. Reference to Ast2600 SOC [1]. Reference to Blackwell GB200NVL Platform [2]. Link: https://www.aspeedtech.com/server_ast2600/ [1] Link: https://nvdam.widen.net/s/wwnsxrhm2w/blackwell-datasheet-3384703 [2] Signed-off-by: Donald Shannon --- Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml b/Doc= umentation/devicetree/bindings/arm/aspeed/aspeed.yaml index 456dbf7b5ec8..624581db2330 100644 --- a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml +++ b/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml @@ -99,6 +99,7 @@ properties: - inventec,starscream-bmc - inventec,transformer-bmc - jabil,rbp-bmc + - nvidia,gb200-ut30b - nvidia,gb200nvl-bmc - qcom,dc-scm-v1-bmc - quanta,s6q-bmc --=20 2.43.0 From nobody Mon Oct 6 06:40:55 2025 Received: from NAM04-BN8-obe.outbound.protection.outlook.com (mail-bn8nam04on2046.outbound.protection.outlook.com [40.107.100.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2579C273D87; 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Wed, 23 Jul 2025 15:23:54 -0700 Received: from rnnvmail203.nvidia.com (10.129.68.9) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.14; Wed, 23 Jul 2025 15:23:54 -0700 Received: from dondevbox.nvidia.com (10.127.8.13) by mail.nvidia.com (10.129.68.9) with Microsoft SMTP Server id 15.2.1544.14 via Frontend Transport; Wed, 23 Jul 2025 15:23:54 -0700 From: Donald Shannon To: , , CC: , , , , , , , Donald Shannon Subject: [PATCH v7 2/2] ARM: dts: aspeed: Add NVIDIA GB200 UT3.0b board Date: Wed, 23 Jul 2025 15:23:50 -0700 Message-ID: <20250723222350.200094-3-donalds@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250723222350.200094-1-donalds@nvidia.com> References: <20250723222350.200094-1-donalds@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000066EC:EE_|SJ2PR12MB8925:EE_ X-MS-Office365-Filtering-Correlation-Id: 9447000c-aacb-4673-d609-08ddca37a466 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|376014|36860700013|7416014|1800799024|13003099007; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Jul 2025 22:24:08.5636 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9447000c-aacb-4673-d609-08ddca37a466 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000066EC.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB8925 Content-Type: text/plain; charset="utf-8" This is an Aspeed AST2600 based unit testing platform for GB200. UT3.0b is different than nvidia-gb200nvl-bmc due to networking topology differences, additional gpio expanders, and voltage regulator gating some devices. Reference to Ast2600 SOC [1]. Reference to Blackwell GB200NVL Platform [2]. Link: https://www.aspeedtech.com/server_ast2600/ [1] Link: https://nvdam.widen.net/s/wwnsxrhm2w/blackwell-datasheet-3384703 [2] Signed-off-by: Donald Shannon --- Changes v1 -> v2: - Changed phy-mode to rgmii-id [Lunn] - Removed redundant max-speed for mac0 [Lunn] - Fixed typo from gb200nvl to gb200 in Makefile Changes v2 -> v3: - Fixed whitespace issues [Krzysztof] - Fixed schema validation issues from my end ( there are still issues with the aspeed dtsi file that are not related to this new dts) [Herring] - Reordered to follow style guide [Krzysztof] - Removed redundant status okays - Changed vcc to vdd for the power gating on the gpio expanders Changes v3 -> v4: - Added changelog [Krzysztof] - Added nvidia,gb200-ut30b board binding [Krzysztof] - Removed unused imports - Reordered a couple other style guide violations - Added back in a couple needed "status okay"s Changes v4 -> v5: - Resumed my patch after a pause - Don't plan to make this include of nvidia-gb200nvl-bmc due to some platform differences - Fixed io expanders that weren't gated by the 3.3V standby regulator - Fixed incorrect interrupt pin for one IO expander - Removed some IO expanders and I2C busses Changes v5 -> v6: - Fixed subject line - Added missing gpio-key compatible type to buttons Changes v6 -> v7: - Removed Acked-by Krzysztof --- arch/arm/boot/dts/aspeed/Makefile | 1 + .../aspeed/aspeed-bmc-nvidia-gb200-ut30b.dts | 1028 +++++++++++++++++ 2 files changed, 1029 insertions(+) create mode 100644 arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-gb200-ut30b.= dts diff --git a/arch/arm/boot/dts/aspeed/Makefile b/arch/arm/boot/dts/aspeed/M= akefile index aba7451ab749..37edc4625a9f 100644 --- a/arch/arm/boot/dts/aspeed/Makefile +++ b/arch/arm/boot/dts/aspeed/Makefile @@ -51,6 +51,7 @@ dtb-$(CONFIG_ARCH_ASPEED) +=3D \ aspeed-bmc-lenovo-hr630.dtb \ aspeed-bmc-lenovo-hr855xg2.dtb \ aspeed-bmc-microsoft-olympus.dtb \ + aspeed-bmc-nvidia-gb200-ut30b.dtb \ aspeed-bmc-nvidia-gb200nvl-bmc.dtb \ aspeed-bmc-opp-lanyang.dtb \ aspeed-bmc-opp-mowgli.dtb \ diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-gb200-ut30b.dts b/a= rch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-gb200-ut30b.dts new file mode 100644 index 000000000000..e0714ad796df --- /dev/null +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-gb200-ut30b.dts @@ -0,0 +1,1028 @@ +// SPDX-License-Identifier: GPL-2.0+ +/dts-v1/; + +#include "aspeed-g6.dtsi" +#include + +/ { + model =3D "AST2600 GB200 UT3.0b BMC"; + compatible =3D "nvidia,gb200-ut30b", "aspeed,ast2600"; + + aliases { + serial2 =3D &uart3; + serial4 =3D &uart5; + i2c16 =3D &imux16; + i2c17 =3D &imux17; + i2c18 =3D &imux18; + i2c19 =3D &imux19; + i2c20 =3D &imux20; + i2c21 =3D &imux21; + i2c22 =3D &imux22; + i2c23 =3D &imux23; + i2c24 =3D &imux24; + i2c25 =3D &imux25; + i2c26 =3D &imux26; + i2c27 =3D &imux27; + i2c28 =3D &imux28; + i2c29 =3D &imux29; + i2c30 =3D &imux30; + i2c31 =3D &imux31; + i2c32 =3D &imux32; + i2c33 =3D &imux33; + i2c34 =3D &imux34; + i2c35 =3D &imux35; + i2c36 =3D &imux36; + i2c37 =3D &imux37; + i2c38 =3D &imux38; + i2c39 =3D &imux39; + i2c40 =3D &e1si2c0; + i2c41 =3D &e1si2c1; + i2c42 =3D &e1si2c2; + i2c43 =3D &e1si2c3; + i2c48 =3D &i2c17mux0; + i2c49 =3D &i2c17mux1; + i2c50 =3D &i2c17mux2; + i2c51 =3D &i2c17mux3; + i2c52 =3D &i2c25mux0; + i2c53 =3D &i2c25mux1; + i2c54 =3D &i2c25mux2; + i2c55 =3D &i2c25mux3; + i2c56 =3D &i2c29mux0; + i2c57 =3D &i2c29mux1; + i2c58 =3D &i2c29mux2; + i2c59 =3D &i2c29mux3; + }; + + buttons { + compatible =3D "gpio-keys"; + button-power { + label =3D "power-btn"; + gpio =3D <&sgpiom0 156 GPIO_ACTIVE_LOW>; + }; + button-uid { + label =3D "uid-btn"; + gpio =3D <&sgpiom0 154 GPIO_ACTIVE_LOW>; + }; + }; + + chosen { + stdout-path =3D &uart5; + }; + + leds { + compatible =3D "gpio-leds"; + led-0 { + label =3D "uid_led"; + gpios =3D <&sgpiom0 27 GPIO_ACTIVE_LOW>; + }; + led-1 { + label =3D "fault_led"; + gpios =3D <&sgpiom0 29 GPIO_ACTIVE_LOW>; + }; + led-2 { + label =3D "power_led"; + gpios =3D <&sgpiom0 31 GPIO_ACTIVE_LOW>; + }; + }; + + memory@80000000 { + device_type =3D "memory"; + reg =3D <0x80000000 0x80000000>; + }; + + reg_3v3_stby: regulator-3v3-standby { + compatible =3D "regulator-fixed"; + regulator-name =3D "3v3-standby"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + gpio =3D <&gpio0 ASPEED_GPIO(M, 3) GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + reserved-memory { + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges; + + vga_memory: framebuffer@9f000000 { + no-map; + reg =3D <0x9f000000 0x01000000>; /* 16M */ + }; + + ramoops@a0000000 { + compatible =3D "ramoops"; + reg =3D <0xa0000000 0x100000>; /* 1MB */ + record-size =3D <0x10000>; /* 64KB */ + max-reason =3D <2>; /* KMSG_DUMP_OOPS */ + }; + + gfx_memory: framebuffer { + compatible =3D "shared-dma-pool"; + reusable; + size =3D <0x01000000>; + alignment =3D <0x01000000>; + }; + + video_engine_memory: jpegbuffer { + compatible =3D "shared-dma-pool"; + reusable; + size =3D <0x02000000>; /* 32M */ + alignment =3D <0x01000000>; + }; + }; +}; + +// Enable Primary flash on FMC for bring up activity +&fmc { + status =3D "okay"; + flash@0 { + compatible =3D "jedec,spi-nor"; + label =3D "bmc"; + spi-max-frequency =3D <50000000>; + status =3D "okay"; + partitions { + compatible =3D "fixed-partitions"; + #address-cells =3D <1>; + #size-cells =3D <1>; + + u-boot@0 { + // 896KB + reg =3D <0x0 0xe0000>; + label =3D "u-boot"; + }; + + kernel@100000 { + // 9MB + reg =3D <0x100000 0x900000>; + label =3D "kernel"; + }; + + rofs@a00000 { + // 55292KB (extends to end of 64MB SPI - 4KB) + reg =3D <0xa00000 0x35FF000>; + label =3D "rofs"; + }; + }; + }; +}; + +&spi2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_spi2_default>; + status =3D "okay"; + // Data SPI is 64MB in size + flash@0 { + label =3D "config"; + spi-max-frequency =3D <50000000>; + status =3D "okay"; + partitions { + compatible =3D "fixed-partitions"; + #address-cells =3D <1>; + #size-cells =3D <1>; + + u-boot-env@0 { + // 256KB + reg =3D <0x0 0x40000>; + label =3D "u-boot-env"; + }; + + rwfs@40000 { + // 16MB + reg =3D <0x40000 0x1000000>; + label =3D "rwfs"; + }; + + log@1040000 { + // 40MB + reg =3D <0x1040000 0x2800000>; + label =3D "log"; + }; + }; + }; +}; + +&mdio0 { + status =3D "okay"; + ethphy0: ethernet-phy@0 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <0>; + }; +}; + +&mac0 { + pinctrl-names =3D "default"; + phy-mode =3D "rgmii-id"; + phy-handle =3D <ðphy0>; + pinctrl-0 =3D <&pinctrl_rgmii1_default>; + status =3D "okay"; +}; + +// USB Port B Controller +&ehci1 { + status =3D "okay"; +}; + +// USB Port B Controller +&uhci { + status =3D "okay"; +}; + +// USB port A vhub +&vhub { + status =3D "okay"; +}; + +&rng { + status =3D "okay"; +}; + +&video { + memory-region =3D <&video_engine_memory>; + status =3D "okay"; +}; + +&gpio0 { + gpio-line-names =3D + /*A0-A7*/ "", "", "", "", "", "", "", "", + /*B0-B7*/ "", "", "", "", "", "", "", "", + /*C0-C7*/ "SGPIO_I2C_MUX_SEL-O", "", "", "", "", "", "", "", + /*D0-D7*/ "", "", "", "UART1_MUX_SEL-O", "", "FPGA_PEX_RST_L-O", "", "", + /*E0-E7*/ "RTL8221_PHY_RST_L-O", "RTL8211_PHY_INT_L-I", "", "UART3_MUX_S= EL-O", + "", "", "", "SGPIO_BMC_EN-O", + /*F0-F7*/ "", "", "", "", "", "", "", "", + /*G0-G7*/ "", "", "", "", "", "", "", "", + /*H0-H7*/ "", "", "", "", "", "", "", "", + /*I0-I7*/ "", "", "", "", "", "QSPI2_RST_L-O", "GLOBAL_WP_BMC-O", "BMC_D= DR4_TEN-O", + /*J0-J7*/ "", "", "", "", "", "", "", "", + /*K0-K7*/ "", "", "", "", "", "", "", "", + /*L0-L7*/ "", "", "", "", "", "", "", "", + /*M0-M7*/ "PCIE_EP_RST_EN-O", "BMC_FRU_WP-O", "FPGA_RST_L-O", "STBY_POWE= R_EN-O", + "STBY_POWER_PG-I", "PCIE_EP_RST_L-O", "", "", + /*N0-N7*/ "", "", "", "", "", "", "", "", + /*O0-O7*/ "", "", "", "", "", "", "", "", + /*P0-P7*/ "", "", "", "", "", "", "", "", + /*Q0-Q7*/ "", "", "", "", "", "", "", "", + /*R0-R7*/ "", "", "", "", "", "", "", "", + /*S0-S7*/ "", "", "", "", "", "", "", "", + /*T0-T7*/ "", "", "", "", "", "", "", "", + /*U0-U7*/ "", "", "", "", "", "", "", "", + /*V0-V7*/ "AP_EROT_REQ-O", "EROT_AP_GNT-I", "", "","PCB_TEMP_ALERT-I", "= ","", "", + /*W0-W7*/ "", "", "", "", "", "", "", "", + /*X0-X7*/ "", "", "TPM_MUX_SEL-O", "", "", "", "", "", + /*Y0-Y7*/ "", "", "", "EMMC_RST-O", "","", "", "", + /*Z0-Z7*/ "BMC_READY-O","", "", "", "", "", "", ""; +}; + +&gpio1 { + /* 36 1.8V GPIOs */ + gpio-line-names =3D + /*A0-A7*/ "", "", "", "", "", "", "", "", + /*B0-B7*/ "", "", "", "", "", "", "IO_EXPANDER_INT_L-I","", + /*C0-C7*/ "", "", "", "", "", "", "", "", + /*D0-D7*/ "", "", "", "", "", "", "SPI_HOST_TPM_RST_L-O", "SPI_BMC_FPGA_= INT_L-I", + /*E0-E7*/ "", "", "", "", "", "", "", ""; +}; + +&sgpiom0 { + ngpios =3D <128>; + status =3D "okay"; + gpio-line-names =3D + "","", + "","", + "","", + "","", + "","", + "","", + "","", + "","", + "RUN_POWER_FAULT_L-I","SYS_RST_IN_L-O", + "RUN_POWER_PG-I","PWR_BRAKE_L-O", + "SYS_RST_OUT_L-I","RUN_POWER_EN-O", + "L0L1_RST_REQ_OUT_L-I","SHDN_FORCE_L-O", + "L2_RST_REQ_OUT_L-I","SHDN_REQ_L-O", + "SHDN_OK_L-I","UID_LED_N-O", + "BMC_I2C1_FPGA_ALERT_L-I","SYS_FAULT_LED_N-O", + "BMC_I2C0_FPGA_ALERT_L-I","PWR_LED_N-O", + "FPGA_RSVD_FFU3-I","", + "FPGA_RSVD_FFU2-I","", + "FPGA_RSVD_FFU1-I","", + "FPGA_RSVD_FFU0-I","BMC_I2C_SSIF_ALERT_L-O", + "CPU_BOOT_DONE-I","JTAG_MUX_SELECT-O", + "SPI_BMC_FPGA_INT_L-I","RTC_CLR_L-O", + "THERM_BB_WARN_L-I","UART_MUX_SEL-O", + "THERM_BB_OVERT_L-I","", + "CPU0_UPHY3_PRSNT1_L-I","IOBRD0_RUN_POWER_EN-O", + "CPU0_UPHY3_PRSNT0_L-I","IOBRD1_RUN_POWER_EN-O", + "CPU0_UPHY2_PRSNT1_L-I","FPGA_RSVD_FFU4-O", + "CPU0_UPHY2_PRSNT0_L-I","FPGA_RSVD_FFU5-O", + "CPU0_UPHY1_PRSNT1_L-I","FPGA_RSVD_FFU6-O", + "CPU0_UPHY1_PRSNT0_L-I","FPGA_RSVD_FFU7-O", + "CPU0_UPHY0_PRSNT1_L-I","RSVD_NV_PLT_DETECT-O", + "CPU0_UPHY0_PRSNT0_L-I","SPI1_INT_L-O", + "CPU1_UPHY3_PRSNT1_L-I","", + "CPU1_UPHY3_PRSNT0_L-I","HMC_EROT_MUX_STATUS", + "CPU1_UPHY2_PRSNT1_L-I","", + "CPU1_UPHY2_PRSNT0_L-I","", + "CPU1_UPHY1_PRSNT1_L-I","", + "CPU1_UPHY1_PRSNT0_L-I","", + "CPU1_UPHY0_PRSNT1_L-I","", + "CPU1_UPHY0_PRSNT0_L-I","", + "FAN1_PRESENT_L-I","", + "FAN0_PRESENT_L-I","", + "","", + "IPEX_CABLE_PRSNT_L-I","", + "M2_1_PRSNT_L-I","", + "M2_0_PRSNT_L-I","", + "CPU1_UPHY4_PRSNT1_L-I","", + "CPU0_UPHY4_PRSNT0_L-I","", + "","", + "I2C_RTC_ALERT_L-I","", + "FAN7_PRESENT_L-I","", + "FAN6_PRESENT_L-I","", + "FAN5_PRESENT_L-I","", + "FAN4_PRESENT_L-I","", + "FAN3_PRESENT_L-I","", + "FAN2_PRESENT_L-I","", + "IOBRD0_IOX_INT_L-I","", + "IOBRD1_PRSNT_L-I","", + "IOBRD0_PRSNT_L-I","", + "IOBRD1_PWR_GOOD-I","", + "IOBRD0_PWR_GOOD-I","", + "","", + "","", + "FAN_FAIL_IN_L-I","", + "","", + "","", + "","", + "PDB_CABLE_PRESENT_L-I","", + "","", + "CHASSIS_PWR_BRK_L-I","", + "","", + "IOBRD1_IOX_INT_L-I","", + "10GBE_SMBALRT_L-I","", + "PCIE_WAKE_L-I","", + "I2C_M21_ALERT_L-I","", + "I2C_M20_ALERT_L-I","", + "TRAY_FAST_SHDN_L-I","", + "UID_BTN_N-I","", + "PWR_BTN_L-I","", + "PSU_SMB_ALERT_L-I","", + "","", + "","", + "NODE_LOC_ID[0]-I","", + "NODE_LOC_ID[1]-I","", + "NODE_LOC_ID[2]-I","", + "NODE_LOC_ID[3]-I","", + "NODE_LOC_ID[4]-I","", + "NODE_LOC_ID[5]-I","", + "FAN10_PRESENT_L-I","", + "FAN9_PRESENT_L-I","", + "FAN8_PRESENT_L-I","", + "FPGA1_READY_HMC-I","", + "DP_HPD-I","", + "HMC_I2C3_FPGA_ALERT_L-I","", + "HMC_I2C2_FPGA_ALERT_L-I","", + "FPGA0_READY_HMC-I","", + "","", + "","", + "","", + "","", + "LEAK_DETECT_ALERT_L-I","", + "MOD1_B2B_CABLE_PRESENT_L-I","", + "MOD1_CLINK_CABLE_PRESENT_L-I","", + "FAN11_PRESENT_L-I","", + "","", + "","", + "","", + "","", + "","", + "","", + "","", + "","", + "","", + "","", + "","", + "","", + "","", + "","", + "","", + "","", + "RSVD_SGPIO_IN_CRC[0]","RSVD_SGPIO_O_CRC[7]", + "RSVD_SGPIO_IN_CRC[1]","RSVD_SGPIO_O_CRC[6]", + "RSVD_SGPIO_IN_CRC[2]","RSVD_SGPIO_O_CRC[5]", + "RSVD_SGPIO_IN_CRC[3]","RSVD_SGPIO_O_CRC[4]", + "RSVD_SGPIO_IN_CRC[4]","RSVD_SGPIO_O_CRC[3]", + "RSVD_SGPIO_IN_CRC[5]","RSVD_SGPIO_O_CRC[2]", + "RSVD_SGPIO_IN_CRC[6]","RSVD_SGPIO_O_CRC[1]", + "RSVD_SGPIO_IN_CRC[7]","RSVD_SGPIO_O_CRC[0]"; +}; + +&uart1 { + status =3D "okay"; +}; + +// Enabling SOL +&uart3 { + status =3D "okay"; +}; + +// BMC Debug Console +&uart5 { + status =3D "okay"; +}; + +&uart_routing { }; + +// I2C1, SSIF IPMI interface +&i2c0 { + clock-frequency =3D <400000>; + status =3D "okay"; + ssif-bmc@10 { + compatible =3D "ssif-bmc"; + reg =3D <0x10>; + }; +}; + +// I2C3 +// BMC_I2C0_FPGA - Primary FPGA +&i2c2 { + clock-frequency =3D <400000>; + multi-master; + status =3D "okay"; +}; + +// I2C5 +// RTC Driver +// IO Expander +&i2c4 { + clock-frequency =3D <400000>; + status =3D "okay"; + // Module 0, Expander @0x21 + exp4: gpio@21 { + compatible =3D "nxp,pca9555"; + reg =3D <0x21>; + gpio-controller; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + interrupt-parent =3D <&gpio1>; + interrupts =3D ; + vcc-supply =3D <®_3v3_stby>; + gpio-line-names =3D + "RTC_MUX_SEL-O", + "PCI_MUX_SEL-O", + "TPM_MUX_SEL-O", + "FAN_MUX-SEL-O", + "SGMII_MUX_SEL-O", + "DP_MUX_SEL-O", + "UPHY3_USB_SEL-O", + "NCSI_MUX_SEL-O", + "BMC_PHY_RST-O", + "RTC_CLR_L-O", + "BMC_12V_CTRL-O", + "PS_RUN_IO0_PG-I", + "", + "", + "", + ""; + }; +}; + +// I2C6 +// Module 0/1 I2C MUX x3 +&i2c5 { + clock-frequency =3D <400000>; + multi-master; + status =3D "okay"; + + i2c-mux@71 { + compatible =3D "nxp,pca9546"; + reg =3D <0x71>; + #address-cells =3D <1>; + #size-cells =3D <0>; + i2c-mux-idle-disconnect; + vdd-supply =3D <®_3v3_stby>; + + imux16: i2c@0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0>; + }; + + imux17: i2c@1 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <1>; + + i2c-mux@74 { + compatible =3D "nxp,pca9546"; + reg =3D <0x74>; + #address-cells =3D <1>; + #size-cells =3D <0>; + i2c-mux-idle-disconnect; + vdd-supply =3D <®_3v3_stby>; + + i2c17mux0: i2c@0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0>; + }; + + i2c17mux1: i2c@1 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <1>; + }; + + i2c17mux2: i2c@2 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <2>; + }; + + i2c17mux3: i2c@3 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <3>; + }; + }; + }; + + imux18: i2c@2 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <2>; + }; + + imux19: i2c@3 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <3>; + }; + }; + + i2c-mux@72 { + compatible =3D "nxp,pca9546"; + reg =3D <0x72>; + #address-cells =3D <1>; + #size-cells =3D <0>; + i2c-mux-idle-disconnect; + vdd-supply =3D <®_3v3_stby>; + + imux20: i2c@0 { + reg =3D <0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + imux21: i2c@1 { + reg =3D <1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + gpio@20 { + compatible =3D "nxp,pca9555"; + reg =3D <0x20>; + gpio-controller; + #gpio-cells =3D <2>; + vcc-supply =3D <®_3v3_stby>; + gpio-line-names =3D + "RST_CX_0_L-O", + "RST_CX_1_L-O", + "CX0_SSD0_PRSNT_L-I", + "CX1_SSD1_PRSNT_L-I", + "CX_BOOT_CMPLT_CX0-I", + "CX_BOOT_CMPLT_CX1-I", + "CX_TWARN_CX0_L-I", + "CX_TWARN_CX1_L-I", + "CX_OVT_SHDN_CX0-I", + "CX_OVT_SHDN_CX1-I", + "FNP_L_CX0-O", + "FNP_L_CX1-O", + "", + "MCU_GPIO-I", + "MCU_RST_N-O", + "MCU_RECOVERY_N-O"; + }; + }; + + imux22: i2c@2 { + reg =3D <2>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + imux23: i2c@3 { + reg =3D <3>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + }; + + i2c-mux@73 { + compatible =3D "nxp,pca9546"; + reg =3D <0x73>; + #address-cells =3D <1>; + #size-cells =3D <0>; + i2c-mux-idle-disconnect; + vdd-supply =3D <®_3v3_stby>; + + imux24: i2c@0 { + reg =3D <0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + imux25: i2c@1 { + reg =3D <1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + i2c-mux@70 { + compatible =3D "nxp,pca9546"; + reg =3D <0x70>; + #address-cells =3D <1>; + #size-cells =3D <0>; + i2c-mux-idle-disconnect; + vdd-supply =3D <®_3v3_stby>; + + i2c25mux0: i2c@0 { + reg =3D <0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + i2c25mux1: i2c@1 { + reg =3D <1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + i2c25mux2: i2c@2 { + reg =3D <2>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + i2c25mux3: i2c@3 { + reg =3D <3>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + }; + }; + + imux26: i2c@2 { + reg =3D <2>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + imux27: i2c@3 { + reg =3D <3>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + }; + + i2c-mux@75 { + compatible =3D "nxp,pca9546"; + reg =3D <0x75>; + #address-cells =3D <1>; + #size-cells =3D <0>; + i2c-mux-idle-disconnect; + vdd-supply =3D <®_3v3_stby>; + + imux28: i2c@0 { + reg =3D <0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + imux29: i2c@1 { + reg =3D <1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + i2c-mux@74 { + compatible =3D "nxp,pca9546"; + reg =3D <0x74>; + #address-cells =3D <1>; + #size-cells =3D <0>; + i2c-mux-idle-disconnect; + vdd-supply =3D <®_3v3_stby>; + + i2c29mux0: i2c@0 { + reg =3D <0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + i2c29mux1: i2c@1 { + reg =3D <1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + i2c29mux2: i2c@2 { + reg =3D <2>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + i2c29mux3: i2c@3 { + reg =3D <3>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + }; + }; + + imux30: i2c@2 { + reg =3D <2>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + imux31: i2c@3 { + reg =3D <3>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + }; + + i2c-mux@76 { + compatible =3D "nxp,pca9546"; + reg =3D <0x76>; + #address-cells =3D <1>; + #size-cells =3D <0>; + i2c-mux-idle-disconnect; + vdd-supply =3D <®_3v3_stby>; + + imux32: i2c@0 { + reg =3D <0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + imux33: i2c@1 { + reg =3D <1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + imux34: i2c@2 { + reg =3D <2>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + imux35: i2c@3 { + reg =3D <3>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + }; + + i2c-mux@77 { + compatible =3D "nxp,pca9546"; + reg =3D <0x77>; + #address-cells =3D <1>; + #size-cells =3D <0>; + i2c-mux-idle-disconnect; + vdd-supply =3D <®_3v3_stby>; + + imux36: i2c@0 { + reg =3D <0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + imux37: i2c@1 { + reg =3D <1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + imux38: i2c@2 { + reg =3D <2>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + imux39: i2c@3 { + reg =3D <3>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + }; +}; + +// I2C7 +// Module 0/1 Leak Sensors +// Module 0/1 Fan Controllers +&i2c6 { + clock-frequency =3D <400000>; + status =3D "okay"; + + pmic@12 { + compatible =3D "ti,lm5066i"; + reg =3D <0x12>; + shunt-resistor-micro-ohms =3D <190>; + }; + + pmic@14 { + compatible =3D "ti,lm5066i"; + reg =3D <0x14>; + shunt-resistor-micro-ohms =3D <190>; + }; + + pwm@20 { + compatible =3D "maxim,max31790"; + reg =3D <0x20>; + }; + + pwm@23 { + compatible =3D "maxim,max31790"; + reg =3D <0x23>; + }; + + pwm@2c { + compatible =3D "maxim,max31790"; + reg =3D <0x2c>; + }; + + pwm@2f { + compatible =3D "maxim,max31790"; + reg =3D <0x2f>; + }; +}; + +// I2C9 +// M.2 +&i2c8 { + clock-frequency =3D <400000>; + multi-master; + status =3D "okay"; +}; + +// I2C10 +// Module 0/1 IO Expanders +&i2c9 { + clock-frequency =3D <400000>; + status =3D "okay"; + + // Module 0, Expander @0x20 + exp0: gpio@20 { + compatible =3D "nxp,pca9555"; + reg =3D <0x20>; + gpio-controller; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + interrupt-parent =3D <&gpio1>; + interrupts =3D ; + vcc-supply =3D <®_3v3_stby>; + gpio-line-names =3D + "FPGA_THERM_OVERT_L-I", + "FPGA_READY_BMC-I", + "HMC_BMC_DETECT-O", + "HMC_PGOOD-O", + "", + "BMC_STBY_CYCLE-O", + "FPGA_EROT_FATAL_ERROR_L-I", + "WP_HW_EXT_CTRL_L-O", + "EROT_FPGA_RST_L-O", + "FPGA_EROT_RECOVERY_L-O", + "BMC_EROT_FPGA_SPI_MUX_SEL-O", + "USB_HUB_RESET_L-O", + "NCSI_CS1_SEL-O", + "SGPIO_EN_L-O", + "B2B_IOEXP_INT_L-I", + "I2C_BUS_MUX_RESET_L-O"; + }; + + // UT3.0b Expander @0x22 + exp2: gpio@22 { + compatible =3D "nxp,pca9555"; + reg =3D <0x22>; + gpio-controller; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + interrupt-parent =3D <&gpio1>; + interrupts =3D ; + vcc-supply =3D <®_3v3_stby>; + gpio-line-names =3D + "BMC1_FANCTRL_FAIL_L-I", + "IOEXP_BMC_RST_12V-O", + "NODE_RST_STBY_H-O", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + ""; + }; + + // UT3.0b Expander @0x23 + exp3: gpio@23 { + compatible =3D "nxp,pca9555"; + reg =3D <0x23>; + gpio-controller; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + interrupt-parent =3D <&gpio1>; + interrupts =3D ; + vcc-supply =3D <®_3v3_stby>; + gpio-line-names =3D + "PEXSW_FL_SPI_MUX_SEL-O", + "PEX_SW_FATAL_ERROR_3V3_L-I", + "IOEXP_PDB_NODE_EN_L-O", + "NODE_PWOK_ISO-I", + "BMC_FAN_PWR_EN-O", + "BMC_ETHERNET_INT-I", + "BMC_ENET_RST-O", + "IOEXP_BMC_RST_SENSE-O", + "BMC_ID-I", + "TPM_MUX_3V3_SEL_N-O", + "IOEXP_TPM_RST_N-O", + "TPM_DOWN_SPI_INT_L-I", + "PS_BRD_PGOOD-I", + "FP_BUTTON_POWER_N-I", + "FP_BUTTON_RESET_N-I", + "FP_LED_POWER_GPIOEXP_N-O"; + }; +}; + +// I2C11 +// BMC FRU EEPROM +// BMC Temp Sensor +&i2c10 { + clock-frequency =3D <400000>; + status =3D "okay"; + + // BMC FRU EEPROM - 256 bytes + eeprom@50 { + compatible =3D "atmel,24c02"; + reg =3D <0x50>; + pagesize =3D <8>; + }; +}; + +// I2C12 +&i2c11 { + clock-frequency =3D <400000>; + status =3D "okay"; +}; + +// I2C15 +// Module 1 UPHY3 SMBus +&i2c14 { + clock-frequency =3D <100000>; + multi-master; + status =3D "okay"; + + //E1.S drive slot 0-3 + i2c-mux@77 { + compatible =3D "nxp,pca9546"; + reg =3D <0x77>; + #address-cells =3D <1>; + #size-cells =3D <0>; + i2c-mux-idle-disconnect; + vdd-supply =3D <®_3v3_stby>; + + e1si2c0: i2c@0 { + reg =3D <0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + e1si2c1: i2c@1 { + reg =3D <1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + e1si2c2: i2c@2 { + reg =3D <2>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + e1si2c3: i2c@3 { + reg =3D <3>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + }; +}; --=20 2.43.0