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If so, it will prevent correct microcode check when consulting p.ucode_rev, resulting in incorrect mitigation selection. This is a stable-only fix. Cc: Signed-off-by: Michael Zhivich Fixes: f2b75f1368af ("x86/bugs: Add a Transient Scheduler Attacks mitigatio= n") --- Changes in v3: - separate "fixes" tag for each stable arch/x86/kernel/cpu/amd.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c index 04ac18ff022f..3c7d64c454b3 100644 --- a/arch/x86/kernel/cpu/amd.c +++ b/arch/x86/kernel/cpu/amd.c @@ -592,6 +592,8 @@ static bool amd_check_tsa_microcode(void) p.model =3D c->x86_model; p.ext_model =3D c->x86_model >> 4; p.stepping =3D c->x86_stepping; + /* reserved bits are expected to be 0 in test below */ + p.__reserved =3D 0; =20 if (c->x86 =3D=3D 0x19) { switch (p.ucode_rev >> 8) { --=20 2.34.1