From nobody Mon Oct 6 08:30:17 2025 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C2F982BEFFB; Wed, 23 Jul 2025 11:08:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753268928; cv=none; b=E6hrTYJN2pEypFGeUXRLG5DQZZYIoJoNOFoHCKcNt7f+jWDm6I9/KHySV7DNDMJ7P2IUqnLgp9SpvJMxuNWXXRPrPsnEhusKwaFoqhjnjmJqi6FSEAnyUoKPHSHvKnAQhOgte5RJSV9G5n9dVKaxGSAHSUSu/Uj8yzOrdV4GKGY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753268928; c=relaxed/simple; bh=f5hFzyqfi79CYRrQfT0e+5B1D+tOqlPGzDYHQkwCOYI=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Jcb5taJpt3Y2a8bkh7OAeX3WPCkIEWmBx9J8RpiXPiTd890rhHe2F/wmvfURonrO6fKiPYjT+F0cxX82CdAwDi9ZZnSl0CI+8YXOGJxQ7VLFnggVeRwUihdpz+9cl0cJOyz8g4EjJE5dV39iO60loRxi/3Q9dC15GPJp43qzdpI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=U4wEUEYB; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="U4wEUEYB" Received: from pps.filterd (m0279871.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 56N9b1lZ011036; Wed, 23 Jul 2025 11:08:41 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= OO0ft4fq4gRriGrrw9/acPRVhY3XFlUUkjAFvDmYWEc=; b=U4wEUEYBKj2it7SP ZxLk3Sq+Ubc56KW07/rDb0TA1KxAEgXFfZGtrqIkkpS47Sxe++tjVOCBsjIuV7BH 2OE7ur6rQansI9F6Wwc0mI6/xZKcxpbNxSnHEWKBd6qTs4kSXnSzFAguZS9JoFpk 87cMIOg4MEwf3XioMQh3Zk/M9YlCogHBY6QUzNXl+GNdXyO8H1QLWx03hVQlgJyG GyRfvNenJcV/DHVP9PHTaQHzJ6asLFbqLP/naHeOLjwnl3KsYOpFXLxTn1tMtW9D XsNwE3LIoA9N9altKgzenx9X1giMVSKTjNsZUnYzqw7sYQpFffFfuIddADxbuAJ/ /Bf08A== Received: from nasanppmta04.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 482d3htxar-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 23 Jul 2025 11:08:41 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA04.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 56NB8eb4021807 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 23 Jul 2025 11:08:40 GMT Received: from hu-varada-blr.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Wed, 23 Jul 2025 04:08:35 -0700 From: Varadarajan Narayanan To: , , , , , , , , , , , , , , , , , CC: Varadarajan Narayanan Subject: [PATCH v2 1/4] dt-bindings: clock: ipq5424-apss-clk: Add ipq5424 apss clock controller Date: Wed, 23 Jul 2025 16:38:12 +0530 Message-ID: <20250723110815.2865403-2-quic_varada@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250723110815.2865403-1-quic_varada@quicinc.com> References: <20250723110815.2865403-1-quic_varada@quicinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Authority-Analysis: v=2.4 cv=G8UcE8k5 c=1 sm=1 tr=0 ts=6880c2b9 cx=c_pps a=JYp8KDb2vCoCEuGobkYCKw==:117 a=JYp8KDb2vCoCEuGobkYCKw==:17 a=GEpy-HfZoHoA:10 a=Wb1JkmetP80A:10 a=gEfo2CItAAAA:8 a=COk6AnOGAAAA:8 a=XO5-lTlbq7D_d7JOJAUA:9 a=sptkURWiP4Gy88Gu7hUp:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzIzMDA5NCBTYWx0ZWRfX1mrvDP++QWF4 qdn2melBQ+z5kIKK7W+6ZbQcgGlbTFQ9LAzLUU6SUGFTYkzJLJ+z+Tk8OMsFkOSvga8eYEF96j5 26e5TPBh/5i7UDaMBrV0ifwD9aBN5qWTr2JJdYvyWOHKcZTm8OaaWRg19eRcKK8iKA/l+tcrN26 SE4YxWyi3xhWcTNnsRp5Wbi5eVp83pJgnXEyd2iYyF19YY8CnGBJPW4mMK/9ZjVNKVSeQ3aAsCu 5aJgsosNpDG9z1fU2xoHWINLRSRsVMsUb32VbCkmaW9ClNBtjUX5PqIEHVou1rRwthWY/hH+Mnc HO7OSNawOdUdsnqRb9A3zIdtRUn4RVHNaCUO2POeT9zLPF6rhFg3b3y/jY0wqSxFYpVFU6kbkGh NNCJYBI0xLtk05Jn8Sl8GC53++3vVqfVTALs83vXf7qMOpWVU+2ehCUzQ713TEniJcUXan0J X-Proofpoint-GUID: yWRJmJ9HTUkuJlJzemt_Mi5fOzh5srNH X-Proofpoint-ORIG-GUID: yWRJmJ9HTUkuJlJzemt_Mi5fOzh5srNH X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-23_02,2025-07-22_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 mlxscore=0 suspectscore=0 priorityscore=1501 clxscore=1015 bulkscore=0 impostorscore=0 phishscore=0 spamscore=0 lowpriorityscore=0 mlxlogscore=999 adultscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507230094 Content-Type: text/plain; charset="utf-8" From: Sricharan Ramabadhran The CPU core in ipq5424 is clocked by a huayra PLL with RCG support. The RCG and PLL have a separate register space from the GCC. Also the L3 cache has a separate pll and needs to be scaled along with the CPU. Co-developed-by: Md Sadre Alam Signed-off-by: Md Sadre Alam Signed-off-by: Sricharan Ramabadhran [ Added interconnect related changes ] Signed-off-by: Varadarajan Narayanan --- v2: Add #interconnect-cells to help enable L3 pll as ICC clock Add master/slave ids --- .../bindings/clock/qcom,ipq5424-apss-clk.yaml | 61 +++++++++++++++++++ include/dt-bindings/clock/qcom,apss-ipq.h | 6 ++ .../dt-bindings/interconnect/qcom,ipq5424.h | 3 + 3 files changed, 70 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,ipq5424-ap= ss-clk.yaml diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq5424-apss-clk.= yaml b/Documentation/devicetree/bindings/clock/qcom,ipq5424-apss-clk.yaml new file mode 100644 index 000000000000..abb9eb78d271 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,ipq5424-apss-clk.yaml @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,ipq5424-apss-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm APSS IPQ5424 Clock Controller + +maintainers: + - Sricharan Ramabadhran + - Md Sadre Alam + +description: | + The CPU core in ipq5424 is clocked by a huayra PLL with RCG support. + The RCG and PLL have a separate register space from the GCC. + +properties: + compatible: + enum: + - qcom,ipq5424-apss-clk + reg: + maxItems: 1 + + clocks: + items: + - description: Reference to the XO clock. + - description: Reference to the GPLL0 clock. + + clock-names: + items: + - const: xo + - const: gpll0 + + '#clock-cells': + const: 1 + + '#interconnect-cells': + const: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + - '#interconnect-cells' + +additionalProperties: false + +examples: + - | + #include + + apss_clk: apss-clock@fa80000 { + compatible =3D "qcom,ipq5424-apss-clk"; + reg =3D <0x0fa80000 0x20000>; + clocks =3D <&xo_board>, <&gcc GPLL0>; + clock-names =3D "xo", "gpll0"; + #clock-cells =3D <1>; + #interconnect-cells =3D <1>; + }; diff --git a/include/dt-bindings/clock/qcom,apss-ipq.h b/include/dt-binding= s/clock/qcom,apss-ipq.h index 77b6e05492e2..0bb41e5efdef 100644 --- a/include/dt-bindings/clock/qcom,apss-ipq.h +++ b/include/dt-bindings/clock/qcom,apss-ipq.h @@ -8,5 +8,11 @@ =20 #define APCS_ALIAS0_CLK_SRC 0 #define APCS_ALIAS0_CORE_CLK 1 +#define APSS_PLL_EARLY 2 +#define APSS_SILVER_CLK_SRC 3 +#define APSS_SILVER_CORE_CLK 4 +#define L3_PLL 5 +#define L3_CLK_SRC 6 +#define L3_CORE_CLK 7 =20 #endif diff --git a/include/dt-bindings/interconnect/qcom,ipq5424.h b/include/dt-b= indings/interconnect/qcom,ipq5424.h index a770356112ee..afd7e0683a24 100644 --- a/include/dt-bindings/interconnect/qcom,ipq5424.h +++ b/include/dt-bindings/interconnect/qcom,ipq5424.h @@ -21,4 +21,7 @@ #define MASTER_CNOC_USB 16 #define SLAVE_CNOC_USB 17 =20 +#define MASTER_CPU 0 +#define SLAVE_L3 1 + #endif /* INTERCONNECT_QCOM_IPQ5424_H */ --=20 2.34.1 From nobody Mon Oct 6 08:30:17 2025 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5D77F2DAFDB; Wed, 23 Jul 2025 11:08:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753268933; cv=none; b=nxbL8cJVXxT+XvL1OHSzuperBkWyXuQlNzd5HCNC6/H8R2dwUPauatln79j2AZZrQj9pNk/qYhSD3Ojwi805QxW0KEo8hqbMaoglZKhGbxP8tdSlXZMLH45yRuXhBqt3tHFV0euUH3DnpyQPhJzcu8dSKJiZ0sYVUq8IprqLDz0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753268933; c=relaxed/simple; bh=jmCrwunjX7t7Lzj12+o466JQt3nHRCdfFDWDqIF8FOc=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=utDPhnjU9MUlnfSj6MPD566EuTkRtWm26n7b4YWjH6wNNhpaR8mIQP8sR0smGQeCo33FESD6LzMXKljAkqlkxvKnPYYR5WC8+kfQZoOjjz6VqBaXv7CghP0vWSlabdZeg+jYNfuA6AIZTC5ve5rqTmv2BbB1w+e/bz+/A4Y7ZEs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=DGmHFHgU; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="DGmHFHgU" Received: from pps.filterd (m0279867.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 56N9LhM0001765; Wed, 23 Jul 2025 11:08:46 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= FXp9B64qx703kMPw3hJqjg9QtQaDfRttDfJjSdHMU04=; b=DGmHFHgUqaZkA+T9 iCHaj1KBqI5OCUe2A8+335Bg5TrjaVCgBvrjdId2N3zI6FUJsDL5J3L/8QKJsNwU HQycwozzEg/4ZtvQ1ZyQRmNxN1E1HllFXEeZYrPnzmsL+0924h822M8XXVTsM6LD bM/roEzp0sERAp9hlkUvELDIlE0D6EQVLCONsEUnRMalNutcFAPD0ubsTJf7Xa6W ioOgLUEGEBai4d5wnOCwVuqVb8Wn6s7224cZtqLJa11na1tZmwmEf6lmm014W+Hd VcKAzZCZQL4JVnHiI6opDvHi0/San9BgYQk4XQwhpFXecbDNMJljeY81XqRlAEhE J/WJ4w== Received: from nasanppmta03.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 481t6w625m-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 23 Jul 2025 11:08:46 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA03.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 56NB8j2X030760 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 23 Jul 2025 11:08:45 GMT Received: from hu-varada-blr.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Wed, 23 Jul 2025 04:08:40 -0700 From: Varadarajan Narayanan To: , , , , , , , , , , , , , , , , , CC: Varadarajan Narayanan Subject: [PATCH v2 2/4] clk: qcom: apss-ipq5424: Add ipq5424 apss clock controller Date: Wed, 23 Jul 2025 16:38:13 +0530 Message-ID: <20250723110815.2865403-3-quic_varada@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250723110815.2865403-1-quic_varada@quicinc.com> References: <20250723110815.2865403-1-quic_varada@quicinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Authority-Analysis: v=2.4 cv=SPpCVPvH c=1 sm=1 tr=0 ts=6880c2be cx=c_pps a=JYp8KDb2vCoCEuGobkYCKw==:117 a=JYp8KDb2vCoCEuGobkYCKw==:17 a=GEpy-HfZoHoA:10 a=Wb1JkmetP80A:10 a=COk6AnOGAAAA:8 a=4qVBXBCilfBDfP_PjJQA:9 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzIzMDA5NCBTYWx0ZWRfXx1zFyXrEnvx7 BtSOL7pHAW2UjdSh8wLE1AMbLiY1fiaS0cOCo54aqUsaREcL78T+/dPFzujosxuHZ8iKHBQEs4p lylFFcsok0jlP+yKozWP97f7lNMVe3SbPS2odmRcNeDvc+vUEcr2S0NZxm6hHwrWyS7qDhwuvdL gaqqCv0/V2ufz7PkG8QvdAFh1n8FwUiE9HyapduuUvDE1rNiCMsrYo2jRoVOkCDGkBe8jIIBvy2 h2dRTTdl0JhFlE1aKARIwSU8eR3b2D3Zwd1iX4a/mCYOzLpYdUNhLn+AvsaMNdEn5VY3uMk/Z1Z V/ToWzn+uoaq+oU51HF0xj/IRILGiUABhrYMSQEvNlkBsj3nvXaoIewudwGUqeOWsIYfjRxmcgT 5230QMgAeveLhVx8IVPs0/TD8YueoNPF/zTYrfFk5GqW+XBdY4rsyjUSPmGRJvS1xkTZ47UH X-Proofpoint-ORIG-GUID: Ncrq2byLJcA5OXjSE4CL3e3Z2XqhI0dU X-Proofpoint-GUID: Ncrq2byLJcA5OXjSE4CL3e3Z2XqhI0dU X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-23_02,2025-07-22_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=0 adultscore=0 phishscore=0 malwarescore=0 mlxscore=0 bulkscore=0 clxscore=1011 priorityscore=1501 impostorscore=0 lowpriorityscore=0 mlxlogscore=999 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507230094 Content-Type: text/plain; charset="utf-8" From: Sricharan Ramabadhran CPU on Qualcomm ipq5424 is clocked by huayra PLL with RCG support. Add support for the APSS PLL, RCG and clock enable for ipq5424. The PLL, RCG register space are clubbed. Hence adding new APSS driver for both PLL and RCG/CBC control. Also the L3 cache has a separate pll and needs to be scaled along with the CPU and is modeled as an ICC clock. Co-developed-by: Md Sadre Alam Signed-off-by: Md Sadre Alam Signed-off-by: Sricharan Ramabadhran [ Removed clock notifier, moved L3 pll to icc-clk, used existing alpha pll structure ] Signed-off-by: Varadarajan Narayanan --- v2: Model L3 pll as ICC clock and add relevant structures Use CLK_ALPHA_PLL_TYPE_HUAYRA_2290 register offsets instead of duplicate ipq5424_pll_offsets definition. Inline clock rates. Fix MODULE_LICENSE --- drivers/clk/qcom/Kconfig | 7 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/apss-ipq5424.c | 282 ++++++++++++++++++++++++++++++++ 3 files changed, 290 insertions(+) create mode 100644 drivers/clk/qcom/apss-ipq5424.c diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 6cb6cd3e1778..dae89599a40e 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -208,6 +208,13 @@ config IPQ_CMN_PLL Say Y or M if you want to support CMN PLL clock on the IPQ based devices. =20 +config IPQ_APSS_5424 + tristate "IPQ APSS Clock Controller" + help + Support for APSS Clock controller on Qualcom IPQ5424 platform. + Say Y if you want to support CPU frequency scaling on ipq based + devices. + config IPQ_GCC_4019 tristate "IPQ4019 Global Clock Controller" help diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index ddb7e06fae40..98de55eb6402 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -29,6 +29,7 @@ obj-$(CONFIG_CLK_X1E80100_TCSRCC) +=3D tcsrcc-x1e80100.o obj-$(CONFIG_CLK_X1P42100_GPUCC) +=3D gpucc-x1p42100.o obj-$(CONFIG_CLK_QCM2290_GPUCC) +=3D gpucc-qcm2290.o obj-$(CONFIG_IPQ_APSS_PLL) +=3D apss-ipq-pll.o +obj-$(CONFIG_IPQ_APSS_5424) +=3D apss-ipq5424.o obj-$(CONFIG_IPQ_APSS_6018) +=3D apss-ipq6018.o obj-$(CONFIG_IPQ_CMN_PLL) +=3D ipq-cmn-pll.o obj-$(CONFIG_IPQ_GCC_4019) +=3D gcc-ipq4019.o diff --git a/drivers/clk/qcom/apss-ipq5424.c b/drivers/clk/qcom/apss-ipq542= 4.c new file mode 100644 index 000000000000..7ce1e169b9a1 --- /dev/null +++ b/drivers/clk/qcom/apss-ipq5424.c @@ -0,0 +1,282 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2025, Qualcomm Innovation Center, Inc. All rights reserve= d. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "common.h" + +enum { + P_XO, + P_GPLL0, + P_APSS_PLL_EARLY, + P_L3_PLL, +}; + +struct apss_clk { + struct notifier_block cpu_clk_notifier; + struct clk_hw *hw; + struct device *dev; + struct clk *l3_clk; +}; + +static struct clk_alpha_pll ipq5424_apss_pll =3D { + .offset =3D 0x0, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_HUAYRA_2290], + .flags =3D SUPPORTS_DYNAMIC_UPDATE, + .clkr =3D { + .enable_reg =3D 0x0, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "apss_pll", + .parent_data =3D &(const struct clk_parent_data) { + .fw_name =3D "xo-board-clk", + }, + .parent_names =3D (const char *[]){ "xo-board-clk"}, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_huayra_ops, + }, + }, +}; + +static const struct clk_parent_data parents_apss_silver_clk_src[] =3D { + { .fw_name =3D "xo-board-clk" }, + { .fw_name =3D "gpll0" }, + { .hw =3D &ipq5424_apss_pll.clkr.hw }, +}; + +static const struct parent_map parents_apss_silver_clk_src_map[] =3D { + { P_XO, 0 }, + { P_GPLL0, 4 }, + { P_APSS_PLL_EARLY, 5 }, +}; + +static const struct freq_tbl ftbl_apss_clk_src[] =3D { + F(800000000, P_GPLL0, 1, 0, 0), + F(1416000000, P_APSS_PLL_EARLY, 1, 0, 0), + F(1800000000, P_APSS_PLL_EARLY, 1, 0, 0), + { } +}; + +static struct clk_rcg2 apss_silver_clk_src =3D { + .cmd_rcgr =3D 0x0080, + .freq_tbl =3D ftbl_apss_clk_src, + .hid_width =3D 5, + .parent_map =3D parents_apss_silver_clk_src_map, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "apss_silver_clk_src", + .parent_data =3D parents_apss_silver_clk_src, + .num_parents =3D ARRAY_SIZE(parents_apss_silver_clk_src), + .ops =3D &clk_rcg2_ops, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_branch apss_silver_core_clk =3D { + .halt_reg =3D 0x008c, + .clkr =3D { + .enable_reg =3D 0x008c, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "apss_silver_core_clk", + .parent_hws =3D (const struct clk_hw *[]){ + &apss_silver_clk_src.clkr.hw }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_alpha_pll ipq5424_l3_pll =3D { + .offset =3D 0x10000, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_HUAYRA_2290], + .flags =3D SUPPORTS_DYNAMIC_UPDATE, + .clkr =3D { + .enable_reg =3D 0x0, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "l3_pll", + .parent_data =3D &(const struct clk_parent_data) { + .fw_name =3D "xo-board-clk", + }, + .parent_names =3D (const char *[]){ "xo-board-clk"}, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_huayra_ops, + }, + }, +}; + +static const struct clk_parent_data parents_l3_clk_src[] =3D { + { .fw_name =3D "xo-board-clk" }, + { .fw_name =3D "gpll0" }, + { .hw =3D &ipq5424_l3_pll.clkr.hw }, +}; + +static const struct parent_map parents_l3_clk_src_map[] =3D { + { P_XO, 0 }, + { P_GPLL0, 4 }, + { P_L3_PLL, 5 }, +}; + +static const struct freq_tbl ftbl_l3_clk_src[] =3D { + F(800000000, P_GPLL0, 1, 0, 0), + F(984000000, P_L3_PLL, 1, 0, 0), + F(1272000000, P_L3_PLL, 1, 0, 0), + { } +}; + +static struct clk_rcg2 l3_clk_src =3D { + .cmd_rcgr =3D 0x10080, + .freq_tbl =3D ftbl_l3_clk_src, + .hid_width =3D 5, + .parent_map =3D parents_l3_clk_src_map, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "l3_clk_src", + .parent_data =3D parents_l3_clk_src, + .num_parents =3D ARRAY_SIZE(parents_l3_clk_src), + .ops =3D &clk_rcg2_ops, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_branch l3_core_clk =3D { + .halt_reg =3D 0x1008c, + .clkr =3D { + .enable_reg =3D 0x1008c, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "l3_clk", + .parent_hws =3D (const struct clk_hw *[]){ + &l3_clk_src.clkr.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static const struct regmap_config apss_ipq5424_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x20000, + .fast_io =3D true, +}; + +static struct clk_regmap *apss_ipq5424_clks[] =3D { + [APSS_PLL_EARLY] =3D &ipq5424_apss_pll.clkr, + [APSS_SILVER_CLK_SRC] =3D &apss_silver_clk_src.clkr, + [APSS_SILVER_CORE_CLK] =3D &apss_silver_core_clk.clkr, + [L3_PLL] =3D &ipq5424_l3_pll.clkr, + [L3_CLK_SRC] =3D &l3_clk_src.clkr, + [L3_CORE_CLK] =3D &l3_core_clk.clkr, + +}; + +#define IPQ_APPS_PLL_ID (5424 * 3) /* some unique value */ + +static const struct qcom_icc_hws_data icc_ipq5424_cpu_l3[] =3D { + { MASTER_CPU, SLAVE_L3, L3_CORE_CLK }, +}; + +static const struct qcom_cc_desc apss_ipq5424_desc =3D { + .config =3D &apss_ipq5424_regmap_config, + .clks =3D apss_ipq5424_clks, + .num_clks =3D ARRAY_SIZE(apss_ipq5424_clks), + .icc_hws =3D icc_ipq5424_cpu_l3, + .num_icc_hws =3D ARRAY_SIZE(icc_ipq5424_cpu_l3), + .icc_first_node_id =3D IPQ_APPS_PLL_ID, +}; + +static const struct alpha_pll_config apss_pll_config =3D { + .l =3D 0x3b, + .config_ctl_val =3D 0x08200920, + .config_ctl_hi_val =3D 0x05008001, + .config_ctl_hi1_val =3D 0x04000000, + .test_ctl_val =3D 0x0, + .test_ctl_hi_val =3D 0x0, + .test_ctl_hi1_val =3D 0x0, + .user_ctl_val =3D 0x1, + .early_output_mask =3D BIT(3), + .aux2_output_mask =3D BIT(2), + .aux_output_mask =3D BIT(1), + .main_output_mask =3D BIT(0), +}; + +static const struct alpha_pll_config l3_pll_config =3D { + .l =3D 0x29, + .config_ctl_val =3D 0x08200920, + .config_ctl_hi_val =3D 0x05008001, + .config_ctl_hi1_val =3D 0x04000000, + .test_ctl_val =3D 0x0, + .test_ctl_hi_val =3D 0x0, + .test_ctl_hi1_val =3D 0x0, + .user_ctl_val =3D 0x1, + .early_output_mask =3D BIT(3), + .aux2_output_mask =3D BIT(2), + .aux_output_mask =3D BIT(1), + .main_output_mask =3D BIT(0), +}; + +static int apss_ipq5424_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct regmap *regmap; + void __iomem *base; + int ret; + + base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) + return PTR_ERR(base); + + regmap =3D devm_regmap_init_mmio(dev, base, &apss_ipq5424_regmap_config); + if (!regmap) + return PTR_ERR(regmap); + + clk_alpha_pll_configure(&ipq5424_l3_pll, regmap, &l3_pll_config); + + clk_alpha_pll_configure(&ipq5424_apss_pll, regmap, &apss_pll_config); + + ret =3D qcom_cc_really_probe(dev, &apss_ipq5424_desc, regmap); + if (!ret) + dev_dbg(&pdev->dev, "Registered APSS & L3 clock provider\n"); + + return ret; +} + +static const struct of_device_id apss_ipq5424_match_table[] =3D { + { .compatible =3D "qcom,ipq5424-apss-clk" }, + { } +}; +MODULE_DEVICE_TABLE(of, apss_ipq5424_match_table); + +static struct platform_driver apss_ipq5424_driver =3D { + .probe =3D apss_ipq5424_probe, + .driver =3D { + .name =3D "apss-ipq5424-clk", + .of_match_table =3D apss_ipq5424_match_table, + }, +}; + +module_platform_driver(apss_ipq5424_driver); + +MODULE_DESCRIPTION("QCOM APSS IPQ5424 CLK Driver"); +MODULE_LICENSE("GPL"); --=20 2.34.1 From nobody Mon Oct 6 08:30:17 2025 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AE1DF2DE71E; Wed, 23 Jul 2025 11:08:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753268937; cv=none; b=dHpSc7KlyqUU9LWPONV70ZcmpVt52X9iGrkw/ZVcDZb6NOHF3bZTvtAE1oGDbSwJ+seFe1YC4n55b+Z05YMf2foTpATGN+qzDAPXOCTDOcY+ZtZ3Ru7tl98ZKQNppTpzRNf8leRb5VUEpy0hcTBgKCqaUTnTbDStGZudNavif7A= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753268937; c=relaxed/simple; bh=b2z02Tg7+vcOZeTgZw3lRIJ677lSvmqCMf5C7B6Yr0A=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=DfUJiWU/60T+iBlzmwrdjSONAOOZxHNFccyMoyiXMYVXNOQnR7gOzOE9Xsbmxp3zj/QfYQwpn9uBxT1iM7vNuXuk0Fwb8fsp0MeO8HGXcyhicXe93XfipXgPn208MIwGRxuqSIfLDJkbtf9fyl3DZuURoVaF74s4UHjnIgmu4KA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=TY5fxCbd; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="TY5fxCbd" Received: from pps.filterd (m0279865.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 56N90Nbm030756; Wed, 23 Jul 2025 11:08:52 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= xF3PiaRiaIJjwDIgFh/oPpSH+ITV10Dk4Nei06/sbNo=; b=TY5fxCbd2hP7gbyp uyJs8tgmq/44bZ+6aq895A2osrfV7ooUmt6JH1bqmoqtx+0bfA5Wh0Q3tSVc96xo T/mdOx436Z42AAoa+LQeW6qHhxiJ0TcVsez0EX95iVVA05g8XJ8YaZW1vEKd6m5m Kc1BSogFnzERWHUsNrHDz3yauHJdZYLqvVQ8pEu2c8LVzMWnFGYKhRpRFSgGCEI/ EN2+p5lZpCqcrrPf+nBVPn8HOAKNoXchZd3nLlsRPXvZo+83dJMbP2t29LW80m/5 yKpOdxVgJvwGvy7ug1Q3g/iYp49OGSFVxheJrzPkWvNbWCYyrpXUy9L1guBcBKwy 2lxrSQ== Received: from nasanppmta03.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 48045w39qv-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 23 Jul 2025 11:08:51 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA03.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 56NB8pDg030833 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 23 Jul 2025 11:08:51 GMT Received: from hu-varada-blr.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Wed, 23 Jul 2025 04:08:45 -0700 From: Varadarajan Narayanan To: , , , , , , , , , , , , , , , , , CC: Konrad Dybcio , Varadarajan Narayanan Subject: [PATCH v2 3/4] cpufreq: qcom-nvmem: Enable cpufreq for ipq5424 Date: Wed, 23 Jul 2025 16:38:14 +0530 Message-ID: <20250723110815.2865403-4-quic_varada@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250723110815.2865403-1-quic_varada@quicinc.com> References: <20250723110815.2865403-1-quic_varada@quicinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Authority-Analysis: v=2.4 cv=LL1mQIW9 c=1 sm=1 tr=0 ts=6880c2c3 cx=c_pps a=JYp8KDb2vCoCEuGobkYCKw==:117 a=JYp8KDb2vCoCEuGobkYCKw==:17 a=GEpy-HfZoHoA:10 a=Wb1JkmetP80A:10 a=COk6AnOGAAAA:8 a=EUspDBNiAAAA:8 a=XqKM0RL5GMr1h_B9R8QA:9 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-GUID: jJ54FnbuT4TfRJc7KPbJhTRvd-ZXjIJZ X-Proofpoint-ORIG-GUID: jJ54FnbuT4TfRJc7KPbJhTRvd-ZXjIJZ X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzIzMDA5NCBTYWx0ZWRfXyXqICZlR9hIH nnklFTQSLwJ6qnvmJoEQCkliTYy6qJ8DvNZLVTt7kblhJaM7p7M+ZGyCMENQRvwu8iMq9tBI732 24p6cupzdQw4dI0vD/eXUw7ibnXWBMkanOTfK/F6FV5VWN27LdG4I4Xr1IZ6xHue7ke7yjjIjDe 8FkikoutTKQFm67cO/sIzH8orU4+/K8sXrLGj5tTLxwEyKR4NlBZgEsh/gwvniJpgsRxLKoRTaD WX61+nY6WfRl1JQa4hH7hDhTjvAGiX/aRuCZGqGCnHN0HgGjjeCQ9BJzsqITrO4Eu7I1NmetIGk nRe3QIFziEC67qmJY3F4pqsTviIBWgOTA3A7g0v03MEyLItW3cGkWlMRNdiTIra9rKWO16bRgfu OfgPCVJoycRMHiX534Yu8etm6TouGLDiHwNzzJ0y5NRYbe5CnozCVPd32hRJ4YRWVhBfbfjH X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-23_02,2025-07-22_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 mlxlogscore=999 clxscore=1011 mlxscore=0 adultscore=0 suspectscore=0 spamscore=0 malwarescore=0 impostorscore=0 bulkscore=0 lowpriorityscore=0 phishscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507230094 Content-Type: text/plain; charset="utf-8" From: Md Sadre Alam IPQ5424 have different OPPs available for the CPU based on SoC variant. This can be determined through use of an eFuse register present in the silicon. Added support for ipq5424 on nvmem driver which helps to determine OPPs at runtime based on the eFuse register which has the CPU frequency limits. opp-supported-hw dt binding can be used to indicate the available OPPs for each limit. nvmem driver also creates the "cpufreq-dt" platform_device after passing the version matching data to the OPP framework so that the cpufreq-dt handles the actual cpufreq implementation. Signed-off-by: Md Sadre Alam Signed-off-by: Sricharan Ramabadhran Reviewed-by: Konrad Dybcio [ Changed '!=3D' based check to '=3D=3D' based check ] Signed-off-by: Varadarajan Narayanan --- v2: Add Reviewed-by: Konrad Change speed bin check to =3D=3D instead of !=3D -- drivers/cpufreq/cpufreq-dt-platdev.c | 1 + drivers/cpufreq/qcom-cpufreq-nvmem.c | 5 +++++ 2 files changed, 6 insertions(+) diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c b/drivers/cpufreq/cpufreq= -dt-platdev.c index 015dd393eaba..de1769649368 100644 --- a/drivers/cpufreq/cpufreq-dt-platdev.c +++ b/drivers/cpufreq/cpufreq-dt-platdev.c @@ -191,6 +191,7 @@ static const struct of_device_id blocklist[] __initcons= t =3D { { .compatible =3D "ti,am62p5", }, =20 { .compatible =3D "qcom,ipq5332", }, + { .compatible =3D "qcom,ipq5424", }, { .compatible =3D "qcom,ipq6018", }, { .compatible =3D "qcom,ipq8064", }, { .compatible =3D "qcom,ipq8074", }, diff --git a/drivers/cpufreq/qcom-cpufreq-nvmem.c b/drivers/cpufreq/qcom-cp= ufreq-nvmem.c index 54f8117103c8..765a5bb81829 100644 --- a/drivers/cpufreq/qcom-cpufreq-nvmem.c +++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c @@ -200,6 +200,10 @@ static int qcom_cpufreq_kryo_name_version(struct devic= e *cpu_dev, case QCOM_ID_IPQ9574: drv->versions =3D 1 << (unsigned int)(*speedbin); break; + case QCOM_ID_IPQ5424: + case QCOM_ID_IPQ5404: + drv->versions =3D (*speedbin =3D=3D 0x3b) ? BIT(1) : BIT(0); + break; case QCOM_ID_MSM8996SG: case QCOM_ID_APQ8096SG: drv->versions =3D 1 << ((unsigned int)(*speedbin) + 4); @@ -591,6 +595,7 @@ static const struct of_device_id qcom_cpufreq_match_lis= t[] __initconst __maybe_u { .compatible =3D "qcom,msm8996", .data =3D &match_data_kryo }, { .compatible =3D "qcom,qcs404", .data =3D &match_data_qcs404 }, { .compatible =3D "qcom,ipq5332", .data =3D &match_data_kryo }, + { .compatible =3D "qcom,ipq5424", .data =3D &match_data_kryo }, { .compatible =3D "qcom,ipq6018", .data =3D &match_data_ipq6018 }, { .compatible =3D "qcom,ipq8064", .data =3D &match_data_ipq8064 }, { .compatible =3D "qcom,ipq8074", .data =3D &match_data_ipq8074 }, --=20 2.34.1 From nobody Mon Oct 6 08:30:17 2025 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DA3502E49A7; Wed, 23 Jul 2025 11:09:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753268942; cv=none; b=fLJ1aIQlIO1QmhtYi6Wc27fdSW6zd+UQPcTiXLPqhGoZryVLDOwv7zmx4oHqGYQ5JhRN6WzYHncvOm9Atz7P2yMxu8TDEzOTTpOEEGEJsledPxUWxqTZuJLtH8S7sd21oVrJermAfRMB+05X38O3Wv4drai5B32z0tZFb3rf2x8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753268942; c=relaxed/simple; bh=QAF/CJx4l1OMxiZsPySVBwt4eqsS9ZvfqlfvkWA/Efo=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=fIzpbQNLQLgcTtkS5zVxzkOyS4VOWxisPHnwxrtn0/RYTD+wNXLGPykJor70gE9OUyzdNez7QltAeLQ1c86Su/j2UoFvpaFM166QaRrOTBz/b9iOFZipeeVHizTNDMeKhAYqtqLksDYOLyV+hIeGP1RllfWcgojquLjYQbA0Bwc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=psZ5r3Hh; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="psZ5r3Hh" Received: from pps.filterd (m0279866.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 56N8tcfq010356; Wed, 23 Jul 2025 11:08:57 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= CBcD5FkL7MwbIlsoWgdrxc9IH2TcznubU5xhsWpCVGE=; b=psZ5r3Hhgzl/0/Ao 91An7FQBkkSyTLQ71UwGUK2P3YUZdYDNFY1iLuInV3IuQ7jcjwJ1AP7fslIVe9ZS PkkJiysJ1eFNYOjeXZ6crcQxNQsJt255xLWifKsvJYeWmCzVS7vdoAakdlTiawTC 6jopc9fJDHQzPflKdJINbEFUew3cTux2rarthioR0tR8vZ/5iI9bfxdVxmzLstYE Z4PaC9MOx4GNFYF4hP7PDUiuiUM/Zl6JM0gUyAG5NelTuL7H4qxjdx6TszyojXQH 8P6m4PaSDWNDXwlF2jKEovY1n0xMen8ojL9Hk77OvZ3ghzIsMY5dRUKt2gTFz8bb ptjpaQ== Received: from nasanppmta04.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4804na3am1-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 23 Jul 2025 11:08:56 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA04.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 56NB8uXo021961 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 23 Jul 2025 11:08:56 GMT Received: from hu-varada-blr.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Wed, 23 Jul 2025 04:08:51 -0700 From: Varadarajan Narayanan To: , , , , , , , , , , , , , , , , , CC: Varadarajan Narayanan Subject: [PATCH v2 4/4] arm64: dts: qcom: ipq5424: Enable cpufreq Date: Wed, 23 Jul 2025 16:38:15 +0530 Message-ID: <20250723110815.2865403-5-quic_varada@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250723110815.2865403-1-quic_varada@quicinc.com> References: <20250723110815.2865403-1-quic_varada@quicinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: vsrAuajVI1lLol1T6k2yzRBddViogAGB X-Proofpoint-ORIG-GUID: vsrAuajVI1lLol1T6k2yzRBddViogAGB X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzIzMDA5NCBTYWx0ZWRfX2tMzF1EfVidy 49cpWWhxpqH+VLZ6Ie+QwgxdqH7Fph/TZ7u6T0iIXPDtrZwOVu7YVq/bbMbGJ2uwvbCWMxwWTeS B49uzIYZI5IHzEU5jxcIhVCWupDp6HCN0NJQ8tdHbgYo16To8mn0FccVm70UzarG5IdYRooGsL9 uDUzWhqcMNMeYEwI1OsQx1oZ7P5EVdkG8FCLmIWdSjucSpslt9xA+Wbj22dPJqolZad/+NswfNk ABRCvsHJdnWEyKYix7aTYyjNn1cKHKKi7TVgZ/tMOlOL/DiDAT6UMyJJ9jzWkGUi9lGKEe6uiNl pKcTl7EXKKFpaWu59oKNbqToJ5yuEQhKCQH4haeSUnOEWEgLcnygqCffEWIGiDjATJ6+Q2VaVyn GG5F0JMoqx1Enlrz43g9EkFHLty++yFd9eNUNfg979xO04eVq6EttFOMV4ziFNjEu6Npzu/j X-Authority-Analysis: v=2.4 cv=DoFW+H/+ c=1 sm=1 tr=0 ts=6880c2c8 cx=c_pps a=JYp8KDb2vCoCEuGobkYCKw==:117 a=JYp8KDb2vCoCEuGobkYCKw==:17 a=GEpy-HfZoHoA:10 a=Wb1JkmetP80A:10 a=COk6AnOGAAAA:8 a=6wL3klP_paFbw1eNuawA:9 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-23_02,2025-07-22_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 phishscore=0 clxscore=1011 mlxscore=0 mlxlogscore=886 bulkscore=0 impostorscore=0 malwarescore=0 lowpriorityscore=0 adultscore=0 spamscore=0 priorityscore=1501 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507230094 Content-Type: text/plain; charset="utf-8" From: Sricharan Ramabadhran Add the qfprom, cpu clocks, A53 PLL and cpu-opp-table required for CPU clock scaling. Signed-off-by: Sricharan Ramabadhran [ Added interconnect related entries, fix dt-bindings errors ] Signed-off-by: Varadarajan Narayanan --- v2: Add 'interconnects' to cpu nodes Add 'opp-peak-kBps' to opp table Add '#interconnect-cells' to apss_clk Remove unnecessary comment Fix dt-binding-errors in qfprom node --- arch/arm64/boot/dts/qcom/ipq5424.dtsi | 65 +++++++++++++++++++++++++++ 1 file changed, 65 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq5424.dtsi b/arch/arm64/boot/dts/qc= om/ipq5424.dtsi index 2eea8a078595..39d394f49789 100644 --- a/arch/arm64/boot/dts/qcom/ipq5424.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5424.dtsi @@ -7,6 +7,7 @@ */ =20 #include +#include #include #include #include @@ -52,6 +53,12 @@ cpu0: cpu@0 { reg =3D <0x0>; enable-method =3D "psci"; next-level-cache =3D <&l2_0>; + clocks =3D <&apss_clk APSS_SILVER_CORE_CLK>, + <&apss_clk L3_CORE_CLK>; + clock-names =3D "cpu", "l3_core"; + operating-points-v2 =3D <&cpu_opp_table>; + interconnects =3D <&apss_clk MASTER_CPU &apss_clk SLAVE_L3>; + l2_0: l2-cache { compatible =3D "cache"; cache-level =3D <2>; @@ -72,6 +79,11 @@ cpu1: cpu@100 { enable-method =3D "psci"; reg =3D <0x100>; next-level-cache =3D <&l2_100>; + clocks =3D <&apss_clk APSS_SILVER_CORE_CLK>, + <&apss_clk L3_CORE_CLK>; + clock-names =3D "cpu", "l3_core"; + operating-points-v2 =3D <&cpu_opp_table>; + interconnects =3D <&apss_clk MASTER_CPU &apss_clk SLAVE_L3>; =20 l2_100: l2-cache { compatible =3D "cache"; @@ -87,6 +99,11 @@ cpu2: cpu@200 { enable-method =3D "psci"; reg =3D <0x200>; next-level-cache =3D <&l2_200>; + clocks =3D <&apss_clk APSS_SILVER_CORE_CLK>, + <&apss_clk L3_CORE_CLK>; + clock-names =3D "cpu", "l3_core"; + operating-points-v2 =3D <&cpu_opp_table>; + interconnects =3D <&apss_clk MASTER_CPU &apss_clk SLAVE_L3>; =20 l2_200: l2-cache { compatible =3D "cache"; @@ -102,6 +119,11 @@ cpu3: cpu@300 { enable-method =3D "psci"; reg =3D <0x300>; next-level-cache =3D <&l2_300>; + clocks =3D <&apss_clk APSS_SILVER_CORE_CLK>, + <&apss_clk L3_CORE_CLK>; + clock-names =3D "cpu", "l3_core"; + operating-points-v2 =3D <&cpu_opp_table>; + interconnects =3D <&apss_clk MASTER_CPU &apss_clk SLAVE_L3>; =20 l2_300: l2-cache { compatible =3D "cache"; @@ -119,6 +141,28 @@ scm { }; }; =20 + cpu_opp_table: opp-table-cpu { + compatible =3D "operating-points-v2-kryo-cpu"; + opp-shared; + nvmem-cells =3D <&cpu_speed_bin>; + + opp-1416000000 { + opp-hz =3D /bits/ 64 <1416000000>; + opp-microvolt =3D <1>; + opp-supported-hw =3D <0x3>; + clock-latency-ns =3D <200000>; + opp-peak-kBps =3D <984000>; + }; + + opp-1800000000 { + opp-hz =3D /bits/ 64 <1800000000>; + opp-microvolt =3D <2>; + opp-supported-hw =3D <0x1>; + clock-latency-ns =3D <200000>; + opp-peak-kBps =3D <1272000>; + }; + }; + memory@80000000 { device_type =3D "memory"; /* We expect the bootloader to fill in the size */ @@ -388,6 +432,18 @@ system-cache-controller@800000 { interrupts =3D ; }; =20 + qfprom@a6000 { + compatible =3D "qcom,ipq5424-qfprom", "qcom,qfprom"; + reg =3D <0x0 0x000a6000 0x0 0x1000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + + cpu_speed_bin: cpu-speed-bin@234 { + reg =3D <0x234 0x1>; + bits =3D <0 8>; + }; + }; + tlmm: pinctrl@1000000 { compatible =3D "qcom,ipq5424-tlmm"; reg =3D <0 0x01000000 0 0x300000>; @@ -730,6 +786,15 @@ frame@f42d000 { }; }; =20 + apss_clk: apss-clock@fa80000 { + compatible =3D "qcom,ipq5424-apss-clk"; + reg =3D <0x0 0x0fa80000 0x0 0x20000>; + clocks =3D <&xo_board>, <&gcc GPLL0>; + clock-names =3D "xo", "gpll0"; + #clock-cells =3D <1>; + #interconnect-cells =3D <1>; + }; + pcie3: pcie@40000000 { compatible =3D "qcom,pcie-ipq5424", "qcom,pcie-ipq9574"; reg =3D <0x0 0x40000000 0x0 0xf1c>, --=20 2.34.1