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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Marek Vasut , , , , , Tristram Ha , Krzysztof Kozlowski Subject: [PATCH net-next v5 1/6] dt-bindings: net: dsa: microchip: Add KSZ8463 switch support Date: Tue, 22 Jul 2025 19:26:07 -0700 Message-ID: <20250723022612.38535-2-Tristram.Ha@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250723022612.38535-1-Tristram.Ha@microchip.com> References: <20250723022612.38535-1-Tristram.Ha@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Tristram Ha KSZ8463 switch is a 3-port switch based from KSZ8863. Its register access is significantly different from the other KSZ SPI switches. Signed-off-by: Tristram Ha Acked-by: Krzysztof Kozlowski Reviewed-by: Andrew Lunn --- Documentation/devicetree/bindings/net/dsa/microchip,ksz.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/net/dsa/microchip,ksz.yaml b= /Documentation/devicetree/bindings/net/dsa/microchip,ksz.yaml index 62ca63e8a26f..eb4607460db7 100644 --- a/Documentation/devicetree/bindings/net/dsa/microchip,ksz.yaml +++ b/Documentation/devicetree/bindings/net/dsa/microchip,ksz.yaml @@ -18,6 +18,7 @@ properties: # required and optional properties. compatible: enum: + - microchip,ksz8463 - microchip,ksz8765 - microchip,ksz8794 - microchip,ksz8795 --=20 2.34.1 From nobody Mon Oct 6 08:24:27 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ACE271DE4F1; Wed, 23 Jul 2025 02:26:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753237607; cv=none; b=Nc7Jp1LhlwQHCuJ7EUAdMdsgt1PoaILM+ElMLONnDdehYxby+ziBgJmX8q13Xq0+CHCMl0UIXb34gnTwtQFJqncI41KxijhAFu2bV/ZCiRuekxr7N8ZmM1sM/dpP1dgRKMiPqjv2PmyVd0fghaRYHe61yYHvbunFSAe2KCEqmEo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753237607; c=relaxed/simple; bh=NTYAQ+3UBj3hccObqN9SlZVsC+hLF/GqYCegjXWG0x4=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=YUzEjmvkxfl1OY25YKDm9/z3MqjYZX8jMZ7gON3/53D2yS1oC0DajLUkWBSAd8kk+pET0hyrJ453Vx/wYkvtjIh001mQ7g+igNJwFyJkcy3eSC0qOXvitxoiYFVm6sk86SlZN+fL0B1UeyCWzv3gOt2xLH7vh1P9k2lu5Z1wiFM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=rCToCD6m; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="rCToCD6m" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1753237606; x=1784773606; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=NTYAQ+3UBj3hccObqN9SlZVsC+hLF/GqYCegjXWG0x4=; b=rCToCD6mO/AqNW5alZIcHkdDSGhmHUMLZPJ/2A/M9/r2lCN/M+D1Kz5p 3+m/TBOk6Sd2nci2lMUPot9ShHOaR6hu0Lit2ozJn+QLsDlKUqAztZdmP YScLTt1YwMECrB1J8Yi9MNsYUhtmnz9Hr1BjKbPZYW91jCvLY6sIh6WOV DTNse9CuDhL9iKc+GvXVMY1p91winzNXxb1wUPPWry1PRiOP+mSJzhZ1I AwjQqFo0r3N9kpLmPNV3G8fy3sqxpVMn4v0RRFnpr77l6D/CdOKSUq1ih 0j0bKZhGgaKPig/lzX/45xXRxK71x3a+wIncxrVKJ2TfbUdRr3WWzqLiz g==; X-CSE-ConnectionGUID: ol8zE+5pQbyz8nKT026TwA== X-CSE-MsgGUID: qeUa0UBVQQC6QhPvpBKfdA== X-IronPort-AV: E=Sophos;i="6.16,333,1744095600"; d="scan'208";a="275694684" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa5.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 22 Jul 2025 19:26:37 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.87.72) by chn-vm-ex02.mchp-main.com (10.10.87.72) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.44; Tue, 22 Jul 2025 19:26:14 -0700 Received: from pop-os.microchip.com (10.10.85.11) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.44 via Frontend Transport; Tue, 22 Jul 2025 19:26:14 -0700 From: To: Woojung Huh , Andrew Lunn , Vladimir Oltean , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley CC: Maxime Chevallier , Simon Horman , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Marek Vasut , , , , , Tristram Ha Subject: [PATCH net-next v5 2/6] net: dsa: microchip: Add KSZ8463 switch support to KSZ DSA driver Date: Tue, 22 Jul 2025 19:26:08 -0700 Message-ID: <20250723022612.38535-3-Tristram.Ha@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250723022612.38535-1-Tristram.Ha@microchip.com> References: <20250723022612.38535-1-Tristram.Ha@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Tristram Ha KSZ8463 switch is a 3-port switch based from KSZ8863. Its major difference from other KSZ SPI switches is its register access is not a simple continual 8-bit transfer with automatic address increase but uses a byte-enable mechanism specifying 8-bit, 16-bit, or 32-bit access. Its registers are also defined in 16-bit format because it shares a design with a MAC controller using 16-bit access. As a result some common register accesses need to be re-arranged. The 64-bit access used by other switches needs to be broken into 2 32-bit accesses. This patch adds the basic structure for using KSZ8463. It cannot use the same regmap table for other KSZ switches as it interprets the 16-bit value as little-endian and its SPI commands are different. KSZ8463 uses a byte-enable mechanism to specify 8-bit, 16-bit, and 32-bit access. The register is first shifted right by 2 then left by 4. Extra 4 bits are added. If the access is 8-bit one of the 4 bits is set. If the access is 16-bit two of the 4 bits are set. If the access is 32-bit all 4 bits are set. The SPI command for read or write is then added. Because of this register transformation separate SPI read and write functions are provided for KSZ8463. KSZ8463's internal PHYs use standard PHY register definitions so there is no need to remap things. However, the hardware has a bug that the high word and low word of the PHY id are swapped. In addition the port registers are arranged differently so KSZ8463 has its own mapping for port registers and PHY registers. Therefore the PORT_CTRL_ADDR macro is replaced with the get_port_addr helper function. Signed-off-by: Tristram Ha --- v5 - Use separate SPI read and write functions for KSZ8463 - remove inline keyword inside ksz8.c v4 - Fix a typo in ksz8_reg.h - Fix logic in ksz8463_r_phy() drivers/net/dsa/microchip/ksz8.c | 83 +++++++++++++- drivers/net/dsa/microchip/ksz8.h | 4 + drivers/net/dsa/microchip/ksz8_reg.h | 49 +++++++++ drivers/net/dsa/microchip/ksz_common.c | 114 ++++++++++++++++++++ drivers/net/dsa/microchip/ksz_common.h | 52 ++++++++- drivers/net/dsa/microchip/ksz_spi.c | 68 ++++++++++++ include/linux/platform_data/microchip-ksz.h | 1 + 7 files changed, 368 insertions(+), 3 deletions(-) diff --git a/drivers/net/dsa/microchip/ksz8.c b/drivers/net/dsa/microchip/k= sz8.c index be433b4e2b1c..3761a81a7320 100644 --- a/drivers/net/dsa/microchip/ksz8.c +++ b/drivers/net/dsa/microchip/ksz8.c @@ -3,6 +3,7 @@ * Microchip KSZ8XXX series switch driver * * It supports the following switches: + * - KSZ8463 * - KSZ8863, KSZ8873 aka KSZ88X3 * - KSZ8895, KSZ8864 aka KSZ8895 family * - KSZ8794, KSZ8795, KSZ8765 aka KSZ87XX @@ -41,7 +42,8 @@ static void ksz_cfg(struct ksz_device *dev, u32 addr, u8 = bits, bool set) static void ksz_port_cfg(struct ksz_device *dev, int port, int offset, u8 = bits, bool set) { - regmap_update_bits(ksz_regmap_8(dev), PORT_CTRL_ADDR(port, offset), + regmap_update_bits(ksz_regmap_8(dev), + dev->dev_ops->get_port_addr(port, offset), bits, set ? bits : 0); } =20 @@ -194,6 +196,7 @@ int ksz8_change_mtu(struct ksz_device *dev, int port, i= nt mtu) case KSZ8794_CHIP_ID: case KSZ8765_CHIP_ID: return ksz8795_change_mtu(dev, frame_size); + case KSZ8463_CHIP_ID: case KSZ88X3_CHIP_ID: case KSZ8864_CHIP_ID: case KSZ8895_CHIP_ID: @@ -1947,6 +1950,84 @@ u32 ksz8_get_port_addr(int port, int offset) return PORT_CTRL_ADDR(port, offset); } =20 +u32 ksz8463_get_port_addr(int port, int offset) +{ + return offset + 0x18 * port; +} + +static u16 ksz8463_get_phy_addr(u16 phy, u16 reg, u16 offset) +{ + return offset + reg * 2 + phy * (P2MBCR - P1MBCR); +} + +int ksz8463_r_phy(struct ksz_device *dev, u16 phy, u16 reg, u16 *val) +{ + u16 sw_reg =3D 0; + u16 data =3D 0; + int ret; + + if (phy > 1) + return -ENOSPC; + switch (reg) { + case MII_PHYSID1: + sw_reg =3D ksz8463_get_phy_addr(phy, 0, PHY1IHR); + break; + case MII_PHYSID2: + sw_reg =3D ksz8463_get_phy_addr(phy, 0, PHY1ILR); + break; + case MII_BMCR: + case MII_BMSR: + case MII_ADVERTISE: + case MII_LPA: + sw_reg =3D ksz8463_get_phy_addr(phy, reg, P1MBCR); + break; + case MII_TPISTATUS: + /* This register holds the PHY interrupt status for simulated + * Micrel KSZ PHY. + */ + data =3D 0x0505; + break; + default: + break; + } + if (sw_reg) { + ret =3D ksz_read16(dev, sw_reg, &data); + if (ret) + return ret; + } + *val =3D data; + + return 0; +} + +int ksz8463_w_phy(struct ksz_device *dev, u16 phy, u16 reg, u16 val) +{ + u16 sw_reg =3D 0; + int ret; + + if (phy > 1) + return -ENOSPC; + + /* No write to fiber port. */ + if (dev->ports[phy].fiber) + return 0; + switch (reg) { + case MII_BMCR: + case MII_ADVERTISE: + sw_reg =3D ksz8463_get_phy_addr(phy, reg, P1MBCR); + break; + default: + break; + } + if (sw_reg) { + ret =3D ksz_write16(dev, sw_reg, val); + if (ret) + return ret; + } + + return 0; +} + int ksz8_switch_init(struct ksz_device *dev) { dev->cpu_port =3D fls(dev->info->cpu_ports) - 1; diff --git a/drivers/net/dsa/microchip/ksz8.h b/drivers/net/dsa/microchip/k= sz8.h index e1c79ff97123..0f2cd1474b44 100644 --- a/drivers/net/dsa/microchip/ksz8.h +++ b/drivers/net/dsa/microchip/ksz8.h @@ -63,4 +63,8 @@ void ksz8_phylink_mac_link_up(struct phylink_config *conf= ig, bool tx_pause, bool rx_pause); int ksz8_all_queues_split(struct ksz_device *dev, int queues); =20 +u32 ksz8463_get_port_addr(int port, int offset); +int ksz8463_r_phy(struct ksz_device *dev, u16 phy, u16 reg, u16 *val); +int ksz8463_w_phy(struct ksz_device *dev, u16 phy, u16 reg, u16 val); + #endif diff --git a/drivers/net/dsa/microchip/ksz8_reg.h b/drivers/net/dsa/microch= ip/ksz8_reg.h index 329688603a58..491aa1e50175 100644 --- a/drivers/net/dsa/microchip/ksz8_reg.h +++ b/drivers/net/dsa/microchip/ksz8_reg.h @@ -729,6 +729,55 @@ #define PHY_POWER_SAVING_ENABLE BIT(2) #define PHY_REMOTE_LOOPBACK BIT(1) =20 +/* KSZ8463 specific registers. */ +#define P1MBCR 0x4C +#define P1MBSR 0x4E +#define PHY1ILR 0x50 +#define PHY1IHR 0x52 +#define P1ANAR 0x54 +#define P1ANLPR 0x56 +#define P2MBCR 0x58 +#define P2MBSR 0x5A +#define PHY2ILR 0x5C +#define PHY2IHR 0x5E +#define P2ANAR 0x60 +#define P2ANLPR 0x62 + +#define P1CR1 0x6C +#define P1CR2 0x6E +#define P1CR3 0x72 +#define P1CR4 0x7E +#define P1SR 0x80 + +#define KSZ8463_FLUSH_TABLE_CTRL 0xAD + +#define KSZ8463_FLUSH_DYN_MAC_TABLE BIT(2) +#define KSZ8463_FLUSH_STA_MAC_TABLE BIT(1) + +#define KSZ8463_REG_SW_CTRL_9 0xAE + +#define KSZ8463_REG_CFG_CTRL 0xD8 + +#define PORT_2_COPPER_MODE BIT(7) +#define PORT_1_COPPER_MODE BIT(6) +#define PORT_COPPER_MODE_S 6 + +#define KSZ8463_REG_SW_RESET 0x126 + +#define KSZ8463_GLOBAL_SOFTWARE_RESET BIT(0) + +#define KSZ8463_PTP_CLK_CTRL 0x600 + +#define PTP_CLK_ENABLE BIT(1) + +#define KSZ8463_PTP_MSG_CONF1 0x620 + +#define PTP_ENABLE BIT(6) + +#define KSZ8463_REG_DSP_CTRL_6 0x734 + +#define COPPER_RECEIVE_ADJUSTMENT BIT(13) + /* Chip resource */ =20 #define PRIO_QUEUES 4 diff --git a/drivers/net/dsa/microchip/ksz_common.c b/drivers/net/dsa/micro= chip/ksz_common.c index 6e1daf0018bc..095e647b3897 100644 --- a/drivers/net/dsa/microchip/ksz_common.c +++ b/drivers/net/dsa/microchip/ksz_common.c @@ -331,6 +331,38 @@ static const struct phylink_mac_ops ksz8_phylink_mac_o= ps =3D { .mac_enable_tx_lpi =3D ksz_phylink_mac_enable_tx_lpi, }; =20 +static const struct ksz_dev_ops ksz8463_dev_ops =3D { + .setup =3D ksz8_setup, + .get_port_addr =3D ksz8463_get_port_addr, + .cfg_port_member =3D ksz8_cfg_port_member, + .flush_dyn_mac_table =3D ksz8_flush_dyn_mac_table, + .port_setup =3D ksz8_port_setup, + .r_phy =3D ksz8463_r_phy, + .w_phy =3D ksz8463_w_phy, + .r_mib_cnt =3D ksz8_r_mib_cnt, + .r_mib_pkt =3D ksz8_r_mib_pkt, + .r_mib_stat64 =3D ksz88xx_r_mib_stats64, + .freeze_mib =3D ksz8_freeze_mib, + .port_init_cnt =3D ksz8_port_init_cnt, + .fdb_dump =3D ksz8_fdb_dump, + .fdb_add =3D ksz8_fdb_add, + .fdb_del =3D ksz8_fdb_del, + .mdb_add =3D ksz8_mdb_add, + .mdb_del =3D ksz8_mdb_del, + .vlan_filtering =3D ksz8_port_vlan_filtering, + .vlan_add =3D ksz8_port_vlan_add, + .vlan_del =3D ksz8_port_vlan_del, + .mirror_add =3D ksz8_port_mirror_add, + .mirror_del =3D ksz8_port_mirror_del, + .get_caps =3D ksz8_get_caps, + .config_cpu_port =3D ksz8_config_cpu_port, + .enable_stp_addr =3D ksz8_enable_stp_addr, + .reset =3D ksz8_reset_switch, + .init =3D ksz8_switch_init, + .exit =3D ksz8_switch_exit, + .change_mtu =3D ksz8_change_mtu, +}; + static const struct ksz_dev_ops ksz88xx_dev_ops =3D { .setup =3D ksz8_setup, .get_port_addr =3D ksz8_get_port_addr, @@ -517,6 +549,60 @@ static const struct ksz_dev_ops lan937x_dev_ops =3D { .exit =3D lan937x_switch_exit, }; =20 +static const u16 ksz8463_regs[] =3D { + [REG_SW_MAC_ADDR] =3D 0x10, + [REG_IND_CTRL_0] =3D 0x30, + [REG_IND_DATA_8] =3D 0x26, + [REG_IND_DATA_CHECK] =3D 0x26, + [REG_IND_DATA_HI] =3D 0x28, + [REG_IND_DATA_LO] =3D 0x2C, + [REG_IND_MIB_CHECK] =3D 0x2F, + [P_FORCE_CTRL] =3D 0x0C, + [P_LINK_STATUS] =3D 0x0E, + [P_LOCAL_CTRL] =3D 0x0C, + [P_NEG_RESTART_CTRL] =3D 0x0D, + [P_REMOTE_STATUS] =3D 0x0E, + [P_SPEED_STATUS] =3D 0x0F, + [S_TAIL_TAG_CTRL] =3D 0xAD, + [P_STP_CTRL] =3D 0x6F, + [S_START_CTRL] =3D 0x01, + [S_BROADCAST_CTRL] =3D 0x06, + [S_MULTICAST_CTRL] =3D 0x04, +}; + +static const u32 ksz8463_masks[] =3D { + [PORT_802_1P_REMAPPING] =3D BIT(3), + [SW_TAIL_TAG_ENABLE] =3D BIT(0), + [MIB_COUNTER_OVERFLOW] =3D BIT(7), + [MIB_COUNTER_VALID] =3D BIT(6), + [VLAN_TABLE_FID] =3D GENMASK(15, 12), + [VLAN_TABLE_MEMBERSHIP] =3D GENMASK(18, 16), + [VLAN_TABLE_VALID] =3D BIT(19), + [STATIC_MAC_TABLE_VALID] =3D BIT(19), + [STATIC_MAC_TABLE_USE_FID] =3D BIT(21), + [STATIC_MAC_TABLE_FID] =3D GENMASK(25, 22), + [STATIC_MAC_TABLE_OVERRIDE] =3D BIT(20), + [STATIC_MAC_TABLE_FWD_PORTS] =3D GENMASK(18, 16), + [DYNAMIC_MAC_TABLE_ENTRIES_H] =3D GENMASK(1, 0), + [DYNAMIC_MAC_TABLE_MAC_EMPTY] =3D BIT(2), + [DYNAMIC_MAC_TABLE_NOT_READY] =3D BIT(7), + [DYNAMIC_MAC_TABLE_ENTRIES] =3D GENMASK(31, 24), + [DYNAMIC_MAC_TABLE_FID] =3D GENMASK(19, 16), + [DYNAMIC_MAC_TABLE_SRC_PORT] =3D GENMASK(21, 20), + [DYNAMIC_MAC_TABLE_TIMESTAMP] =3D GENMASK(23, 22), +}; + +static u8 ksz8463_shifts[] =3D { + [VLAN_TABLE_MEMBERSHIP_S] =3D 16, + [STATIC_MAC_FWD_PORTS] =3D 16, + [STATIC_MAC_FID] =3D 22, + [DYNAMIC_MAC_ENTRIES_H] =3D 8, + [DYNAMIC_MAC_ENTRIES] =3D 24, + [DYNAMIC_MAC_FID] =3D 16, + [DYNAMIC_MAC_TIMESTAMP] =3D 22, + [DYNAMIC_MAC_SRC_PORT] =3D 20, +}; + static const u16 ksz8795_regs[] =3D { [REG_SW_MAC_ADDR] =3D 0x68, [REG_IND_CTRL_0] =3D 0x6E, @@ -1387,6 +1473,29 @@ static const struct regmap_access_table ksz8873_regi= ster_set =3D { }; =20 const struct ksz_chip_data ksz_switch_chips[] =3D { + [KSZ8463] =3D { + .chip_id =3D KSZ8463_CHIP_ID, + .dev_name =3D "KSZ8463", + .num_vlans =3D 16, + .num_alus =3D 0, + .num_statics =3D 8, + .cpu_ports =3D 0x4, /* can be configured as cpu port */ + .port_cnt =3D 3, + .num_tx_queues =3D 4, + .num_ipms =3D 4, + .ops =3D &ksz8463_dev_ops, + .phylink_mac_ops =3D &ksz88x3_phylink_mac_ops, + .mib_names =3D ksz88xx_mib_names, + .mib_cnt =3D ARRAY_SIZE(ksz88xx_mib_names), + .reg_mib_cnt =3D MIB_COUNTER_NUM, + .regs =3D ksz8463_regs, + .masks =3D ksz8463_masks, + .shifts =3D ksz8463_shifts, + .supports_mii =3D {false, false, true}, + .supports_rmii =3D {false, false, true}, + .internal_phy =3D {true, true, false}, + }, + [KSZ8563] =3D { .chip_id =3D KSZ8563_CHIP_ID, .dev_name =3D "KSZ8563", @@ -3400,6 +3509,7 @@ static enum dsa_tag_protocol ksz_get_tag_protocol(str= uct dsa_switch *ds, proto =3D DSA_TAG_PROTO_KSZ8795; =20 if (dev->chip_id =3D=3D KSZ88X3_CHIP_ID || + dev->chip_id =3D=3D KSZ8463_CHIP_ID || dev->chip_id =3D=3D KSZ8563_CHIP_ID || dev->chip_id =3D=3D KSZ9893_CHIP_ID || dev->chip_id =3D=3D KSZ9563_CHIP_ID) @@ -3512,6 +3622,7 @@ static int ksz_max_mtu(struct dsa_switch *ds, int por= t) case KSZ8794_CHIP_ID: case KSZ8765_CHIP_ID: return KSZ8795_HUGE_PACKET_SIZE - VLAN_ETH_HLEN - ETH_FCS_LEN; + case KSZ8463_CHIP_ID: case KSZ88X3_CHIP_ID: case KSZ8864_CHIP_ID: case KSZ8895_CHIP_ID: @@ -3866,6 +3977,9 @@ static int ksz_switch_detect(struct ksz_device *dev) id2 =3D FIELD_GET(SW_CHIP_ID_M, id16); =20 switch (id1) { + case KSZ84_FAMILY_ID: + dev->chip_id =3D KSZ8463_CHIP_ID; + break; case KSZ87_FAMILY_ID: if (id2 =3D=3D KSZ87_CHIP_ID_95) { u8 val; diff --git a/drivers/net/dsa/microchip/ksz_common.h b/drivers/net/dsa/micro= chip/ksz_common.h index a08417df2ca4..ab728f788285 100644 --- a/drivers/net/dsa/microchip/ksz_common.h +++ b/drivers/net/dsa/microchip/ksz_common.h @@ -222,6 +222,7 @@ struct ksz_device { =20 /* List of supported models */ enum ksz_model { + KSZ8463, KSZ8563, KSZ8567, KSZ8795, @@ -484,6 +485,11 @@ static inline struct regmap *ksz_regmap_32(struct ksz_= device *dev) return dev->regmap[KSZ_REGMAP_32]; } =20 +static inline bool ksz_is_ksz8463(struct ksz_device *dev) +{ + return dev->chip_id =3D=3D KSZ8463_CHIP_ID; +} + static inline int ksz_read8(struct ksz_device *dev, u32 reg, u8 *val) { unsigned int value; @@ -528,6 +534,15 @@ static inline int ksz_read64(struct ksz_device *dev, u= 32 reg, u64 *val) u32 value[2]; int ret; =20 + if (ksz_is_ksz8463(dev)) { + int i; + + for (i =3D 0; i < 2; i++) + ret =3D regmap_read(ksz_regmap_32(dev), reg + i * 4, + &value[i]); + *val =3D (u64)value[0] << 32 | value[1]; + return ret; + } ret =3D regmap_bulk_read(ksz_regmap_32(dev), reg, value, 2); if (ret) dev_err(dev->dev, "can't read 64bit reg: 0x%x %pe\n", reg, @@ -609,6 +624,14 @@ static inline int ksz_write64(struct ksz_device *dev, = u32 reg, u64 value) val[0] =3D swab32(value & 0xffffffffULL); val[1] =3D swab32(value >> 32ULL); =20 + if (ksz_is_ksz8463(dev)) { + int i, ret; + + for (i =3D 0; i < 2; i++) + ret =3D regmap_write(ksz_regmap_32(dev), reg + i * 4, + val[i]); + return ret; + } return regmap_bulk_write(ksz_regmap_32(dev), reg, val, 2); } =20 @@ -709,12 +732,13 @@ static inline bool ksz_is_8895_family(struct ksz_devi= ce *dev) static inline bool is_ksz8(struct ksz_device *dev) { return ksz_is_ksz87xx(dev) || ksz_is_ksz88x3(dev) || - ksz_is_8895_family(dev); + ksz_is_8895_family(dev) || ksz_is_ksz8463(dev); } =20 static inline bool is_ksz88xx(struct ksz_device *dev) { - return ksz_is_ksz88x3(dev) || ksz_is_8895_family(dev); + return ksz_is_ksz88x3(dev) || ksz_is_8895_family(dev) || + ksz_is_ksz8463(dev); } =20 static inline bool is_ksz9477(struct ksz_device *dev) @@ -761,6 +785,7 @@ static inline bool ksz_is_sgmii_port(struct ksz_device = *dev, int port) #define REG_CHIP_ID0 0x00 =20 #define SW_FAMILY_ID_M GENMASK(15, 8) +#define KSZ84_FAMILY_ID 0x84 #define KSZ87_FAMILY_ID 0x87 #define KSZ88_FAMILY_ID 0x88 #define KSZ8895_FAMILY_ID 0x95 @@ -939,4 +964,27 @@ static inline bool ksz_is_sgmii_port(struct ksz_device= *dev, int port) [KSZ_REGMAP_32] =3D KSZ_REGMAP_ENTRY(32, swp, (regbits), (regpad), (rega= lign)), \ } =20 +#define KSZ8463_REGMAP_ENTRY(width, regbits, regpad, regalign) \ + { \ + .name =3D #width, \ + .val_bits =3D (width), \ + .reg_stride =3D 1, \ + .reg_bits =3D (regbits) + (regalign), \ + .pad_bits =3D (regpad), \ + .read =3D ksz8463_spi_read, \ + .write =3D ksz8463_spi_write, \ + .max_register =3D BIT(regbits) - 1, \ + .cache_type =3D REGCACHE_NONE, \ + .zero_flag_mask =3D 1, \ + .lock =3D ksz_regmap_lock, \ + .unlock =3D ksz_regmap_unlock, \ + } + +#define KSZ8463_REGMAP_TABLE(ksz, regbits, regpad, regalign) \ + static const struct regmap_config ksz##_regmap_config[] =3D { \ + [KSZ_REGMAP_8] =3D KSZ8463_REGMAP_ENTRY(8, (regbits), (regpad), (regalig= n)), \ + [KSZ_REGMAP_16] =3D KSZ8463_REGMAP_ENTRY(16, (regbits), (regpad), (regal= ign)), \ + [KSZ_REGMAP_32] =3D KSZ8463_REGMAP_ENTRY(32, (regbits), (regpad), (regal= ign)), \ + } + #endif diff --git a/drivers/net/dsa/microchip/ksz_spi.c b/drivers/net/dsa/microchi= p/ksz_spi.c index b633d263098c..4ec209f49ccb 100644 --- a/drivers/net/dsa/microchip/ksz_spi.c +++ b/drivers/net/dsa/microchip/ksz_spi.c @@ -16,6 +16,10 @@ =20 #include "ksz_common.h" =20 +#define KSZ8463_SPI_ADDR_SHIFT 13 +#define KSZ8463_SPI_ADDR_ALIGN 3 +#define KSZ8463_SPI_TURNAROUND_SHIFT 2 + #define KSZ8795_SPI_ADDR_SHIFT 12 #define KSZ8795_SPI_ADDR_ALIGN 3 #define KSZ8795_SPI_TURNAROUND_SHIFT 1 @@ -37,6 +41,63 @@ KSZ_REGMAP_TABLE(ksz8863, 16, KSZ8863_SPI_ADDR_SHIFT, KSZ_REGMAP_TABLE(ksz9477, 32, KSZ9477_SPI_ADDR_SHIFT, KSZ9477_SPI_TURNAROUND_SHIFT, KSZ9477_SPI_ADDR_ALIGN); =20 +static u16 ksz8463_reg(u16 reg, size_t size) +{ + switch (size) { + case 1: + reg =3D ((reg >> 2) << 4) | (1 << (reg & 3)); + break; + case 2: + reg =3D ((reg >> 2) << 4) | (reg & 2 ? 0x0c : 0x03); + break; + default: + reg =3D ((reg >> 2) << 4) | 0xf; + break; + } + reg <<=3D KSZ8463_SPI_TURNAROUND_SHIFT; + return reg; +} + +static int ksz8463_spi_read(void *context, + const void *reg, size_t reg_size, + void *val, size_t val_size) +{ + struct device *dev =3D context; + struct spi_device *spi =3D to_spi_device(dev); + u8 bytes[2]; + u16 cmd; + + if (reg_size > 2 || val_size > 4) + return -EINVAL; + memcpy(bytes, reg, reg_size); + cmd =3D ((u16)bytes[1] << 8) | bytes[0]; + cmd =3D ksz8463_reg(cmd, val_size); + bytes[0] =3D (u8)(cmd >> 8); + bytes[1] =3D (u8)cmd; + return spi_write_then_read(spi, bytes, reg_size, val, val_size); +} + +static int ksz8463_spi_write(void *context, const void *data, size_t count) +{ + struct device *dev =3D context; + struct spi_device *spi =3D to_spi_device(dev); + u8 bytes[6]; + u16 cmd; + + if (count <=3D 2 || count > 6) + return -EINVAL; + memcpy(bytes, data, count); + cmd =3D ((u16)bytes[1] << 8) | bytes[0]; + cmd =3D ksz8463_reg(cmd, count - 2); + cmd |=3D (1 << (KSZ8463_SPI_ADDR_SHIFT + KSZ8463_SPI_TURNAROUND_SHIFT)); + bytes[0] =3D (u8)(cmd >> 8); + bytes[1] =3D (u8)cmd; + return spi_write(spi, bytes, count); +} + +KSZ8463_REGMAP_TABLE(ksz8463, KSZ8463_SPI_ADDR_SHIFT, 0, + KSZ8463_SPI_ADDR_ALIGN); + static int ksz_spi_probe(struct spi_device *spi) { const struct regmap_config *regmap_config; @@ -58,6 +119,8 @@ static int ksz_spi_probe(struct spi_device *spi) dev->chip_id =3D chip->chip_id; if (chip->chip_id =3D=3D KSZ88X3_CHIP_ID) regmap_config =3D ksz8863_regmap_config; + else if (chip->chip_id =3D=3D KSZ8463_CHIP_ID) + regmap_config =3D ksz8463_regmap_config; else if (chip->chip_id =3D=3D KSZ8795_CHIP_ID || chip->chip_id =3D=3D KSZ8794_CHIP_ID || chip->chip_id =3D=3D KSZ8765_CHIP_ID) @@ -125,6 +188,10 @@ static void ksz_spi_shutdown(struct spi_device *spi) } =20 static const struct of_device_id ksz_dt_ids[] =3D { + { + .compatible =3D "microchip,ksz8463", + .data =3D &ksz_switch_chips[KSZ8463] + }, { .compatible =3D "microchip,ksz8765", .data =3D &ksz_switch_chips[KSZ8765] @@ -214,6 +281,7 @@ static const struct of_device_id ksz_dt_ids[] =3D { MODULE_DEVICE_TABLE(of, ksz_dt_ids); =20 static const struct spi_device_id ksz_spi_ids[] =3D { + { "ksz8463" }, { "ksz8765" }, { "ksz8794" }, { "ksz8795" }, diff --git a/include/linux/platform_data/microchip-ksz.h b/include/linux/pl= atform_data/microchip-ksz.h index 0e0e8fe6975f..028781ad4059 100644 --- a/include/linux/platform_data/microchip-ksz.h +++ b/include/linux/platform_data/microchip-ksz.h @@ -23,6 +23,7 @@ #include =20 enum ksz_chip_id { + KSZ8463_CHIP_ID =3D 0x8463, KSZ8563_CHIP_ID =3D 0x8563, KSZ8795_CHIP_ID =3D 0x8795, KSZ8794_CHIP_ID =3D 0x8794, --=20 2.34.1 From nobody Mon Oct 6 08:24:27 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B8B8B1E1DE7; Wed, 23 Jul 2025 02:26:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; 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Miller" , Eric Dumazet , Paolo Abeni , Marek Vasut , , , , , Tristram Ha Subject: [PATCH net-next v5 3/6] net: dsa: microchip: Use different registers for KSZ8463 Date: Tue, 22 Jul 2025 19:26:09 -0700 Message-ID: <20250723022612.38535-4-Tristram.Ha@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250723022612.38535-1-Tristram.Ha@microchip.com> References: <20250723022612.38535-1-Tristram.Ha@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Tristram Ha KSZ8463 does not use same set of registers as KSZ8863 so it is necessary to change some registers when using KSZ8463. Signed-off-by: Tristram Ha --- v3 - Replace cpu_to_be16() with swab16() to avoid compiler warning drivers/net/dsa/microchip/ksz8.c | 78 +++++++++++++++++++------- drivers/net/dsa/microchip/ksz_common.c | 32 +++++++++-- drivers/net/dsa/microchip/ksz_dcb.c | 10 +++- 3 files changed, 92 insertions(+), 28 deletions(-) diff --git a/drivers/net/dsa/microchip/ksz8.c b/drivers/net/dsa/microchip/k= sz8.c index 3761a81a7320..55c1460b8b2e 100644 --- a/drivers/net/dsa/microchip/ksz8.c +++ b/drivers/net/dsa/microchip/ksz8.c @@ -142,6 +142,11 @@ int ksz8_reset_switch(struct ksz_device *dev) KSZ8863_GLOBAL_SOFTWARE_RESET | KSZ8863_PCS_RESET, true); ksz_cfg(dev, KSZ8863_REG_SW_RESET, KSZ8863_GLOBAL_SOFTWARE_RESET | KSZ8863_PCS_RESET, false); + } else if (ksz_is_ksz8463(dev)) { + ksz_cfg(dev, KSZ8463_REG_SW_RESET, + KSZ8463_GLOBAL_SOFTWARE_RESET, true); + ksz_cfg(dev, KSZ8463_REG_SW_RESET, + KSZ8463_GLOBAL_SOFTWARE_RESET, false); } else { /* reset switch */ ksz_write8(dev, REG_POWER_MANAGEMENT_1, @@ -230,6 +235,11 @@ static int ksz8_port_queue_split(struct ksz_device *de= v, int port, int queues) WEIGHTED_FAIR_QUEUE_ENABLE); if (ret) return ret; + } else if (ksz_is_ksz8463(dev)) { + mask_4q =3D KSZ8873_PORT_4QUEUE_SPLIT_EN; + mask_2q =3D KSZ8873_PORT_2QUEUE_SPLIT_EN; + reg_4q =3D P1CR1; + reg_2q =3D P1CR1 + 1; } else { mask_4q =3D KSZ8795_PORT_4QUEUE_SPLIT_EN; mask_2q =3D KSZ8795_PORT_2QUEUE_SPLIT_EN; @@ -1268,12 +1278,15 @@ int ksz8_w_phy(struct ksz_device *dev, u16 phy, u16= reg, u16 val) =20 void ksz8_cfg_port_member(struct ksz_device *dev, int port, u8 member) { + int offset =3D P_MIRROR_CTRL; u8 data; =20 - ksz_pread8(dev, port, P_MIRROR_CTRL, &data); - data &=3D ~PORT_VLAN_MEMBERSHIP; + if (ksz_is_ksz8463(dev)) + offset =3D P1CR2; + ksz_pread8(dev, port, offset, &data); + data &=3D ~dev->port_mask; data |=3D (member & dev->port_mask); - ksz_pwrite8(dev, port, P_MIRROR_CTRL, data); + ksz_pwrite8(dev, port, offset, data); } =20 void ksz8_flush_dyn_mac_table(struct ksz_device *dev, int port) @@ -1281,6 +1294,8 @@ void ksz8_flush_dyn_mac_table(struct ksz_device *dev,= int port) u8 learn[DSA_MAX_PORTS]; int first, index, cnt; const u16 *regs; + int reg =3D S_FLUSH_TABLE_CTRL; + int mask =3D SW_FLUSH_DYN_MAC_TABLE; =20 regs =3D dev->info->regs; =20 @@ -1298,7 +1313,11 @@ void ksz8_flush_dyn_mac_table(struct ksz_device *dev= , int port) ksz_pwrite8(dev, index, regs[P_STP_CTRL], learn[index] | PORT_LEARN_DISABLE); } - ksz_cfg(dev, S_FLUSH_TABLE_CTRL, SW_FLUSH_DYN_MAC_TABLE, true); + if (ksz_is_ksz8463(dev)) { + reg =3D KSZ8463_FLUSH_TABLE_CTRL; + mask =3D KSZ8463_FLUSH_DYN_MAC_TABLE; + } + ksz_cfg(dev, reg, mask, true); for (index =3D first; index < cnt; index++) { if (!(learn[index] & PORT_LEARN_DISABLE)) ksz_pwrite8(dev, index, regs[P_STP_CTRL], learn[index]); @@ -1437,7 +1456,7 @@ int ksz8_fdb_del(struct ksz_device *dev, int port, co= nst unsigned char *addr, int ksz8_port_vlan_filtering(struct ksz_device *dev, int port, bool flag, struct netlink_ext_ack *extack) { - if (ksz_is_ksz88x3(dev)) + if (ksz_is_ksz88x3(dev) || ksz_is_ksz8463(dev)) return -ENOTSUPP; =20 /* Discard packets with VID not enabled on the switch */ @@ -1453,9 +1472,12 @@ int ksz8_port_vlan_filtering(struct ksz_device *dev,= int port, bool flag, =20 static void ksz8_port_enable_pvid(struct ksz_device *dev, int port, bool s= tate) { - if (ksz_is_ksz88x3(dev)) { - ksz_cfg(dev, REG_SW_INSERT_SRC_PVID, - 0x03 << (4 - 2 * port), state); + if (ksz_is_ksz88x3(dev) || ksz_is_ksz8463(dev)) { + int reg =3D REG_SW_INSERT_SRC_PVID; + + if (ksz_is_ksz8463(dev)) + reg =3D KSZ8463_REG_SW_CTRL_9; + ksz_cfg(dev, reg, 0x03 << (4 - 2 * port), state); } else { ksz_pwrite8(dev, port, REG_PORT_CTRL_12, state ? 0x0f : 0x00); } @@ -1470,7 +1492,7 @@ int ksz8_port_vlan_add(struct ksz_device *dev, int po= rt, u16 data, new_pvid =3D 0; u8 fid, member, valid; =20 - if (ksz_is_ksz88x3(dev)) + if (ksz_is_ksz88x3(dev) || ksz_is_ksz8463(dev)) return -ENOTSUPP; =20 /* If a VLAN is added with untagged flag different from the @@ -1539,7 +1561,7 @@ int ksz8_port_vlan_del(struct ksz_device *dev, int po= rt, u16 data, pvid; u8 fid, member, valid; =20 - if (ksz_is_ksz88x3(dev)) + if (ksz_is_ksz88x3(dev) || ksz_is_ksz8463(dev)) return -ENOTSUPP; =20 ksz_pread16(dev, port, REG_PORT_CTRL_VID, &pvid); @@ -1569,19 +1591,23 @@ int ksz8_port_mirror_add(struct ksz_device *dev, in= t port, struct dsa_mall_mirror_tc_entry *mirror, bool ingress, struct netlink_ext_ack *extack) { + int offset =3D P_MIRROR_CTRL; + + if (ksz_is_ksz8463(dev)) + offset =3D P1CR2; if (ingress) { - ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_RX, true); + ksz_port_cfg(dev, port, offset, PORT_MIRROR_RX, true); dev->mirror_rx |=3D BIT(port); } else { - ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_TX, true); + ksz_port_cfg(dev, port, offset, PORT_MIRROR_TX, true); dev->mirror_tx |=3D BIT(port); } =20 - ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_SNIFFER, false); + ksz_port_cfg(dev, port, offset, PORT_MIRROR_SNIFFER, false); =20 /* configure mirror port */ if (dev->mirror_rx || dev->mirror_tx) - ksz_port_cfg(dev, mirror->to_local_port, P_MIRROR_CTRL, + ksz_port_cfg(dev, mirror->to_local_port, offset, PORT_MIRROR_SNIFFER, true); =20 return 0; @@ -1590,20 +1616,23 @@ int ksz8_port_mirror_add(struct ksz_device *dev, in= t port, void ksz8_port_mirror_del(struct ksz_device *dev, int port, struct dsa_mall_mirror_tc_entry *mirror) { + int offset =3D P_MIRROR_CTRL; u8 data; =20 + if (ksz_is_ksz8463(dev)) + offset =3D P1CR2; if (mirror->ingress) { - ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_RX, false); + ksz_port_cfg(dev, port, offset, PORT_MIRROR_RX, false); dev->mirror_rx &=3D ~BIT(port); } else { - ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_TX, false); + ksz_port_cfg(dev, port, offset, PORT_MIRROR_TX, false); dev->mirror_tx &=3D ~BIT(port); } =20 - ksz_pread8(dev, port, P_MIRROR_CTRL, &data); + ksz_pread8(dev, port, offset, &data); =20 if (!dev->mirror_rx && !dev->mirror_tx) - ksz_port_cfg(dev, mirror->to_local_port, P_MIRROR_CTRL, + ksz_port_cfg(dev, mirror->to_local_port, offset, PORT_MIRROR_SNIFFER, false); } =20 @@ -1628,17 +1657,24 @@ void ksz8_port_setup(struct ksz_device *dev, int po= rt, bool cpu_port) const u16 *regs =3D dev->info->regs; struct dsa_switch *ds =3D dev->ds; const u32 *masks; + int offset; u8 member; =20 masks =3D dev->info->masks; =20 /* enable broadcast storm limit */ - ksz_port_cfg(dev, port, P_BCAST_STORM_CTRL, PORT_BROADCAST_STORM, true); + offset =3D P_BCAST_STORM_CTRL; + if (ksz_is_ksz8463(dev)) + offset =3D P1CR1; + ksz_port_cfg(dev, port, offset, PORT_BROADCAST_STORM, true); =20 ksz8_port_queue_split(dev, port, dev->info->num_tx_queues); =20 /* replace priority */ - ksz_port_cfg(dev, port, P_802_1P_CTRL, + offset =3D P_802_1P_CTRL; + if (ksz_is_ksz8463(dev)) + offset =3D P1CR2; + ksz_port_cfg(dev, port, offset, masks[PORT_802_1P_REMAPPING], false); =20 if (cpu_port) @@ -1904,7 +1940,7 @@ int ksz8_setup(struct dsa_switch *ds) =20 ksz_cfg(dev, S_MIRROR_CTRL, SW_MIRROR_RX_TX, false); =20 - if (!ksz_is_ksz88x3(dev)) + if (!ksz_is_ksz88x3(dev) && !ksz_is_ksz8463(dev)) ksz_cfg(dev, REG_SW_CTRL_19, SW_INS_TAG_ENABLE, true); =20 for (i =3D 0; i < (dev->info->num_vlans / 4); i++) diff --git a/drivers/net/dsa/microchip/ksz_common.c b/drivers/net/dsa/micro= chip/ksz_common.c index 095e647b3897..552c993b6519 100644 --- a/drivers/net/dsa/microchip/ksz_common.c +++ b/drivers/net/dsa/microchip/ksz_common.c @@ -2951,6 +2951,7 @@ static int ksz_parse_drive_strength(struct ksz_device= *dev); static int ksz_setup(struct dsa_switch *ds) { struct ksz_device *dev =3D ds->priv; + u16 storm_mask, storm_rate; struct dsa_port *dp; struct ksz_port *p; const u16 *regs; @@ -2980,10 +2981,14 @@ static int ksz_setup(struct dsa_switch *ds) } =20 /* set broadcast storm protection 10% rate */ + storm_mask =3D BROADCAST_STORM_RATE; + storm_rate =3D (BROADCAST_STORM_VALUE * BROADCAST_STORM_PROT_RATE) / 100; + if (ksz_is_ksz8463(dev)) { + storm_mask =3D swab16(storm_mask); + storm_rate =3D swab16(storm_rate); + } regmap_update_bits(ksz_regmap_16(dev), regs[S_BROADCAST_CTRL], - BROADCAST_STORM_RATE, - (BROADCAST_STORM_VALUE * - BROADCAST_STORM_PROT_RATE) / 100); + storm_mask, storm_rate); =20 dev->dev_ops->config_cpu_port(ds); =20 @@ -4221,6 +4226,17 @@ static int ksz_ets_band_to_queue(struct tc_ets_qopt_= offload_replace_params *p, return p->bands - 1 - band; } =20 +static u8 ksz8463_tc_ctrl(int port, int queue) +{ + u8 reg; + + reg =3D 0xC8 + port * 4; + reg +=3D ((3 - queue) / 2) * 2; + reg++; + reg -=3D (queue & 1); + return reg; +} + /** * ksz88x3_tc_ets_add - Configure ETS (Enhanced Transmission Selection) * for a port on KSZ88x3 switch @@ -4256,6 +4272,8 @@ static int ksz88x3_tc_ets_add(struct ksz_device *dev,= int port, * port/queue */ reg =3D KSZ8873_TXQ_SPLIT_CTRL_REG(port, queue); + if (ksz_is_ksz8463(dev)) + reg =3D ksz8463_tc_ctrl(port, queue); =20 /* Clear WFQ enable bit to select strict priority scheduling */ ret =3D ksz_rmw8(dev, reg, KSZ8873_TXQ_WFQ_ENABLE, 0); @@ -4291,6 +4309,8 @@ static int ksz88x3_tc_ets_del(struct ksz_device *dev,= int port) * port/queue */ reg =3D KSZ8873_TXQ_SPLIT_CTRL_REG(port, queue); + if (ksz_is_ksz8463(dev)) + reg =3D ksz8463_tc_ctrl(port, queue); =20 /* Set WFQ enable bit to revert back to default scheduling * mode @@ -4438,7 +4458,7 @@ static int ksz_tc_setup_qdisc_ets(struct dsa_switch *= ds, int port, struct ksz_device *dev =3D ds->priv; int ret; =20 - if (is_ksz8(dev) && !ksz_is_ksz88x3(dev)) + if (is_ksz8(dev) && !(ksz_is_ksz88x3(dev) || ksz_is_ksz8463(dev))) return -EOPNOTSUPP; =20 if (qopt->parent !=3D TC_H_ROOT) { @@ -4452,13 +4472,13 @@ static int ksz_tc_setup_qdisc_ets(struct dsa_switch= *ds, int port, if (ret) return ret; =20 - if (ksz_is_ksz88x3(dev)) + if (ksz_is_ksz88x3(dev) || ksz_is_ksz8463(dev)) return ksz88x3_tc_ets_add(dev, port, &qopt->replace_params); else return ksz_tc_ets_add(dev, port, &qopt->replace_params); case TC_ETS_DESTROY: - if (ksz_is_ksz88x3(dev)) + if (ksz_is_ksz88x3(dev) || ksz_is_ksz8463(dev)) return ksz88x3_tc_ets_del(dev, port); else return ksz_tc_ets_del(dev, port); diff --git a/drivers/net/dsa/microchip/ksz_dcb.c b/drivers/net/dsa/microchi= p/ksz_dcb.c index c3b501997ac9..7131c5caac54 100644 --- a/drivers/net/dsa/microchip/ksz_dcb.c +++ b/drivers/net/dsa/microchip/ksz_dcb.c @@ -16,10 +16,12 @@ * Therefore, we define the base offset as 0x00 here to align with that lo= gic. */ #define KSZ8_REG_PORT_1_CTRL_0 0x00 +#define KSZ8463_REG_PORT_1_CTRL_0 0x6C #define KSZ8_PORT_DIFFSERV_ENABLE BIT(6) #define KSZ8_PORT_802_1P_ENABLE BIT(5) #define KSZ8_PORT_BASED_PRIO_M GENMASK(4, 3) =20 +#define KSZ8463_REG_TOS_DSCP_CTRL 0x16 #define KSZ88X3_REG_TOS_DSCP_CTRL 0x60 #define KSZ8765_REG_TOS_DSCP_CTRL 0x90 =20 @@ -98,6 +100,8 @@ static void ksz_get_default_port_prio_reg(struct ksz_dev= ice *dev, int *reg, *reg =3D KSZ8_REG_PORT_1_CTRL_0; *mask =3D KSZ8_PORT_BASED_PRIO_M; *shift =3D __bf_shf(KSZ8_PORT_BASED_PRIO_M); + if (ksz_is_ksz8463(dev)) + *reg =3D KSZ8463_REG_PORT_1_CTRL_0; } else { *reg =3D KSZ9477_REG_PORT_MRI_MAC_CTRL; *mask =3D KSZ9477_PORT_BASED_PRIO_M; @@ -122,10 +126,12 @@ static void ksz_get_dscp_prio_reg(struct ksz_device *= dev, int *reg, *reg =3D KSZ8765_REG_TOS_DSCP_CTRL; *per_reg =3D 4; *mask =3D GENMASK(1, 0); - } else if (ksz_is_ksz88x3(dev)) { + } else if (ksz_is_ksz88x3(dev) || ksz_is_ksz8463(dev)) { *reg =3D KSZ88X3_REG_TOS_DSCP_CTRL; *per_reg =3D 4; *mask =3D GENMASK(1, 0); + if (ksz_is_ksz8463(dev)) + *reg =3D KSZ8463_REG_TOS_DSCP_CTRL; } else { *reg =3D KSZ9477_REG_DIFFSERV_PRIO_MAP; *per_reg =3D 2; @@ -151,6 +157,8 @@ static void ksz_get_apptrust_map_and_reg(struct ksz_dev= ice *dev, *map =3D ksz8_apptrust_map_to_bit; *reg =3D KSZ8_REG_PORT_1_CTRL_0; *mask =3D KSZ8_PORT_DIFFSERV_ENABLE | KSZ8_PORT_802_1P_ENABLE; + if (ksz_is_ksz8463(dev)) + *reg =3D KSZ8463_REG_PORT_1_CTRL_0; } else { *map =3D ksz9477_apptrust_map_to_bit; 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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Marek Vasut , , , , , Tristram Ha Subject: [PATCH net-next v5 4/6] net: dsa: microchip: Write switch MAC address differently for KSZ8463 Date: Tue, 22 Jul 2025 19:26:10 -0700 Message-ID: <20250723022612.38535-5-Tristram.Ha@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250723022612.38535-1-Tristram.Ha@microchip.com> References: <20250723022612.38535-1-Tristram.Ha@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Tristram Ha KSZ8463 uses 16-bit register definitions so it writes differently for 8-bit switch MAC address. Signed-off-by: Tristram Ha Reviewed-by: Andrew Lunn --- drivers/net/dsa/microchip/ksz_common.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/net/dsa/microchip/ksz_common.c b/drivers/net/dsa/micro= chip/ksz_common.c index 552c993b6519..e47c4a5aad6f 100644 --- a/drivers/net/dsa/microchip/ksz_common.c +++ b/drivers/net/dsa/microchip/ksz_common.c @@ -4821,7 +4821,16 @@ int ksz_switch_macaddr_get(struct dsa_switch *ds, in= t port, =20 /* Program the switch MAC address to hardware */ for (i =3D 0; i < ETH_ALEN; i++) { - ret =3D ksz_write8(dev, regs[REG_SW_MAC_ADDR] + i, addr[i]); + if (ksz_is_ksz8463(dev)) { + u16 addr16 =3D ((u16)addr[i] << 8) | addr[i + 1]; + + ret =3D ksz_write16(dev, regs[REG_SW_MAC_ADDR] + i, + addr16); + i++; + } else { + ret =3D ksz_write8(dev, regs[REG_SW_MAC_ADDR] + i, + addr[i]); + } if (ret) goto macaddr_drop; } --=20 2.34.1 From nobody Mon Oct 6 08:24:27 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E5A581F099C; Wed, 23 Jul 2025 02:26:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753237609; cv=none; b=pi6uC3piPG2fWgnjtwhdQYpmhvUyEPB8+2zYYAk9l9iXY01HeFjmzqb6P6eQaqqtfTQMN73FNibD+TLURlgCe6A9TtS3GueMyXmDmR8ITcC87Gj53Q+UTyVOlKdnMF0a3CqMRDhzcaT3JRfkjXuXU0ecI48n5AvJFahV4jMequI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753237609; c=relaxed/simple; bh=79Wgk5IW5Uc8vPPB58ide3VHHikd+vcI72rhK/lnzFo=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=qF4lQ068dal1zlCHlkPY3m32FjZ5s3p7F7zCTsg5eH3ciYh2ozMUF8F9f8V24ut0omPFhJejwavRhffdPuaWjsoYcTpttu6MtrzhKc8Fa4qIu6ti0FBBKH97RmeIxpij1jt2LDcVz3+Ew8gfcRx+xgPdlMr7rjhok8nsowRW7Q0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=f5hC/fl0; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="f5hC/fl0" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1753237608; x=1784773608; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=79Wgk5IW5Uc8vPPB58ide3VHHikd+vcI72rhK/lnzFo=; b=f5hC/fl0o620tVp4QypFnjnTWkbVoFRb9Bqk53tdqJVcjY2uS5AqplDJ QcaUZaQwuNKzIgiMlyN5SZ8fH9zru/xAGAfubJYiwjXO2CCRS0rnjBqUs gESdOS4Ab00Kwo9b/5/WMCiWvd3407yJdz1itjFsAyzT0cXdtORegcwZX vGQ0UvWrIH3L71Sem0evCLo9KUZc+eDl45UhoVdQy5yyajVCQUyehC49I gWcurHNfsVvVZhy9CyPp6c0r60NMNoTM9QS0dRLb3xzzcfNz46MXkBsWS YdpW0JUaqZ8To0AoBYbRW0Fojy3iRE7Je04H+aX35M4gfaEzcDJi1VM3q g==; X-CSE-ConnectionGUID: ol8zE+5pQbyz8nKT026TwA== X-CSE-MsgGUID: Yi0SYItcTfKusgzYP8TsBw== X-IronPort-AV: E=Sophos;i="6.16,333,1744095600"; d="scan'208";a="275694688" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa5.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 22 Jul 2025 19:26:39 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.87.72) by chn-vm-ex02.mchp-main.com (10.10.87.72) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.44; Tue, 22 Jul 2025 19:26:16 -0700 Received: from pop-os.microchip.com (10.10.85.11) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.44 via Frontend Transport; Tue, 22 Jul 2025 19:26:16 -0700 From: To: Woojung Huh , Andrew Lunn , Vladimir Oltean , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley CC: Maxime Chevallier , Simon Horman , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Marek Vasut , , , , , Tristram Ha Subject: [PATCH net-next v5 5/6] net: dsa: microchip: Setup fiber ports for KSZ8463 Date: Tue, 22 Jul 2025 19:26:11 -0700 Message-ID: <20250723022612.38535-6-Tristram.Ha@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250723022612.38535-1-Tristram.Ha@microchip.com> References: <20250723022612.38535-1-Tristram.Ha@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Tristram Ha The fiber ports in KSZ8463 cannot be detected internally, so it requires specifying that condition in the device tree. Like the one used in Micrel PHY the port link can only be read and there is no write to the PHY. The driver programs registers to operate fiber ports correctly. Signed-off-by: Tristram Ha --- v3 - Disable PTP function in a separate patch drivers/net/dsa/microchip/ksz8.c | 16 ++++++++++++++++ drivers/net/dsa/microchip/ksz_common.c | 3 +++ 2 files changed, 19 insertions(+) diff --git a/drivers/net/dsa/microchip/ksz8.c b/drivers/net/dsa/microchip/k= sz8.c index 55c1460b8b2e..62224426a9bd 100644 --- a/drivers/net/dsa/microchip/ksz8.c +++ b/drivers/net/dsa/microchip/ksz8.c @@ -1714,6 +1714,7 @@ void ksz8_config_cpu_port(struct dsa_switch *ds) const u32 *masks; const u16 *regs; u8 remote; + u8 fiber_ports =3D 0; int i; =20 masks =3D dev->info->masks; @@ -1744,6 +1745,21 @@ void ksz8_config_cpu_port(struct dsa_switch *ds) else ksz_port_cfg(dev, i, regs[P_STP_CTRL], PORT_FORCE_FLOW_CTRL, false); + if (p->fiber) + fiber_ports |=3D (1 << i); + } + if (ksz_is_ksz8463(dev)) { + /* Setup fiber ports. */ + if (fiber_ports) { + fiber_ports &=3D 3; + regmap_update_bits(ksz_regmap_16(dev), + KSZ8463_REG_CFG_CTRL, + fiber_ports << PORT_COPPER_MODE_S, + 0); + regmap_update_bits(ksz_regmap_16(dev), + KSZ8463_REG_DSP_CTRL_6, + COPPER_RECEIVE_ADJUSTMENT, 0); + } } } =20 diff --git a/drivers/net/dsa/microchip/ksz_common.c b/drivers/net/dsa/micro= chip/ksz_common.c index e47c4a5aad6f..7292bfe2f7ca 100644 --- a/drivers/net/dsa/microchip/ksz_common.c +++ b/drivers/net/dsa/microchip/ksz_common.c @@ -5439,6 +5439,9 @@ int ksz_switch_register(struct ksz_device *dev) &dev->ports[port_num].interface); =20 ksz_parse_rgmii_delay(dev, port_num, port); + dev->ports[port_num].fiber =3D + of_property_read_bool(port, + "micrel,fiber-mode"); } of_node_put(ports); } --=20 2.34.1 From nobody Mon Oct 6 08:24:27 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BA9BD1F461A; Wed, 23 Jul 2025 02:26:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753237610; cv=none; b=DiyQEGkme9gvgvJ2CQrO8bjtx1rCFsO+LFH9dIv/WW5ZMoftTiNct+aC62GztWEYEiDpV8KQAlX2Rx+OO0lg/powdySyq92yVYLtdtajPrGgqVFSowcOXFkFhORvce7KlLiS13vtO6uWYaCnX0bfZ04MbjH8yohQnAs399N/kTQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753237610; c=relaxed/simple; bh=KV62NoXC9aWiyFqUrd583Tuwhbt7qTYtiziCYEan+zg=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=P7yQ2R0M0FVAzzH4GeK6GBQZIbJpjSr3Bu2JnY0+15Bi+iMkMl1UT7xcIAoxs5ClrmjcZJeLEF3QT8pLBkO/ckXlD/4OIm5eeVTM9dDX7nuPJo6yUqXKEuIyYme6juL1LWzqcflm/BCljPJA/pRxMUCw7DyRrbMVW9Dmvrk74B8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=R2bBWHZ4; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="R2bBWHZ4" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1753237609; x=1784773609; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=KV62NoXC9aWiyFqUrd583Tuwhbt7qTYtiziCYEan+zg=; b=R2bBWHZ4sBaSIZ9xdbwQ9OsDDzKpwELCTGoPQgYY6qwC063Wtm5c439M 9dlAxPfOaO/+oNlWdaglQ+Y+uTf71zCH8zze9q5vmd4hzuQChr2kRNjOn q8U1kH12kPJ6OHqhBO1uE3ykq24mWut++k1VwHwDXhvaChfMg1s5rvr+X ERUeQzcYI07FDKCUDld4w/ny1VqOO5d7llvbvYs+wj8B+C9CR06BAUY3k 6FF4PP5GML+5q5mruvoeamKwkOgJ15LTs2RPoIA1nbsrm6p+CoACJ3HZi DNcPyrJTLOUg6V3CMwQBO3ecHTrgM4gs8/EwLc8Xl/emzOlGcMAYEWwxt Q==; X-CSE-ConnectionGUID: ol8zE+5pQbyz8nKT026TwA== X-CSE-MsgGUID: k7HcpH0dTvu2Xe51WtW5JQ== X-IronPort-AV: E=Sophos;i="6.16,333,1744095600"; d="scan'208";a="275694689" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa5.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 22 Jul 2025 19:26:39 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.87.72) by chn-vm-ex02.mchp-main.com (10.10.87.72) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.44; Tue, 22 Jul 2025 19:26:17 -0700 Received: from pop-os.microchip.com (10.10.85.11) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.44 via Frontend Transport; Tue, 22 Jul 2025 19:26:16 -0700 From: To: Woojung Huh , Andrew Lunn , Vladimir Oltean , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley CC: Maxime Chevallier , Simon Horman , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Marek Vasut , , , , , Tristram Ha Subject: [PATCH net-next v5 6/6] net: dsa: microchip: Disable PTP function of KSZ8463 Date: Tue, 22 Jul 2025 19:26:12 -0700 Message-ID: <20250723022612.38535-7-Tristram.Ha@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250723022612.38535-1-Tristram.Ha@microchip.com> References: <20250723022612.38535-1-Tristram.Ha@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Tristram Ha The PTP function of KSZ8463 is on by default. However, its proprietary way of storing timestamp directly in a reserved field inside the PTP message header is not suitable for use with the current Linux PTP stack implementation. It is necessary to disable the PTP function to not interfere the normal operation of the MAC. Note the PTP driver for KSZ switches does not work for KSZ8463 and is not activated for it. Signed-off-by: Tristram Ha --- drivers/net/dsa/microchip/ksz8.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/net/dsa/microchip/ksz8.c b/drivers/net/dsa/microchip/k= sz8.c index 62224426a9bd..c400e1c0369e 100644 --- a/drivers/net/dsa/microchip/ksz8.c +++ b/drivers/net/dsa/microchip/ksz8.c @@ -1760,6 +1760,17 @@ void ksz8_config_cpu_port(struct dsa_switch *ds) KSZ8463_REG_DSP_CTRL_6, COPPER_RECEIVE_ADJUSTMENT, 0); } + + /* Turn off PTP function as the switch's proprietary way of + * handling timestamp is not supported in current Linux PTP + * stack implementation. + */ + regmap_update_bits(ksz_regmap_16(dev), + KSZ8463_PTP_MSG_CONF1, + PTP_ENABLE, 0); + regmap_update_bits(ksz_regmap_16(dev), + KSZ8463_PTP_CLK_CTRL, + PTP_CLK_ENABLE, 0); } } =20 --=20 2.34.1