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charset="utf-8" Add optional device tree properties to limit Tx/Rx gear and rate during UFS initialization. Parse these properties in ufs_qcom_init() and apply them to host->host_params to enforce platform-specific constraints. Use this mechanism to cap the maximum gear or rate on platforms with hardware limitations, such as those required by some automotive customers using SA8155. Preserve the default behavior if the properties are not specified in the device tree. Signed-off-by: Ram Kumar Dwivedi --- drivers/ufs/host/ufs-qcom.c | 28 ++++++++++++++++++++++------ 1 file changed, 22 insertions(+), 6 deletions(-) diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c index 4bbe4de1679b..5e7fd3257aca 100644 --- a/drivers/ufs/host/ufs-qcom.c +++ b/drivers/ufs/host/ufs-qcom.c @@ -494,12 +494,8 @@ static int ufs_qcom_power_up_sequence(struct ufs_hba *= hba) * If the HS-G5 PHY gear is used, update host_params->hs_rate to Rate-A, * so that the subsequent power mode change shall stick to Rate-A. */ - if (host->hw_ver.major =3D=3D 0x5) { - if (host->phy_gear =3D=3D UFS_HS_G5) - host_params->hs_rate =3D PA_HS_MODE_A; - else - host_params->hs_rate =3D PA_HS_MODE_B; - } + if (host->hw_ver.major =3D=3D 0x5 && host->phy_gear =3D=3D UFS_HS_G5) + host_params->hs_rate =3D PA_HS_MODE_A; =20 mode =3D host_params->hs_rate =3D=3D PA_HS_MODE_B ? PHY_MODE_UFS_HS_B : P= HY_MODE_UFS_HS_A; =20 @@ -1096,6 +1092,25 @@ static void ufs_qcom_set_phy_gear(struct ufs_qcom_ho= st *host) } } =20 +static void ufs_qcom_parse_limits(struct ufs_qcom_host *host) +{ + struct ufs_host_params *host_params =3D &host->host_params; + struct device_node *np =3D host->hba->dev->of_node; + u32 hs_gear, hs_rate =3D 0; + + if (!np) + return; + + if (!of_property_read_u32(np, "limit-hs-gear", &hs_gear)) { + host_params->hs_tx_gear =3D hs_gear; + host_params->hs_rx_gear =3D hs_gear; + host->phy_gear =3D hs_gear; + } + + if (!of_property_read_u32(np, "limit-rate", &hs_rate)) + host_params->hs_rate =3D hs_rate; +} + static void ufs_qcom_set_host_params(struct ufs_hba *hba) { struct ufs_qcom_host *host =3D ufshcd_get_variant(hba); @@ -1337,6 +1352,7 @@ static int ufs_qcom_init(struct ufs_hba *hba) ufs_qcom_advertise_quirks(hba); ufs_qcom_set_host_params(hba); ufs_qcom_set_phy_gear(host); + ufs_qcom_parse_limits(host); =20 err =3D ufs_qcom_ice_init(host); if (err) --=20 2.50.1 From nobody Mon Oct 6 10:18:48 2025 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BE5F0246764; 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charset="utf-8" Add optional limit-hs-gear and limit-rate properties to the UFS node to support automotive use cases that require limiting the maximum Tx/Rx HS gear and rate due to hardware constraints. Signed-off-by: Ram Kumar Dwivedi --- arch/arm64/boot/dts/qcom/sm8150.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qco= m/sm8150.dtsi index b5494bcf5cff..87e8b60b3b2d 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -2082,6 +2082,9 @@ ufs_mem_hc: ufshc@1d84000 { resets =3D <&gcc GCC_UFS_PHY_BCR>; reset-names =3D "rst"; =20 + limit-hs-gear =3D <3>; + limit-rate =3D <1>; + iommus =3D <&apps_smmu 0x300 0>; =20 clock-names =3D --=20 2.50.1 From nobody Mon Oct 6 10:18:48 2025 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C1CE427BF80; Tue, 22 Jul 2025 16:11:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; 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charset="utf-8" Add documentation for two new optional properties: - limit-hs-gear - limit-rate These properties allow platforms to restrict the maximum high-speed gear and rate used by the UFS controller. This is required for certain automotive platforms with hardware constraints. Signed-off-by: Ram Kumar Dwivedi --- Documentation/devicetree/bindings/ufs/qcom,ufs.yaml | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml b/Document= ation/devicetree/bindings/ufs/qcom,ufs.yaml index 6c6043d9809e..9dedd09df9e0 100644 --- a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml +++ b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml @@ -111,6 +111,16 @@ properties: description: GPIO connected to the RESET pin of the UFS memory device. =20 + limit-hs-gear: + maxItems: 1 + description: + Limit max phy hs gear + + limit-rate: + maxItems: 1 + description: + Limit max phy hs rate + required: - compatible - reg --=20 2.50.1