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Tue, 22 Jul 2025 09:09:53 -0700 (PDT) Received: from localhost ([2a02:8308:a00c:e200:30d6:4986:8040:bb0a]) by smtp.gmail.com with UTF8SMTPSA id ffacd0b85a97d-3b61ca25533sm13602031f8f.11.2025.07.22.09.09.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Jul 2025 09:09:52 -0700 (PDT) From: =?UTF-8?q?Radim=20Kr=C4=8Dm=C3=A1=C5=99?= To: linux-riscv@lists.infradead.org Cc: linux-kernel@vger.kernel.org, Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Deepak Gupta Subject: [PATCH 1/3] riscv: use TASK_TI_CPU instead of TASK_TI_CPU_NUM Date: Tue, 22 Jul 2025 18:05:55 +0200 Message-ID: <20250722160556.2216925-3-rkrcmar@ventanamicro.com> X-Mailer: git-send-email 2.50.0 In-Reply-To: <20250722160556.2216925-2-rkrcmar@ventanamicro.com> References: <20250722160556.2216925-2-rkrcmar@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The offsets of TASK_TI_CPU and TASK_TI_CPU_NUM are identical, and TASK_TI_CPU is a better name for thread_info.cpu. Signed-off-by: Radim Kr=C4=8Dm=C3=A1=C5=99 Reviewed-by: Alexandre Ghiti --- arch/riscv/include/asm/asm.h | 2 +- arch/riscv/kernel/asm-offsets.c | 1 - 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/riscv/include/asm/asm.h b/arch/riscv/include/asm/asm.h index a8a2af6dfe9d..b3022bc224ec 100644 --- a/arch/riscv/include/asm/asm.h +++ b/arch/riscv/include/asm/asm.h @@ -91,7 +91,7 @@ #endif =20 .macro asm_per_cpu dst sym tmp - REG_L \tmp, TASK_TI_CPU_NUM(tp) + REG_L \tmp, TASK_TI_CPU(tp) slli \tmp, \tmp, PER_CPU_OFFSET_SHIFT la \dst, __per_cpu_offset add \dst, \dst, \tmp diff --git a/arch/riscv/kernel/asm-offsets.c b/arch/riscv/kernel/asm-offset= s.c index 6e8c0d6feae9..49cf2c347485 100644 --- a/arch/riscv/kernel/asm-offsets.c +++ b/arch/riscv/kernel/asm-offsets.c @@ -49,7 +49,6 @@ void asm_offsets(void) OFFSET(TASK_TI_A2, task_struct, thread_info.a2); #endif =20 - OFFSET(TASK_TI_CPU_NUM, task_struct, thread_info.cpu); OFFSET(TASK_THREAD_F0, task_struct, thread.fstate.f[0]); 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Tue, 22 Jul 2025 09:09:54 -0700 (PDT) Received: from localhost ([2a02:8308:a00c:e200:30d6:4986:8040:bb0a]) by smtp.gmail.com with UTF8SMTPSA id ffacd0b85a97d-3b61ca4c754sm13900391f8f.59.2025.07.22.09.09.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Jul 2025 09:09:53 -0700 (PDT) From: =?UTF-8?q?Radim=20Kr=C4=8Dm=C3=A1=C5=99?= To: linux-riscv@lists.infradead.org Cc: linux-kernel@vger.kernel.org, Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Deepak Gupta Subject: [PATCH 2/3] riscv: use lw instead of REG_L when reading int cpu Date: Tue, 22 Jul 2025 18:05:56 +0200 Message-ID: <20250722160556.2216925-4-rkrcmar@ventanamicro.com> X-Mailer: git-send-email 2.50.0 In-Reply-To: <20250722160556.2216925-2-rkrcmar@ventanamicro.com> References: <20250722160556.2216925-2-rkrcmar@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable REG_L is wrong, because thread_info.cpu is 32-bit, not xlen-bit wide. The struct currently has a hole after cpu, so little endian accesses seemed fine. Fixes: be97d0db5f44 ("riscv: VMAP_STACK overflow detection thread-safe") Fixes: 503638e0babf ("riscv: Stop emitting preventive sfence.vma for new vm= alloc mappings") Signed-off-by: Radim Kr=C4=8Dm=C3=A1=C5=99 Reviewed-by: Alexandre Ghiti --- arch/riscv/include/asm/asm.h | 2 +- arch/riscv/kernel/entry.S | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/riscv/include/asm/asm.h b/arch/riscv/include/asm/asm.h index b3022bc224ec..93b1e4ce34d1 100644 --- a/arch/riscv/include/asm/asm.h +++ b/arch/riscv/include/asm/asm.h @@ -91,7 +91,7 @@ #endif =20 .macro asm_per_cpu dst sym tmp - REG_L \tmp, TASK_TI_CPU(tp) + lw \tmp, TASK_TI_CPU(tp) slli \tmp, \tmp, PER_CPU_OFFSET_SHIFT la \dst, __per_cpu_offset add \dst, \dst, \tmp diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S index 75656afa2d6b..4fdf187a62bf 100644 --- a/arch/riscv/kernel/entry.S +++ b/arch/riscv/kernel/entry.S @@ -46,7 +46,7 @@ * a0 =3D &new_vmalloc[BIT_WORD(cpu)] * a1 =3D BIT_MASK(cpu) */ - REG_L a2, TASK_TI_CPU(tp) + lw a2, TASK_TI_CPU(tp) /* * Compute the new_vmalloc element position: * (cpu / 64) * 8 =3D (cpu >> 6) << 3 --=20 2.50.0 From nobody Mon Oct 6 10:16:11 2025 Received: from mail-wm1-f48.google.com (mail-wm1-f48.google.com [209.85.128.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 10D3827A915 for ; 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Tue, 22 Jul 2025 09:09:56 -0700 (PDT) Received: from localhost ([2a02:8308:a00c:e200:30d6:4986:8040:bb0a]) by smtp.gmail.com with UTF8SMTPSA id 5b1f17b1804b1-458639ffca5sm19058775e9.1.2025.07.22.09.09.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Jul 2025 09:09:55 -0700 (PDT) From: =?UTF-8?q?Radim=20Kr=C4=8Dm=C3=A1=C5=99?= To: linux-riscv@lists.infradead.org Cc: linux-kernel@vger.kernel.org, Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Deepak Gupta Subject: [PATCH 3/3] riscv: pack rv64 thread_info better Date: Tue, 22 Jul 2025 18:05:57 +0200 Message-ID: <20250722160556.2216925-5-rkrcmar@ventanamicro.com> X-Mailer: git-send-email 2.50.0 In-Reply-To: <20250722160556.2216925-2-rkrcmar@ventanamicro.com> References: <20250722160556.2216925-2-rkrcmar@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable On rv64, preempt_count and cpu were both 32-bit followed by 64-bit, so placing one in the hole saves 8 bytes in the struct. Signed-off-by: Radim Kr=C4=8Dm=C3=A1=C5=99 Reviewed-by: Alexandre Ghiti Tested-by: Alexandre Ghiti --- arch/riscv/include/asm/thread_info.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/include/asm/thread_info.h b/arch/riscv/include/asm/= thread_info.h index f5916a70879a..c267d6bd838e 100644 --- a/arch/riscv/include/asm/thread_info.h +++ b/arch/riscv/include/asm/thread_info.h @@ -53,6 +53,7 @@ struct thread_info { unsigned long flags; /* low level flags */ int preempt_count; /* 0=3D>preemptible, <0=3D>BUG */ + int cpu; /* * These stack pointers are overwritten on every system call or * exception. SP is also saved to the stack it can be recovered when @@ -60,7 +61,6 @@ struct thread_info { */ long kernel_sp; /* Kernel stack pointer */ long user_sp; /* User stack pointer */ - int cpu; unsigned long syscall_work; /* SYSCALL_WORK_ flags */ #ifdef CONFIG_SHADOW_CALL_STACK void *scs_base; --=20 2.50.0