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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Jul 2025 15:41:24.8559 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 955faad6-5299-4401-7933-08ddc9363750 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: MWH0EPF000A672F.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV8PR12MB9083 Content-Type: text/plain; charset="utf-8" Add Enhanced Network Scheduling and Timing (ENST) support to queue infrastructure with speed-dependent timing calculations for precise gate control. Hardware timing unit conversion: - Timing values programmed as hardware units based on link speed - Conversion formula: time_bytes =3D time_ns / divisor - Speed-specific divisors: * 1 Gbps: divisor =3D 8 * 100 Mbps: divisor =3D 80 * 10 Mbps: divisor =3D 800 Infrastructure changes: - Extend macb_queue structure with ENST timing control registers - Add queue_enst_configs structure for per-entry TC configuration storage - Map ENST register offsets into existing queue management framework - Define ENST_NS_TO_HW_UNITS() macro for automatic speed-based conversion This enables hardware-native timing programming while abstracting the speed-dependent conversions Signed-off-by: Vineeth Karumanchi --- drivers/net/ethernet/cadence/macb.h | 32 ++++++++++++++++++++++++ drivers/net/ethernet/cadence/macb_main.c | 6 +++++ 2 files changed, 38 insertions(+) diff --git a/drivers/net/ethernet/cadence/macb.h b/drivers/net/ethernet/cad= ence/macb.h index e456ac65d6c6..ef3995564c5c 100644 --- a/drivers/net/ethernet/cadence/macb.h +++ b/drivers/net/ethernet/cadence/macb.h @@ -857,6 +857,16 @@ =20 #define MACB_READ_NSR(bp) macb_readl(bp, NSR) =20 +/* ENST macros*/ +#define ENST_NS_TO_HW_UNITS(ns, speed_mbps) \ + DIV_ROUND_UP((ns) * (speed_mbps), (ENST_TIME_GRANULARITY_NS * 1000)) + +#define ENST_MAX_HW_INTERVAL(speed_mbps) \ + DIV_ROUND_UP(GENMASK(GEM_ON_TIME_SIZE - 1, 0) * ENST_TIME_GRANULARITY_NS= * 1000,\ + (speed_mbps)) + +#define ENST_MAX_START_TIME_SEC GENMASK(GEM_START_TIME_SEC_SIZE - 1, 0) + /* struct macb_dma_desc - Hardware DMA descriptor * @addr: DMA address of data buffer * @ctrl: Control and status bits @@ -1262,6 +1272,11 @@ struct macb_queue { unsigned int RBQP; unsigned int RBQPH; =20 + /* ENST register offsets for this queue */ + unsigned int ENST_START_TIME; + unsigned int ENST_ON_TIME; + unsigned int ENST_OFF_TIME; + /* Lock to protect tx_head and tx_tail */ spinlock_t tx_ptr_lock; unsigned int tx_head, tx_tail; @@ -1450,4 +1465,21 @@ struct macb_platform_data { struct clk *hclk; }; =20 +/** + * struct queue_enst_configs - Configuration for Enhanced Scheduled Traffi= c (ENST) queue + * @queue_id: Identifier for the queue + * @start_time_mask: Bitmask representing the start time for the queue + * @on_time_bytes: "on" time nsec expressed in bytes + * @off_time_bytes: "off" time nsec expressed in bytes + * + * This structure holds the configuration parameters for an ENST queue, + * used to control time-based transmission scheduling in the MACB driver. + */ +struct queue_enst_configs { + u8 queue_id; + u32 start_time_mask; + u32 on_time_bytes; + u32 off_time_bytes; +}; + #endif /* _MACB_H */ diff --git a/drivers/net/ethernet/cadence/macb_main.c b/drivers/net/etherne= t/cadence/macb_main.c index ce95fad8cedd..ff87d3e1d8a0 100644 --- a/drivers/net/ethernet/cadence/macb_main.c +++ b/drivers/net/ethernet/cadence/macb_main.c @@ -4305,6 +4305,9 @@ static int macb_init(struct platform_device *pdev) queue->TBQP =3D GEM_TBQP(hw_q - 1); queue->RBQP =3D GEM_RBQP(hw_q - 1); queue->RBQS =3D GEM_RBQS(hw_q - 1); + queue->ENST_START_TIME =3D GEM_ENST_START_TIME(hw_q); + queue->ENST_ON_TIME =3D GEM_ENST_ON_TIME(hw_q); + queue->ENST_OFF_TIME =3D GEM_ENST_OFF_TIME(hw_q); #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT if (bp->hw_dma_cap & HW_DMA_CAP_64B) { queue->TBQPH =3D GEM_TBQPH(hw_q - 1); @@ -4319,6 +4322,9 @@ static int macb_init(struct platform_device *pdev) queue->IMR =3D MACB_IMR; queue->TBQP =3D MACB_TBQP; queue->RBQP =3D MACB_RBQP; + queue->ENST_START_TIME =3D GEM_ENST_START_TIME(0); + queue->ENST_ON_TIME =3D GEM_ENST_ON_TIME(0); + queue->ENST_OFF_TIME =3D GEM_ENST_OFF_TIME(0); #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT if (bp->hw_dma_cap & HW_DMA_CAP_64B) { queue->TBQPH =3D MACB_TBQPH; --=20 2.34.1