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charset="utf-8" SA8775P, QCS9100 and QCS9075 are all variants of the same die, collectively referred to as lemans. Most notably, the last of them has the SAIL (Safety Island) fused off, but remains identical otherwise. In an effort to streamline the codebase, rename the SoC DTSI, moving away from less meaningful numerical model identifiers. Signed-off-by: Wasim Nazir Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/{sa8775p.dtsi =3D> lemans.dtsi} | 0 arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi | 2 +- 2 files changed, 1 insertion(+), 1 deletion(-) rename arch/arm64/boot/dts/qcom/{sa8775p.dtsi =3D> lemans.dtsi} (100%) diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qc= om/lemans.dtsi similarity index 100% rename from arch/arm64/boot/dts/qcom/sa8775p.dtsi rename to arch/arm64/boot/dts/qcom/lemans.dtsi diff --git a/arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi b/arch/arm64/boot/d= ts/qcom/sa8775p-ride.dtsi index 63b3031cfcc1..bcd284c0f939 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi @@ -8,7 +8,7 @@ #include #include -#include "sa8775p.dtsi" +#include "lemans.dtsi" #include "sa8775p-pmics.dtsi" / { -- 2.49.0 From nobody Mon Oct 6 10:17:31 2025 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C46B32EBDF6; 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charset="utf-8" Stop using the outdated automotive memory map for Lemans; update it to meet IoT requirements. Since, most platforms are IoT-based, treat IoT as the default variant under "lemans" and apply it to all platforms, except those requiring the old memory-map (e.g., sa8775p, ride, and ride-r3). Introduce "lemans-auto" as a derivative of "lemans" that retains the old automotive memory map to support legacy use cases. As part of the IoT memory map updates: - Introduce new carveouts for gunyah_md and pil_dtb. Adjust the size and base address of the PIL carveout to accommodate these changes. - Increase the size of the video/camera PIL carveout without affecting existing functionality. - Reduce the size of the trusted apps carveout to meet IoT-specific requirements. - Remove audio_mdf_mem, tz_ffi_mem, and their corresponding SCM reference= s, as they are not required for IoT platforms. Co-developed-by: Pratyush Brahma Signed-off-by: Pratyush Brahma Co-developed-by: Prakash Gupta Signed-off-by: Prakash Gupta Signed-off-by: Wasim Nazir --- arch/arm64/boot/dts/qcom/lemans-auto.dtsi | 104 +++++++++++++++++++++ arch/arm64/boot/dts/qcom/lemans.dtsi | 75 +++++++++------ arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi | 2 +- 3 files changed, 149 insertions(+), 32 deletions(-) create mode 100644 arch/arm64/boot/dts/qcom/lemans-auto.dtsi diff --git a/arch/arm64/boot/dts/qcom/lemans-auto.dtsi b/arch/arm64/boot/dt= s/qcom/lemans-auto.dtsi new file mode 100644 index 000000000000..8db958d60fd1 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/lemans-auto.dtsi @@ -0,0 +1,104 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023, Linaro Limited + */ + +/dts-v1/; + +#include "lemans.dtsi" + +/delete-node/ &pil_camera_mem; +/delete-node/ &pil_adsp_mem; +/delete-node/ &q6_adsp_dtb_mem; +/delete-node/ &q6_gdsp0_dtb_mem; +/delete-node/ &pil_gdsp0_mem; +/delete-node/ &pil_gdsp1_mem; +/delete-node/ &q6_gdsp1_dtb_mem; +/delete-node/ &q6_cdsp0_dtb_mem; +/delete-node/ &pil_cdsp0_mem; +/delete-node/ &pil_gpu_mem; +/delete-node/ &pil_cdsp1_mem; +/delete-node/ &q6_cdsp1_dtb_mem; +/delete-node/ &pil_cvp_mem; +/delete-node/ &pil_video_mem; +/delete-node/ &gunyah_md_mem; + +/ { + reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + tz_ffi_mem: tz-ffi@91c00000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x0 0x91c00000 0x0 0x1400000>; + no-map; + }; + + pil_camera_mem: pil-camera@95200000 { + reg =3D <0x0 0x95200000 0x0 0x500000>; + no-map; + }; + + pil_adsp_mem: pil-adsp@95c00000 { + reg =3D <0x0 0x95c00000 0x0 0x1e00000>; + no-map; + }; + + pil_gdsp0_mem: pil-gdsp0@97b00000 { + reg =3D <0x0 0x97b00000 0x0 0x1e00000>; + no-map; + }; + + pil_gdsp1_mem: pil-gdsp1@99900000 { + reg =3D <0x0 0x99900000 0x0 0x1e00000>; + no-map; + }; + + pil_cdsp0_mem: pil-cdsp0@9b800000 { + reg =3D <0x0 0x9b800000 0x0 0x1e00000>; + no-map; + }; + + pil_gpu_mem: pil-gpu@9d600000 { + reg =3D <0x0 0x9d600000 0x0 0x2000>; + no-map; + }; + + pil_cdsp1_mem: pil-cdsp1@9d700000 { + reg =3D <0x0 0x9d700000 0x0 0x1e00000>; + no-map; + }; + + pil_cvp_mem: pil-cvp@9f500000 { + reg =3D <0x0 0x9f500000 0x0 0x700000>; + no-map; + }; + + pil_video_mem: pil-video@9fc00000 { + reg =3D <0x0 0x9fc00000 0x0 0x700000>; + no-map; + }; + + audio_mdf_mem: audio-mdf-region@ae000000 { + reg =3D <0x0 0xae000000 0x0 0x1000000>; + no-map; + }; + + hyptz_reserved_mem: hyptz-reserved@beb00000 { + reg =3D <0x0 0xbeb00000 0x0 0x11500000>; + no-map; + }; + + trusted_apps_mem: trusted-apps@d1900000 { + reg =3D <0x0 0xd1900000 0x0 0x3800000>; + no-map; + }; + }; + + firmware { + scm { + memory-region =3D <&tz_ffi_mem>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qco= m/lemans.dtsi index 9997a29901f5..bf273660e0cb 100644 --- a/arch/arm64/boot/dts/qcom/lemans.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi @@ -514,7 +514,6 @@ firmware { scm { compatible =3D "qcom,scm-sa8775p", "qcom,scm"; qcom,dload-mode =3D <&tcsr 0x13000>; - memory-region =3D <&tz_ffi_mem>; }; }; @@ -773,6 +772,11 @@ sail_ota_mem: sail-ss@90e00000 { no-map; }; + gunyah_md_mem: gunyah-md@91a80000 { + reg =3D <0x0 0x91a80000 0x0 0x80000>; + no-map; + }; + aoss_backup_mem: aoss-backup@91b00000 { reg =3D <0x0 0x91b00000 0x0 0x40000>; no-map; @@ -798,12 +802,6 @@ cdt_data_backup_mem: cdt-data-backup@91ba0000 { no-map; }; - tz_ffi_mem: tz-ffi@91c00000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x0 0x91c00000 0x0 0x1400000>; - no-map; - }; - lpass_machine_learning_mem: lpass-machine-learning@93b00000 { reg =3D <0x0 0x93b00000 0x0 0xf00000>; no-map; @@ -815,62 +813,77 @@ adsp_rpc_remote_heap_mem: adsp-rpc-remote-heap@94a000= 00 { }; pil_camera_mem: pil-camera@95200000 { - reg =3D <0x0 0x95200000 0x0 0x500000>; + reg =3D <0x0 0x95200000 0x0 0x700000>; no-map; }; - pil_adsp_mem: pil-adsp@95c00000 { - reg =3D <0x0 0x95c00000 0x0 0x1e00000>; + pil_adsp_mem: pil-adsp@95900000 { + reg =3D <0x0 0x95900000 0x0 0x1e00000>; no-map; }; - pil_gdsp0_mem: pil-gdsp0@97b00000 { - reg =3D <0x0 0x97b00000 0x0 0x1e00000>; + q6_adsp_dtb_mem: q6-adsp-dtb@97700000 { + reg =3D <0x0 0x97700000 0x0 0x80000>; no-map; }; - pil_gdsp1_mem: pil-gdsp1@99900000 { - reg =3D <0x0 0x99900000 0x0 0x1e00000>; + q6_gdsp0_dtb_mem: q6-gdsp0-dtb@97780000 { + reg =3D <0x0 0x97780000 0x0 0x80000>; no-map; }; - pil_cdsp0_mem: pil-cdsp0@9b800000 { - reg =3D <0x0 0x9b800000 0x0 0x1e00000>; + pil_gdsp0_mem: pil-gdsp0@97800000 { + reg =3D <0x0 0x97800000 0x0 0x1e00000>; no-map; }; - pil_gpu_mem: pil-gpu@9d600000 { - reg =3D <0x0 0x9d600000 0x0 0x2000>; + pil_gdsp1_mem: pil-gdsp1@99600000 { + reg =3D <0x0 0x99600000 0x0 0x1e00000>; no-map; }; - pil_cdsp1_mem: pil-cdsp1@9d700000 { - reg =3D <0x0 0x9d700000 0x0 0x1e00000>; + q6_gdsp1_dtb_mem: q6-gdsp1-dtb@9b400000 { + reg =3D <0x0 0x9b400000 0x0 0x80000>; no-map; }; - pil_cvp_mem: pil-cvp@9f500000 { - reg =3D <0x0 0x9f500000 0x0 0x700000>; + q6_cdsp0_dtb_mem: q6-cdsp0-dtb@9b480000 { + reg =3D <0x0 0x9b480000 0x0 0x80000>; no-map; }; - pil_video_mem: pil-video@9fc00000 { - reg =3D <0x0 0x9fc00000 0x0 0x700000>; + pil_cdsp0_mem: pil-cdsp0@9b500000 { + reg =3D <0x0 0x9b500000 0x0 0x1e00000>; no-map; }; - audio_mdf_mem: audio-mdf-region@ae000000 { - reg =3D <0x0 0xae000000 0x0 0x1000000>; + pil_gpu_mem: pil-gpu@9d300000 { + reg =3D <0x0 0x9d300000 0x0 0x2000>; no-map; }; - firmware_mem: firmware-region@b0000000 { - reg =3D <0x0 0xb0000000 0x0 0x800000>; + q6_cdsp1_dtb_mem: q6-cdsp1-dtb@9d380000 { + reg =3D <0x0 0x9d380000 0x0 0x80000>; no-map; }; - hyptz_reserved_mem: hyptz-reserved@beb00000 { - reg =3D <0x0 0xbeb00000 0x0 0x11500000>; + pil_cdsp1_mem: pil-cdsp1@9d400000 { + reg =3D <0x0 0x9d400000 0x0 0x1e00000>; + no-map; + }; + + pil_cvp_mem: pil-cvp@9f200000 { + reg =3D <0x0 0x9f200000 0x0 0x700000>; + no-map; + }; + + pil_video_mem: pil-video@9f900000 { + reg =3D <0x0 0x9f900000 0x0 0x1000000>; + no-map; + }; + + firmware_mem: firmware-region@b0000000 { + reg =3D <0x0 0xb0000000 0x0 0x800000>; no-map; }; @@ -915,7 +928,7 @@ deepsleep_backup_mem: deepsleep-backup@d1800000 { }; trusted_apps_mem: trusted-apps@d1900000 { - reg =3D <0x0 0xd1900000 0x0 0x3800000>; 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charset="utf-8" Ride & Ride-r3 in lemans/lemans-auto uses different ethernet cards with different phy capabilities. Separate out the ethernet card information from main board so that it can be reused for all the variants of ride & ride-r3 platforms in lemans/lemans-auto. Lemans/lemans-auto Ride uses 1G phy while Lemans/lemans-auto Ride-r3 uses 2.5G phy. Introduce ethernet cards with 1G & 2.5G phy capabilities respectively: *-88ea1512.dtsi is for 2x 1G - SGMII (Marvell 88EA1512-B2) phy *-aqr115c.dtsi is for 2x 2.5G - HSGMII (Marvell AQR115c) phy Signed-off-by: Wasim Nazir --- .../qcom/lemans-ride-ethernet-88ea1512.dtsi | 205 ++++++++++++++++++ .../qcom/lemans-ride-ethernet-aqr115c.dtsi | 205 ++++++++++++++++++ arch/arm64/boot/dts/qcom/sa8775p-ride-r3.dts | 35 +-- arch/arm64/boot/dts/qcom/sa8775p-ride.dts | 35 +-- arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi | 163 -------------- 5 files changed, 412 insertions(+), 231 deletions(-) create mode 100644 arch/arm64/boot/dts/qcom/lemans-ride-ethernet-88ea1512.= dtsi create mode 100644 arch/arm64/boot/dts/qcom/lemans-ride-ethernet-aqr115c.d= tsi diff --git a/arch/arm64/boot/dts/qcom/lemans-ride-ethernet-88ea1512.dtsi b/= arch/arm64/boot/dts/qcom/lemans-ride-ethernet-88ea1512.dtsi new file mode 100644 index 000000000000..9d6bbe1447a4 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/lemans-ride-ethernet-88ea1512.dtsi @@ -0,0 +1,205 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023, Linaro Limited + */ + +/* + * Ethernet card for Lemans based Ride boards. + * It supports 2x 1G - SGMII (Marvell 88EA1512-B2) phy for Main domain + */ + +#include +#include + +/ { + aliases { + ethernet0 =3D ðernet0; + ethernet1 =3D ðernet1; + }; +}; + +&tlmm { + ethernet0_default: ethernet0-default-state { + ethernet0_mdc: ethernet0-mdc-pins { + pins =3D "gpio8"; + function =3D "emac0_mdc"; + drive-strength =3D <16>; + bias-pull-up; + }; + + ethernet0_mdio: ethernet0-mdio-pins { + pins =3D "gpio9"; + function =3D "emac0_mdio"; + drive-strength =3D <16>; + bias-pull-up; + }; + }; +}; + +ðernet0 { + phy-handle =3D <&sgmii_phy0>; + phy-mode =3D "sgmii"; + + pinctrl-0 =3D <ðernet0_default>; + pinctrl-names =3D "default"; + + snps,mtl-rx-config =3D <&mtl_rx_setup>; + snps,mtl-tx-config =3D <&mtl_tx_setup>; + snps,ps-speed =3D <1000>; + + status =3D "okay"; + + mdio { + compatible =3D "snps,dwmac-mdio"; + #address-cells =3D <1>; + #size-cells =3D <0>; + + sgmii_phy0: phy@8 { + compatible =3D "ethernet-phy-id0141.0dd4"; + reg =3D <0x8>; + device_type =3D "ethernet-phy"; + interrupts-extended =3D <&tlmm 7 IRQ_TYPE_EDGE_FALLING>; + reset-gpios =3D <&pmm8654au_2_gpios 8 GPIO_ACTIVE_LOW>; + reset-assert-us =3D <11000>; + reset-deassert-us =3D <70000>; + }; + + sgmii_phy1: phy@a { + compatible =3D "ethernet-phy-id0141.0dd4"; + reg =3D <0xa>; + device_type =3D "ethernet-phy"; + interrupts-extended =3D <&tlmm 26 IRQ_TYPE_EDGE_FALLING>; + reset-gpios =3D <&pmm8654au_2_gpios 9 GPIO_ACTIVE_LOW>; + reset-assert-us =3D <11000>; + reset-deassert-us =3D <70000>; + }; + }; + + mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use =3D <4>; + snps,rx-sched-sp; + + queue0 { + snps,dcb-algorithm; + snps,map-to-dma-channel =3D <0x0>; + snps,route-up; + snps,priority =3D <0x1>; + }; + + queue1 { + snps,dcb-algorithm; + snps,map-to-dma-channel =3D <0x1>; + snps,route-ptp; + }; + + queue2 { + snps,avb-algorithm; + snps,map-to-dma-channel =3D <0x2>; + snps,route-avcp; + }; + + queue3 { + snps,avb-algorithm; + snps,map-to-dma-channel =3D <0x3>; + snps,priority =3D <0xc>; + }; + }; + + mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use =3D <4>; + + queue0 { + snps,dcb-algorithm; + }; + + queue1 { + snps,dcb-algorithm; + }; + + queue2 { + snps,avb-algorithm; + snps,send_slope =3D <0x1000>; + snps,idle_slope =3D <0x1000>; + snps,high_credit =3D <0x3e800>; + snps,low_credit =3D <0xffc18000>; + }; + + queue3 { + snps,avb-algorithm; + snps,send_slope =3D <0x1000>; + snps,idle_slope =3D <0x1000>; + snps,high_credit =3D <0x3e800>; + snps,low_credit =3D <0xffc18000>; + }; + }; +}; + +ðernet1 { + phy-handle =3D <&sgmii_phy1>; + phy-mode =3D "sgmii"; + + snps,mtl-rx-config =3D <&mtl_rx_setup1>; + snps,mtl-tx-config =3D <&mtl_tx_setup1>; + snps,ps-speed =3D <1000>; + + status =3D "okay"; + + mtl_rx_setup1: rx-queues-config { + snps,rx-queues-to-use =3D <4>; + snps,rx-sched-sp; + + queue0 { + snps,dcb-algorithm; + snps,map-to-dma-channel =3D <0x0>; + snps,route-up; + snps,priority =3D <0x1>; + }; + + queue1 { + snps,dcb-algorithm; + snps,map-to-dma-channel =3D <0x1>; + snps,route-ptp; + }; + + queue2 { + snps,avb-algorithm; + snps,map-to-dma-channel =3D <0x2>; + snps,route-avcp; + }; + + queue3 { + snps,avb-algorithm; + snps,map-to-dma-channel =3D <0x3>; + snps,priority =3D <0xc>; + }; + }; + + mtl_tx_setup1: tx-queues-config { + snps,tx-queues-to-use =3D <4>; + + queue0 { + snps,dcb-algorithm; + }; + + queue1 { + snps,dcb-algorithm; + }; + + queue2 { + snps,avb-algorithm; + snps,send_slope =3D <0x1000>; + snps,idle_slope =3D <0x1000>; + snps,high_credit =3D <0x3e800>; + snps,low_credit =3D <0xffc18000>; + }; + + queue3 { + snps,avb-algorithm; + snps,send_slope =3D <0x1000>; + snps,idle_slope =3D <0x1000>; + snps,high_credit =3D <0x3e800>; + snps,low_credit =3D <0xffc18000>; + }; + }; +}; + diff --git a/arch/arm64/boot/dts/qcom/lemans-ride-ethernet-aqr115c.dtsi b/a= rch/arm64/boot/dts/qcom/lemans-ride-ethernet-aqr115c.dtsi new file mode 100644 index 000000000000..2d2d9ee5f0d9 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/lemans-ride-ethernet-aqr115c.dtsi @@ -0,0 +1,205 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023, Linaro Limited + */ + +/* + * Ethernet card for Lemans based Ride r3 boards. + * It supports 2x 2.5G - HSGMII (Marvell hsgmii) phy for Main domain + */ + +#include +#include + +/ { + aliases { + ethernet0 =3D ðernet0; + ethernet1 =3D ðernet1; + }; +}; + +&tlmm { + ethernet0_default: ethernet0-default-state { + ethernet0_mdc: ethernet0-mdc-pins { + pins =3D "gpio8"; + function =3D "emac0_mdc"; + drive-strength =3D <16>; + bias-pull-up; + }; + + ethernet0_mdio: ethernet0-mdio-pins { + pins =3D "gpio9"; + function =3D "emac0_mdio"; + drive-strength =3D <16>; + bias-pull-up; + }; + }; +}; + +ðernet0 { + phy-handle =3D <&hsgmii_phy0>; + phy-mode =3D "2500base-x"; + + pinctrl-0 =3D <ðernet0_default>; + pinctrl-names =3D "default"; + + snps,mtl-rx-config =3D <&mtl_rx_setup>; + snps,mtl-tx-config =3D <&mtl_tx_setup>; + snps,ps-speed =3D <1000>; + + status =3D "okay"; + + mdio { + compatible =3D "snps,dwmac-mdio"; + #address-cells =3D <1>; + #size-cells =3D <0>; + + hsgmii_phy0: phy@8 { + compatible =3D "ethernet-phy-id31c3.1c33"; + reg =3D <0x8>; + device_type =3D "ethernet-phy"; + interrupts-extended =3D <&tlmm 7 IRQ_TYPE_EDGE_FALLING>; + reset-gpios =3D <&pmm8654au_2_gpios 8 GPIO_ACTIVE_LOW>; + reset-assert-us =3D <11000>; + reset-deassert-us =3D <70000>; + }; + + hsgmii_phy1: phy@0 { + compatible =3D "ethernet-phy-id31c3.1c33"; + reg =3D <0x0>; + device_type =3D "ethernet-phy"; + interrupts-extended =3D <&tlmm 26 IRQ_TYPE_EDGE_FALLING>; + reset-gpios =3D <&pmm8654au_2_gpios 9 GPIO_ACTIVE_LOW>; + reset-assert-us =3D <11000>; + reset-deassert-us =3D <70000>; + }; + }; + + mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use =3D <4>; + snps,rx-sched-sp; + + queue0 { + snps,dcb-algorithm; + snps,map-to-dma-channel =3D <0x0>; + snps,route-up; + snps,priority =3D <0x1>; + }; + + queue1 { + snps,dcb-algorithm; + snps,map-to-dma-channel =3D <0x1>; + snps,route-ptp; + }; + + queue2 { + snps,avb-algorithm; + snps,map-to-dma-channel =3D <0x2>; + snps,route-avcp; + }; + + queue3 { + snps,avb-algorithm; + snps,map-to-dma-channel =3D <0x3>; + snps,priority =3D <0xc>; + }; + }; + + mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use =3D <4>; + + queue0 { + snps,dcb-algorithm; + }; + + queue1 { + snps,dcb-algorithm; + }; + + queue2 { + snps,avb-algorithm; + snps,send_slope =3D <0x1000>; + snps,idle_slope =3D <0x1000>; + snps,high_credit =3D <0x3e800>; + snps,low_credit =3D <0xffc18000>; + }; + + queue3 { + snps,avb-algorithm; + snps,send_slope =3D <0x1000>; + snps,idle_slope =3D <0x1000>; + snps,high_credit =3D <0x3e800>; + snps,low_credit =3D <0xffc18000>; + }; + }; +}; + +ðernet1 { + phy-handle =3D <&hsgmii_phy1>; + phy-mode =3D "2500base-x"; + + snps,mtl-rx-config =3D <&mtl_rx_setup1>; + snps,mtl-tx-config =3D <&mtl_tx_setup1>; + snps,ps-speed =3D <1000>; + + status =3D "okay"; + + mtl_rx_setup1: rx-queues-config { + snps,rx-queues-to-use =3D <4>; + snps,rx-sched-sp; + + queue0 { + snps,dcb-algorithm; + snps,map-to-dma-channel =3D <0x0>; + snps,route-up; + snps,priority =3D <0x1>; + }; + + queue1 { + snps,dcb-algorithm; + snps,map-to-dma-channel =3D <0x1>; + snps,route-ptp; + }; + + queue2 { + snps,avb-algorithm; + snps,map-to-dma-channel =3D <0x2>; + snps,route-avcp; + }; + + queue3 { + snps,avb-algorithm; + snps,map-to-dma-channel =3D <0x3>; + snps,priority =3D <0xc>; + }; + }; + + mtl_tx_setup1: tx-queues-config { + snps,tx-queues-to-use =3D <4>; + + queue0 { + snps,dcb-algorithm; + }; + + queue1 { + snps,dcb-algorithm; + }; + + queue2 { + snps,avb-algorithm; + snps,send_slope =3D <0x1000>; + snps,idle_slope =3D <0x1000>; + snps,high_credit =3D <0x3e800>; + snps,low_credit =3D <0xffc18000>; + }; + + queue3 { + snps,avb-algorithm; + snps,send_slope =3D <0x1000>; + snps,idle_slope =3D <0x1000>; + snps,high_credit =3D <0x3e800>; + snps,low_credit =3D <0xffc18000>; + }; + }; +}; + diff --git a/arch/arm64/boot/dts/qcom/sa8775p-ride-r3.dts b/arch/arm64/boot= /dts/qcom/sa8775p-ride-r3.dts index ae065ae92478..a7f377dc4733 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p-ride-r3.dts +++ b/arch/arm64/boot/dts/qcom/sa8775p-ride-r3.dts @@ -6,42 +6,9 @@ /dts-v1/; #include "sa8775p-ride.dtsi" +#include "lemans-ride-ethernet-aqr115c.dtsi" / { model =3D "Qualcomm SA8775P Ride Rev3"; compatible =3D "qcom,sa8775p-ride-r3", "qcom,sa8775p"; }; - -ðernet0 { - phy-mode =3D "2500base-x"; -}; - -ðernet1 { - phy-mode =3D "2500base-x"; -}; - -&mdio { - compatible =3D "snps,dwmac-mdio"; - #address-cells =3D <1>; - #size-cells =3D <0>; - - sgmii_phy0: phy@8 { - compatible =3D "ethernet-phy-id31c3.1c33"; - reg =3D <0x8>; - device_type =3D "ethernet-phy"; - interrupts-extended =3D <&tlmm 7 IRQ_TYPE_EDGE_FALLING>; - reset-gpios =3D <&pmm8654au_2_gpios 8 GPIO_ACTIVE_LOW>; - reset-assert-us =3D <11000>; - reset-deassert-us =3D <70000>; - }; - - sgmii_phy1: phy@0 { - compatible =3D "ethernet-phy-id31c3.1c33"; - reg =3D <0x0>; - device_type =3D "ethernet-phy"; - interrupts-extended =3D <&tlmm 26 IRQ_TYPE_EDGE_FALLING>; - reset-gpios =3D <&pmm8654au_2_gpios 9 GPIO_ACTIVE_LOW>; - reset-assert-us =3D <11000>; - reset-deassert-us =3D <70000>; - }; -}; diff --git a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts b/arch/arm64/boot/dt= s/qcom/sa8775p-ride.dts index 2e87fd760dbd..b765794f7e54 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts +++ b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts @@ -6,42 +6,9 @@ /dts-v1/; #include "sa8775p-ride.dtsi" +#include "lemans-ride-ethernet-88ea1512.dtsi" / { model =3D "Qualcomm SA8775P Ride"; compatible =3D "qcom,sa8775p-ride", "qcom,sa8775p"; }; - -ðernet0 { - phy-mode =3D "sgmii"; -}; - -ðernet1 { - phy-mode =3D "sgmii"; -}; - -&mdio { - compatible =3D "snps,dwmac-mdio"; - #address-cells =3D <1>; - #size-cells =3D <0>; - - sgmii_phy0: phy@8 { - compatible =3D "ethernet-phy-id0141.0dd4"; - reg =3D <0x8>; - device_type =3D "ethernet-phy"; - interrupts-extended =3D <&tlmm 7 IRQ_TYPE_EDGE_FALLING>; - reset-gpios =3D <&pmm8654au_2_gpios 8 GPIO_ACTIVE_LOW>; - reset-assert-us =3D <11000>; - reset-deassert-us =3D <70000>; - }; - - sgmii_phy1: phy@a { - compatible =3D "ethernet-phy-id0141.0dd4"; - reg =3D <0xa>; - device_type =3D "ethernet-phy"; - interrupts-extended =3D <&tlmm 26 IRQ_TYPE_EDGE_FALLING>; - reset-gpios =3D <&pmm8654au_2_gpios 9 GPIO_ACTIVE_LOW>; - reset-assert-us =3D <11000>; - reset-deassert-us =3D <70000>; - }; -}; diff --git a/arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi b/arch/arm64/boot/d= ts/qcom/sa8775p-ride.dtsi index a9ec6ded412e..f512363f6222 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi @@ -13,8 +13,6 @@ / { aliases { - ethernet0 =3D ðernet0; - ethernet1 =3D ðernet1; i2c11 =3D &i2c11; i2c18 =3D &i2c18; serial0 =3D &uart10; @@ -443,151 +441,6 @@ vreg_l8e: ldo8 { }; }; -ðernet0 { - phy-handle =3D <&sgmii_phy0>; - - pinctrl-0 =3D <ðernet0_default>; - pinctrl-names =3D "default"; - - snps,mtl-rx-config =3D <&mtl_rx_setup>; - snps,mtl-tx-config =3D <&mtl_tx_setup>; - snps,ps-speed =3D <1000>; - - status =3D "okay"; - - mdio: mdio { - compatible =3D "snps,dwmac-mdio"; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - - mtl_rx_setup: rx-queues-config { - snps,rx-queues-to-use =3D <4>; - snps,rx-sched-sp; - - queue0 { - snps,dcb-algorithm; - snps,map-to-dma-channel =3D <0x0>; - snps,route-up; - snps,priority =3D <0x1>; - }; - - queue1 { - snps,dcb-algorithm; - snps,map-to-dma-channel =3D <0x1>; - snps,route-ptp; - }; - - queue2 { - snps,avb-algorithm; - snps,map-to-dma-channel =3D <0x2>; - snps,route-avcp; - }; - - queue3 { - snps,avb-algorithm; - snps,map-to-dma-channel =3D <0x3>; - snps,priority =3D <0xc>; - }; - }; - - mtl_tx_setup: tx-queues-config { - snps,tx-queues-to-use =3D <4>; - - queue0 { - snps,dcb-algorithm; - }; - - queue1 { - snps,dcb-algorithm; - }; - - queue2 { - snps,avb-algorithm; - snps,send_slope =3D <0x1000>; - snps,idle_slope =3D <0x1000>; - snps,high_credit =3D <0x3e800>; - snps,low_credit =3D <0xffc18000>; - }; - - queue3 { - snps,avb-algorithm; - snps,send_slope =3D <0x1000>; - snps,idle_slope =3D <0x1000>; - snps,high_credit =3D <0x3e800>; - snps,low_credit =3D <0xffc18000>; - }; - }; -}; - -ðernet1 { - phy-handle =3D <&sgmii_phy1>; - - snps,mtl-rx-config =3D <&mtl_rx_setup1>; - snps,mtl-tx-config =3D <&mtl_tx_setup1>; - snps,ps-speed =3D <1000>; - - status =3D "okay"; - - mtl_rx_setup1: rx-queues-config { - snps,rx-queues-to-use =3D <4>; - snps,rx-sched-sp; - - queue0 { - snps,dcb-algorithm; - snps,map-to-dma-channel =3D <0x0>; - snps,route-up; - snps,priority =3D <0x1>; - }; - - queue1 { - snps,dcb-algorithm; - snps,map-to-dma-channel =3D <0x1>; - snps,route-ptp; - }; - - queue2 { - snps,avb-algorithm; - snps,map-to-dma-channel =3D <0x2>; - snps,route-avcp; - }; - - queue3 { - snps,avb-algorithm; - snps,map-to-dma-channel =3D <0x3>; - snps,priority =3D <0xc>; - }; - }; - - mtl_tx_setup1: tx-queues-config { - snps,tx-queues-to-use =3D <4>; - - queue0 { - snps,dcb-algorithm; - }; - - queue1 { - snps,dcb-algorithm; - }; - - queue2 { - snps,avb-algorithm; - snps,send_slope =3D <0x1000>; - snps,idle_slope =3D <0x1000>; - snps,high_credit =3D <0x3e800>; - snps,low_credit =3D <0xffc18000>; - }; - - queue3 { - snps,avb-algorithm; - snps,send_slope =3D <0x1000>; - snps,idle_slope =3D <0x1000>; - snps,high_credit =3D <0x3e800>; - snps,low_credit =3D <0xffc18000>; - }; - }; -}; - &i2c11 { clock-frequency =3D <400000>; status =3D "okay"; @@ -960,22 +813,6 @@ dp1_hot_plug_det: dp1-hot-plug-det-state { bias-disable; }; - ethernet0_default: ethernet0-default-state { - ethernet0_mdc: ethernet0-mdc-pins { - pins =3D "gpio8"; - function =3D "emac0_mdc"; - drive-strength =3D <16>; - bias-pull-up; - }; - - ethernet0_mdio: ethernet0-mdio-pins { - pins =3D "gpio9"; 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charset="utf-8" Ride/Ride-r3 boards used with lemans and derivatives: - Are composed of multiple daughter cards (SoC-card, display, camera, ethernet, pcie, sensor, front & backplane, WLAN & BT). - Across lemans & its derivatives, SoM is changing. - Across Ride & Ride-r3 board, ethernet card is changing. Excluding the differences all other cards i.e SoC-card, display, camera, PCIe, sensor, front & backplane are same across Ride/Ride-r3 boards used with lemans and derivatives. Describe all the common cards in lemans-ride-common so that it can be reused for all the variants of ride & ride-r3 platforms in lemans and derivatives. Signed-off-by: Wasim Nazir --- .../dts/qcom/{sa8775p-ride.dtsi =3D> lemans-ride-common.dtsi} | 5 ----- arch/arm64/boot/dts/qcom/sa8775p-ride-r3.dts | 5 ++++- arch/arm64/boot/dts/qcom/sa8775p-ride.dts | 5 ++++- 3 files changed, 8 insertions(+), 7 deletions(-) rename arch/arm64/boot/dts/qcom/{sa8775p-ride.dtsi =3D> lemans-ride-common= .dtsi} (99%) diff --git a/arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi b/arch/arm64/boot/d= ts/qcom/lemans-ride-common.dtsi similarity index 99% rename from arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi rename to arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi index f512363f6222..25e756c14160 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi @@ -3,14 +3,9 @@ * Copyright (c) 2023, Linaro Limited */ -/dts-v1/; - #include #include -#include "lemans-auto.dtsi" -#include "sa8775p-pmics.dtsi" - / { aliases { i2c11 =3D &i2c11; diff --git a/arch/arm64/boot/dts/qcom/sa8775p-ride-r3.dts b/arch/arm64/boot= /dts/qcom/sa8775p-ride-r3.dts index a7f377dc4733..3e19ff5e061f 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p-ride-r3.dts +++ b/arch/arm64/boot/dts/qcom/sa8775p-ride-r3.dts @@ -5,7 +5,10 @@ /dts-v1/; -#include "sa8775p-ride.dtsi" +#include "lemans-auto.dtsi" + +#include "sa8775p-pmics.dtsi" +#include "lemans-ride-common.dtsi" #include "lemans-ride-ethernet-aqr115c.dtsi" / { diff --git a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts b/arch/arm64/boot/dt= s/qcom/sa8775p-ride.dts index b765794f7e54..68a99582b538 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts +++ b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts @@ -5,7 +5,10 @@ /dts-v1/; -#include "sa8775p-ride.dtsi" +#include "lemans-auto.dtsi" + +#include "sa8775p-pmics.dtsi" +#include "lemans-ride-common.dtsi" #include "lemans-ride-ethernet-88ea1512.dtsi" / { -- 2.49.0 From nobody Mon Oct 6 10:17:31 2025 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C2D432EBDF5; Tue, 22 Jul 2025 14:49:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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charset="utf-8" Rename qcs9100 based ride-r3 board to lemans ride-r3 and use it for all the IoT ride-r3 boards. Rename sa8775p based ride/ride-r3 boards to lemans-auto ride/ride-r3, to allow users to run with old automotive memory-map. Remove support for qcs9100-ride, as no platform currently uses it. Signed-off-by: Wasim Nazir --- arch/arm64/boot/dts/qcom/Makefile | 7 +++---- .../{sa8775p-ride-r3.dts =3D> lemans-auto-ride-r3.dts} | 6 +++--- .../qcom/{sa8775p-ride.dts =3D> lemans-auto-ride.dts} | 6 +++--- .../qcom/{sa8775p-pmics.dtsi =3D> lemans-pmics.dtsi} | 0 .../qcom/{qcs9100-ride-r3.dts =3D> lemans-ride-r3.dts} | 12 +++++++++--- arch/arm64/boot/dts/qcom/qcs9100-ride.dts | 11 ----------- 6 files changed, 18 insertions(+), 24 deletions(-) rename arch/arm64/boot/dts/qcom/{sa8775p-ride-r3.dts =3D> lemans-auto-ride= -r3.dts} (59%) rename arch/arm64/boot/dts/qcom/{sa8775p-ride.dts =3D> lemans-auto-ride.dt= s} (60%) rename arch/arm64/boot/dts/qcom/{sa8775p-pmics.dtsi =3D> lemans-pmics.dtsi= } (100%) rename arch/arm64/boot/dts/qcom/{qcs9100-ride-r3.dts =3D> lemans-ride-r3.d= ts} (36%) delete mode 100644 arch/arm64/boot/dts/qcom/qcs9100-ride.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/M= akefile index 4bfa926b6a08..2a1941c29537 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -29,6 +29,9 @@ dtb-$(CONFIG_ARCH_QCOM) +=3D ipq9574-rdp433.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D ipq9574-rdp449.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D ipq9574-rdp453.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D ipq9574-rdp454.dtb +dtb-$(CONFIG_ARCH_QCOM) +=3D lemans-auto-ride.dtb +dtb-$(CONFIG_ARCH_QCOM) +=3D lemans-auto-ride-r3.dtb +dtb-$(CONFIG_ARCH_QCOM) +=3D lemans-ride-r3.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D msm8216-samsung-fortuna3g.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D msm8916-acer-a1-724.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D msm8916-alcatel-idol347.dtb @@ -126,8 +129,6 @@ dtb-$(CONFIG_ARCH_QCOM) +=3D qcs6490-rb3gen2-industrial= -mezzanine.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D qcs6490-rb3gen2-vision-mezzanine.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D qcs8300-ride.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D qcs8550-aim300-aiot.dtb -dtb-$(CONFIG_ARCH_QCOM) +=3D qcs9100-ride.dtb -dtb-$(CONFIG_ARCH_QCOM) +=3D qcs9100-ride-r3.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D qdu1000-idp.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D qrb2210-rb1.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D qrb4210-rb2.dtb @@ -140,8 +141,6 @@ dtb-$(CONFIG_ARCH_QCOM) +=3D qru1000-idp.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sa8155p-adp.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sa8295p-adp.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sa8540p-ride.dtb -dtb-$(CONFIG_ARCH_QCOM) +=3D sa8775p-ride.dtb -dtb-$(CONFIG_ARCH_QCOM) +=3D sa8775p-ride-r3.dtb sc7180-acer-aspire1-el2-dtbs :=3D sc7180-acer-aspire1.dtb sc7180-el2.dtbo dtb-$(CONFIG_ARCH_QCOM) +=3D sc7180-acer-aspire1.dtb sc7180-acer-aspire1-e= l2.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sc7180-idp.dtb diff --git a/arch/arm64/boot/dts/qcom/sa8775p-ride-r3.dts b/arch/arm64/boot= /dts/qcom/lemans-auto-ride-r3.dts similarity index 59% rename from arch/arm64/boot/dts/qcom/sa8775p-ride-r3.dts rename to arch/arm64/boot/dts/qcom/lemans-auto-ride-r3.dts index 3e19ff5e061f..0e19ec46be3c 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p-ride-r3.dts +++ b/arch/arm64/boot/dts/qcom/lemans-auto-ride-r3.dts @@ -7,11 +7,11 @@ #include "lemans-auto.dtsi" -#include "sa8775p-pmics.dtsi" +#include "lemans-pmics.dtsi" #include "lemans-ride-common.dtsi" #include "lemans-ride-ethernet-aqr115c.dtsi" / { - model =3D "Qualcomm SA8775P Ride Rev3"; - compatible =3D "qcom,sa8775p-ride-r3", "qcom,sa8775p"; + model =3D "Qualcomm Technologies, Inc. Lemans-auto Ride Rev3"; + compatible =3D "qcom,lemans-auto-ride-r3", "qcom,sa8775p"; }; diff --git a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts b/arch/arm64/boot/dt= s/qcom/lemans-auto-ride.dts similarity index 60% rename from arch/arm64/boot/dts/qcom/sa8775p-ride.dts rename to arch/arm64/boot/dts/qcom/lemans-auto-ride.dts index 68a99582b538..6af707263ad7 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts +++ b/arch/arm64/boot/dts/qcom/lemans-auto-ride.dts @@ -7,11 +7,11 @@ #include "lemans-auto.dtsi" -#include "sa8775p-pmics.dtsi" +#include "lemans-pmics.dtsi" #include "lemans-ride-common.dtsi" #include "lemans-ride-ethernet-88ea1512.dtsi" / { - model =3D "Qualcomm SA8775P Ride"; - compatible =3D "qcom,sa8775p-ride", "qcom,sa8775p"; + model =3D "Qualcomm Technologies, Inc. Lemans-auto Ride"; + compatible =3D "qcom,lemans-auto-ride", "qcom,sa8775p"; }; diff --git a/arch/arm64/boot/dts/qcom/sa8775p-pmics.dtsi b/arch/arm64/boot/= dts/qcom/lemans-pmics.dtsi similarity index 100% rename from arch/arm64/boot/dts/qcom/sa8775p-pmics.dtsi rename to arch/arm64/boot/dts/qcom/lemans-pmics.dtsi diff --git a/arch/arm64/boot/dts/qcom/qcs9100-ride-r3.dts b/arch/arm64/boot= /dts/qcom/lemans-ride-r3.dts similarity index 36% rename from arch/arm64/boot/dts/qcom/qcs9100-ride-r3.dts rename to arch/arm64/boot/dts/qcom/lemans-ride-r3.dts index 759d1ec694b2..310c93f4a275 100644 --- a/arch/arm64/boot/dts/qcom/qcs9100-ride-r3.dts +++ b/arch/arm64/boot/dts/qcom/lemans-ride-r3.dts @@ -2,10 +2,16 @@ /* * Copyright (c) 2024, Qualcomm Innovation Center, Inc. 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charset="utf-8" Remove qcs9100 SoC and rename its associated boards to "lemans-*", to represent the IoT variants. Rename sa8775p based boards to "lemans-auto-*", derived from "lemans", to represent boards which uses old automotive memory-map. Preserve sa8775p SoC definition to maintain backward compatibility. Both "lemans" and "lemans-auto" are essentially the same non-safe chips, since the safety monitoring feature of Safety Island (SAIL) subsystem is not supported, but they differ in memory-map. Introduce new bindings for the Lemans Evaluation Kit (EVK), an additional IoT board without safety features. Signed-off-by: Wasim Nazir --- Documentation/devicetree/bindings/arm/qcom.yaml | 16 +++++----------- 1 file changed, 5 insertions(+), 11 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentatio= n/devicetree/bindings/arm/qcom.yaml index 47a7b1cb3cac..174ef6924906 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -59,14 +59,13 @@ description: | qcs8550 qcm2290 qcm6490 - qcs9100 qdu1000 qrb2210 qrb4210 qru1000 sa8155p sa8540p - sa8775p + sa8775p # lemans sar2130p sc7180 sc7280 @@ -972,15 +971,10 @@ properties: - items: - enum: - - qcom,sa8775p-ride - - qcom,sa8775p-ride-r3 - - const: qcom,sa8775p - - - items: - - enum: - - qcom,qcs9100-ride - - qcom,qcs9100-ride-r3 - - const: qcom,qcs9100 + - qcom,lemans-evk + - qcom,lemans-ride-r3 + - qcom,lemans-auto-ride + - qcom,lemans-auto-ride-r3 - const: qcom,sa8775p - items: -- 2.49.0 From nobody Mon Oct 6 10:17:31 2025 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1F2E62EBBB6; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: DGpeP0TReHlrLthH1C7cNiOTvUWXcj5N X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzIyMDEyMyBTYWx0ZWRfX5t/urR/1AZ/9 V+bwTanNp6bvw+9JnkbZMeOggDSIhepDEWTGVYEXx+mJvo59H6vWNZbjFG0V0XUQ8DIIm7bgm/Z 5i0ugdVm8wej6Ds2ts3wHk0T60v8mbEI869Hzr+FKcf16oWLnXk+XufACY3gwSErcGZmHeS1M83 rGf47n1fwKwlH2W19C8VAwSsCghv7tgX53BY1s7Fpws8ZQPyoJRDb0ypMdMrplPiEvyanQupMY2 CEqodhudeVeqZAWJMCrK0u2LmaqpAD217RYGsqBMJQg0Y5dlm6Ek2J7i12eg7CEpt4fR/k+37Ag UPGofRM6PG+12ZDeRAF4NB189F7B57SjSeSp3ZoPwmtGA/pKYRrNCrre0O23ZyDD9+LNqEx1dkK kcKwdfuXITag2w/4VBaq12mKPWR0TGmmWWHlo92Tp/pdEubiHNh0MFZ/ZwJ/9BBu0dL/qnXT X-Authority-Analysis: v=2.4 cv=Q+fS452a c=1 sm=1 tr=0 ts=687fa511 cx=c_pps a=Ou0eQOY4+eZoSc0qltEV5Q==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=IkcTkHD0fZMA:10 a=Wb1JkmetP80A:10 a=COk6AnOGAAAA:8 a=EUspDBNiAAAA:8 a=SOkdykdnccwuzwQJ1m4A:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-GUID: DGpeP0TReHlrLthH1C7cNiOTvUWXcj5N X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-22_02,2025-07-21_02,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 adultscore=0 phishscore=0 mlxscore=0 lowpriorityscore=0 mlxlogscore=999 suspectscore=0 spamscore=0 priorityscore=1501 malwarescore=0 bulkscore=0 impostorscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507220123 Lemans EVK is an IoT board without safety monitoring feature of Safety Island(SAIL) subsystem. Lemans EVK is single board supporting these peripherals: - Storage: 2 =C3=97 128 GB UFS, micro-SD card, EEPROMs for MACs, eMMC on mezzanine card - Audio/Video, Camera & Display ports - Connectivity: RJ45 2.5GbE, WLAN/Bluetooth, CAN/CAN-FD - Sensors: IMU - PCIe ports - USB & UART ports On top of lemans EVK board additional mezzanine boards can be stacked in future. Implement basic features like uart/ufs to enable 'boot to shell'. Co-developed-by: Rakesh Kota Signed-off-by: Rakesh Kota Co-developed-by: Sayali Lokhande Signed-off-by: Sayali Lokhande Reviewed-by: Konrad Dybcio Signed-off-by: Wasim Nazir --- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/lemans-evk.dts | 291 ++++++++++++++++++++++++ 2 files changed, 292 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/lemans-evk.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/M= akefile index 2a1941c29537..cbc89c54f92b 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -31,6 +31,7 @@ dtb-$(CONFIG_ARCH_QCOM) +=3D ipq9574-rdp453.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D ipq9574-rdp454.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D lemans-auto-ride.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D lemans-auto-ride-r3.dtb +dtb-$(CONFIG_ARCH_QCOM) +=3D lemans-evk.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D lemans-ride-r3.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D msm8216-samsung-fortuna3g.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D msm8916-acer-a1-724.dtb diff --git a/arch/arm64/boot/dts/qcom/lemans-evk.dts b/arch/arm64/boot/dts/= qcom/lemans-evk.dts new file mode 100644 index 000000000000..dd357d514587 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/lemans-evk.dts @@ -0,0 +1,291 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/dts-v1/; + +#include +#include + +#include "lemans.dtsi" +#include "lemans-pmics.dtsi" + +/ { + model =3D "Qualcomm Technologies, Inc. Lemans EVK"; + compatible =3D "qcom,lemans-evk", "qcom,sa8775p"; + + aliases { + serial0 =3D &uart10; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; +}; + +&apps_rsc { + regulators-0 { + compatible =3D "qcom,pmm8654au-rpmh-regulators"; + qcom,pmic-id =3D "a"; + + vreg_s4a: smps4 { + regulator-name =3D "vreg_s4a"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1816000>; + regulator-initial-mode =3D ; + }; + + vreg_s5a: smps5 { + regulator-name =3D "vreg_s5a"; + regulator-min-microvolt =3D <1850000>; + regulator-max-microvolt =3D <1996000>; + regulator-initial-mode =3D ; + }; + + vreg_s9a: smps9 { + regulator-name =3D "vreg_s9a"; + regulator-min-microvolt =3D <535000>; + regulator-max-microvolt =3D <1120000>; + regulator-initial-mode =3D ; + }; + + vreg_l4a: ldo4 { + regulator-name =3D "vreg_l4a"; + regulator-min-microvolt =3D <788000>; + regulator-max-microvolt =3D <1050000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l5a: ldo5 { + regulator-name =3D "vreg_l5a"; + regulator-min-microvolt =3D <870000>; + regulator-max-microvolt =3D <950000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l6a: ldo6 { + regulator-name =3D "vreg_l6a"; + regulator-min-microvolt =3D <870000>; + regulator-max-microvolt =3D <970000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l7a: ldo7 { + regulator-name =3D "vreg_l7a"; + regulator-min-microvolt =3D <720000>; + regulator-max-microvolt =3D <950000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l8a: ldo8 { + regulator-name =3D "vreg_l8a"; + regulator-min-microvolt =3D <2504000>; + regulator-max-microvolt =3D <3300000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l9a: ldo9 { + regulator-name =3D "vreg_l9a"; + regulator-min-microvolt =3D <2970000>; + regulator-max-microvolt =3D <3544000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + }; + + regulators-1 { + compatible =3D "qcom,pmm8654au-rpmh-regulators"; + qcom,pmic-id =3D "c"; + + vreg_l1c: ldo1 { + regulator-name =3D "vreg_l1c"; + regulator-min-microvolt =3D <1140000>; + regulator-max-microvolt =3D <1260000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l2c: ldo2 { + regulator-name =3D "vreg_l2c"; + regulator-min-microvolt =3D <900000>; + regulator-max-microvolt =3D <1100000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l3c: ldo3 { + regulator-name =3D "vreg_l3c"; + regulator-min-microvolt =3D <1100000>; + regulator-max-microvolt =3D <1300000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l4c: ldo4 { + regulator-name =3D "vreg_l4c"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l5c: ldo5 { + regulator-name =3D "vreg_l5c"; + regulator-min-microvolt =3D <1100000>; + regulator-max-microvolt =3D <1300000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l6c: ldo6 { + regulator-name =3D "vreg_l6c"; + regulator-min-microvolt =3D <1620000>; + regulator-max-microvolt =3D <1980000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l7c: ldo7 { + regulator-name =3D "vreg_l7c"; + regulator-min-microvolt =3D <1620000>; + regulator-max-microvolt =3D <2000000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l8c: ldo8 { + regulator-name =3D "vreg_l8c"; + regulator-min-microvolt =3D <2400000>; + regulator-max-microvolt =3D <3300000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l9c: ldo9 { + regulator-name =3D "vreg_l9c"; + regulator-min-microvolt =3D <1650000>; + regulator-max-microvolt =3D <2700000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + }; + + regulators-2 { + compatible =3D "qcom,pmm8654au-rpmh-regulators"; + qcom,pmic-id =3D "e"; + + vreg_s4e: smps4 { + regulator-name =3D "vreg_s4e"; + regulator-min-microvolt =3D <970000>; + regulator-max-microvolt =3D <1520000>; + regulator-initial-mode =3D ; + }; + + vreg_s7e: smps7 { + regulator-name =3D "vreg_s7e"; + regulator-min-microvolt =3D <1010000>; + regulator-max-microvolt =3D <1170000>; + regulator-initial-mode =3D ; + }; + + vreg_s9e: smps9 { + regulator-name =3D "vreg_s9e"; + regulator-min-microvolt =3D <300000>; + regulator-max-microvolt =3D <570000>; + regulator-initial-mode =3D ; + }; + + vreg_l6e: ldo6 { + regulator-name =3D "vreg_l6e"; + regulator-min-microvolt =3D <1280000>; + regulator-max-microvolt =3D <1450000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l8e: ldo8 { + regulator-name =3D "vreg_l8e"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1950000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + }; +}; + +&qupv3_id_1 { + status =3D "okay"; +}; + +&sleep_clk { + clock-frequency =3D <32768>; +}; + +&uart10 { + compatible =3D "qcom,geni-debug-uart"; + pinctrl-0 =3D <&qup_uart10_default>; + pinctrl-names =3D "default"; + + status =3D "okay"; +}; + +&ufs_mem_hc { + reset-gpios =3D <&tlmm 149 GPIO_ACTIVE_LOW>; + vcc-supply =3D <&vreg_l8a>; + vcc-max-microamp =3D <1100000>; + vccq-supply =3D <&vreg_l4c>; + vccq-max-microamp =3D <1200000>; + + status =3D "okay"; +}; + +&ufs_mem_phy { + vdda-phy-supply =3D <&vreg_l4a>; + vdda-pll-supply =3D <&vreg_l1c>; + + status =3D "okay"; +}; + +&xo_board_clk { + clock-frequency =3D <38400000>; +}; -- 2.49.0