From nobody Mon Oct 6 11:53:24 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E781A2E3B09; Tue, 22 Jul 2025 10:13:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753179214; cv=none; b=W2sgF+kQhjIN6OXtIZ2bfR8xqam8nbspWrtRClZXaACtbFg2lyRg2Uz1iGMMJfTUKPPbbWLsRTub2ryK9RmID3rpeDxFabVbL1nfBLhP78rTTvn6MQHFasE/EbzTQC7XP1txFlUcfuhyhiuMDAcnpTkgS+ewPUTYrNdBq4iKCJI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753179214; c=relaxed/simple; bh=Zl45Sp752j3kbveJVbJG3Co5ddYS+kiIWQF02duR3WI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=sJnh1+E3N7ghnf0UsDt3RggzvDsqArmlTHTUVD2hbH1vP2qS8btM7pFf8724JM09OB70JFpLfYSIZeHqL7NMpc3gC0DRNDCkYDjm0RmY5E5Vo1X55W6EE2PqvvQc4sy43Luuznh2pOT1+/7J5eIJ8L57pchlm8M5oKIB8FGq2Yw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=l5XUIhfH; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="l5XUIhfH" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1753179211; bh=Zl45Sp752j3kbveJVbJG3Co5ddYS+kiIWQF02duR3WI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=l5XUIhfHx3NdMAj6Fi8IsEI8jETgNOrdAh2PUnnW66E505F4+5V9CMcwSxuyyoc9J e1w2EVnhHxn6BMe6IKw+gqZ2cutClSNXFIDvSE/h5Q4y6+NnEOiLSflbZVo0vqjSXf Dqh80YZAfJUViNqoR8jx7LyIy8S22QZJfNUymIixzenDuK+6M+AYFeUb++uWCdB5oK JgapbVeQy6PzffrPM5P5yjEf+ff5mtvTpsFxYaRuoIBHNcgAetP4av5B+Z9tQF3UF+ /pZp3XX/zShAzurQAxnyZut78bwcYZnx8JaEX2T4jfG6zTw/NLZZPX7zUQtybclE2g ANzk83Ls8P6EQ== Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by bali.collaboradmins.com (Postfix) with ESMTPSA id 4C84C17E1324; Tue, 22 Jul 2025 12:13:30 +0200 (CEST) From: AngeloGioacchino Del Regno To: sboyd@kernel.org Cc: jic23@kernel.org, dlechner@baylibre.com, nuno.sa@analog.com, andy@kernel.org, arnd@arndb.de, gregkh@linuxfoundation.org, srini@kernel.org, vkoul@kernel.org, kishon@kernel.org, sre@kernel.org, krzysztof.kozlowski@linaro.org, u.kleine-koenig@baylibre.com, angelogioacchino.delregno@collabora.com, linux-arm-msm@vger.kernel.org, linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-pm@vger.kernel.org, kernel@collabora.com, wenst@chromium.org, casey.connolly@linaro.org Subject: [PATCH v2 6/7] iio: adc: qcom-spmi-iadc: Migrate to devm_spmi_subdevice_alloc_and_add() Date: Tue, 22 Jul 2025 12:13:16 +0200 Message-ID: <20250722101317.76729-7-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20250722101317.76729-1-angelogioacchino.delregno@collabora.com> References: <20250722101317.76729-1-angelogioacchino.delregno@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Some Qualcomm PMICs integrate an Current ADC device, reachable in a specific address range over SPMI. Instead of using the parent SPMI device (the main PMIC) as a kind of syscon in this driver, register a new SPMI sub-device and initialize its own regmap with this sub-device's specific base address, retrieved from the devicetree. This allows to stop manually adding the register base address to every R/W call in this driver, as this can be, and is now, handled by the regmap API instead. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Jonathan Cameron --- drivers/iio/adc/qcom-spmi-iadc.c | 36 +++++++++++++++++++++++--------- 1 file changed, 26 insertions(+), 10 deletions(-) diff --git a/drivers/iio/adc/qcom-spmi-iadc.c b/drivers/iio/adc/qcom-spmi-i= adc.c index b64a8a407168..985967c85bca 100644 --- a/drivers/iio/adc/qcom-spmi-iadc.c +++ b/drivers/iio/adc/qcom-spmi-iadc.c @@ -16,6 +16,7 @@ #include #include #include +#include =20 /* IADC register and bit definition */ #define IADC_REVISION2 0x1 @@ -94,7 +95,6 @@ * struct iadc_chip - IADC Current ADC device structure. * @regmap: regmap for register read/write. * @dev: This device pointer. - * @base: base offset for the ADC peripheral. * @rsense: Values of the internal and external sense resister in micro Oh= ms. * @poll_eoc: Poll for end of conversion instead of waiting for IRQ. * @offset: Raw offset values for the internal and external channels. @@ -105,7 +105,6 @@ struct iadc_chip { struct regmap *regmap; struct device *dev; - u16 base; bool poll_eoc; u32 rsense[2]; u16 offset[2]; @@ -119,7 +118,7 @@ static int iadc_read(struct iadc_chip *iadc, u16 offset= , u8 *data) unsigned int val; int ret; =20 - ret =3D regmap_read(iadc->regmap, iadc->base + offset, &val); + ret =3D regmap_read(iadc->regmap, offset, &val); if (ret < 0) return ret; =20 @@ -129,7 +128,7 @@ static int iadc_read(struct iadc_chip *iadc, u16 offset= , u8 *data) =20 static int iadc_write(struct iadc_chip *iadc, u16 offset, u8 data) { - return regmap_write(iadc->regmap, iadc->base + offset, data); + return regmap_write(iadc->regmap, offset, data); } =20 static int iadc_reset(struct iadc_chip *iadc) @@ -270,7 +269,7 @@ static int iadc_poll_wait_eoc(struct iadc_chip *iadc, u= nsigned int interval_us) =20 static int iadc_read_result(struct iadc_chip *iadc, u16 *data) { - return regmap_bulk_read(iadc->regmap, iadc->base + IADC_DATA, data, 2); + return regmap_bulk_read(iadc->regmap, IADC_DATA, data, 2); } =20 static int iadc_do_conversion(struct iadc_chip *iadc, int chan, u16 *data) @@ -483,12 +482,22 @@ static const struct iio_chan_spec iadc_channels[] =3D= { =20 static int iadc_probe(struct platform_device *pdev) { + struct regmap_config iadc_regmap_config =3D { + .reg_bits =3D 16, + .val_bits =3D 8, + .max_register =3D 0x100, + .fast_io =3D true, + }; struct device_node *node =3D pdev->dev.of_node; struct device *dev =3D &pdev->dev; + struct spmi_subdevice *sub_sdev; + struct spmi_device *sparent; struct iio_dev *indio_dev; struct iadc_chip *iadc; int ret, irq_eoc; - u32 res; + + if (!dev->parent) + return -ENODEV; =20 indio_dev =3D devm_iio_device_alloc(dev, sizeof(*iadc)); if (!indio_dev) @@ -497,18 +506,24 @@ static int iadc_probe(struct platform_device *pdev) iadc =3D iio_priv(indio_dev); iadc->dev =3D dev; =20 - iadc->regmap =3D dev_get_regmap(dev->parent, NULL); - if (!iadc->regmap) + sparent =3D to_spmi_device(dev->parent); + if (!sparent) return -ENODEV; =20 + sub_sdev =3D devm_spmi_subdevice_alloc_and_add(dev, sparent); + if (IS_ERR(sub_sdev)) + return PTR_ERR(sub_sdev); + init_completion(&iadc->complete); mutex_init(&iadc->lock); =20 - ret =3D of_property_read_u32(node, "reg", &res); + ret =3D of_property_read_u32(node, "reg", &iadc_regmap_config.reg_base); if (ret < 0) return -ENODEV; =20 - iadc->base =3D res; + iadc->regmap =3D devm_regmap_init_spmi_ext(&sub_sdev->sdev, &iadc_regmap_= config); + if (IS_ERR(iadc->regmap)) + return PTR_ERR(iadc->regmap); =20 ret =3D iadc_version_check(iadc); if (ret < 0) @@ -584,3 +599,4 @@ MODULE_ALIAS("platform:qcom-spmi-iadc"); MODULE_DESCRIPTION("Qualcomm SPMI PMIC current ADC driver"); MODULE_LICENSE("GPL v2"); MODULE_AUTHOR("Ivan T. Ivanov "); +MODULE_IMPORT_NS("SPMI"); --=20 2.50.1