From nobody Mon Oct 6 11:53:25 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 58D6E2E0B71; Tue, 22 Jul 2025 10:13:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753179211; cv=none; b=D6jMZOR+lvHvMFBuvBMk8C/9nQrndTs0NmqG6FwY6l/6yLjVFJvuCvVHMw5ePFvQTm5H2U9I6c9kTpsDBT7cvJPVVlX2weSlFhbN/EPN1YgzTvyx0QNtdduF0AZkt5h6tAqIXHOLax+OaKzFkm0ANEnhQLmC2x45Wrl6i5kgtcM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753179211; c=relaxed/simple; bh=bo9ebHaqpjpmIYPivWIUuH66mrJ7Mn0+hVa9wGAEH7U=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=T3tX9et7fjoRCVyMfI9pbqRmNCVizDzhm7nyyVM4x5sPzCNYS7lBKLA3na9M4e/WeoDOiJyYiHEzJzWKjKWiLvdi9+NXivpP29HaKLImlex7KaoRLVEvLSz2tHn6rgPdWv3QxqDv/1h01Fxamcid3+a6caSkIt81BtkoicNZTUI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=hrPId0SU; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="hrPId0SU" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1753179207; bh=bo9ebHaqpjpmIYPivWIUuH66mrJ7Mn0+hVa9wGAEH7U=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=hrPId0SU+k0Dpvdeg79zxRa4yBetRztb3blsQX9Rr6G/hURLm4G5f5yPLe1oQ8EQI GYmhNtB2NRi2QZlZV2iDDZtrO5aA886LUSgG5oVW8ob8qXR43ESV0bHmwI7s3L6RPs qkXp4gWhjCHeAkHjXJ5UOoXG9zyILscKL5d8NEeMSO77lvLDrPUwTRsJkme33dZ+KH EL36aypMVUcHIwmRP63Dpy8ai6m7TLhkZc9sEH0oC94wLlf/ZHaebXkdQ7OzpPMrsy Irh9kFi4dcHDFJ0p7BFSGbb3DbceJMp69q3gbjHnwr5MIGfM038UDWlEY06/nWe+QG +z/VbTr5Om1Gw== Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by bali.collaboradmins.com (Postfix) with ESMTPSA id ADF4D17E1550; Tue, 22 Jul 2025 12:13:26 +0200 (CEST) From: AngeloGioacchino Del Regno To: sboyd@kernel.org Cc: jic23@kernel.org, dlechner@baylibre.com, nuno.sa@analog.com, andy@kernel.org, arnd@arndb.de, gregkh@linuxfoundation.org, srini@kernel.org, vkoul@kernel.org, kishon@kernel.org, sre@kernel.org, krzysztof.kozlowski@linaro.org, u.kleine-koenig@baylibre.com, angelogioacchino.delregno@collabora.com, linux-arm-msm@vger.kernel.org, linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-pm@vger.kernel.org, kernel@collabora.com, wenst@chromium.org, casey.connolly@linaro.org Subject: [PATCH v2 3/7] power: reset: qcom-pon: Migrate to devm_spmi_subdevice_alloc_and_add() Date: Tue, 22 Jul 2025 12:13:13 +0200 Message-ID: <20250722101317.76729-4-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20250722101317.76729-1-angelogioacchino.delregno@collabora.com> References: <20250722101317.76729-1-angelogioacchino.delregno@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Some Qualcomm PMICs integrates a Power On device supporting pwrkey and resin along with the Android reboot reason action identifier. Instead of using the parent SPMI device (the main PMIC) as a kind of syscon in this driver, register a new SPMI sub-device for PON and initialize its own regmap with this sub-device's specific base address, retrieved from the devicetree. This allows to stop manually adding the register base address to every R/W call in this driver, as this can be, and is now, handled by the regmap API instead. Signed-off-by: AngeloGioacchino Del Regno --- drivers/power/reset/qcom-pon.c | 37 ++++++++++++++++++++++++++-------- 1 file changed, 29 insertions(+), 8 deletions(-) diff --git a/drivers/power/reset/qcom-pon.c b/drivers/power/reset/qcom-pon.c index 7e108982a582..3558494aea36 100644 --- a/drivers/power/reset/qcom-pon.c +++ b/drivers/power/reset/qcom-pon.c @@ -11,6 +11,7 @@ #include #include #include +#include =20 #define PON_SOFT_RB_SPARE 0x8f =20 @@ -22,7 +23,6 @@ struct qcom_pon { struct device *dev; struct regmap *regmap; - u32 baseaddr; struct reboot_mode_driver reboot_mode; long reason_shift; }; @@ -35,7 +35,7 @@ static int qcom_pon_reboot_mode_write(struct reboot_mode_= driver *reboot, int ret; =20 ret =3D regmap_update_bits(pon->regmap, - pon->baseaddr + PON_SOFT_RB_SPARE, + PON_SOFT_RB_SPARE, GENMASK(7, pon->reason_shift), magic << pon->reason_shift); if (ret < 0) @@ -46,27 +46,47 @@ static int qcom_pon_reboot_mode_write(struct reboot_mod= e_driver *reboot, =20 static int qcom_pon_probe(struct platform_device *pdev) { + struct regmap_config qcom_pon_regmap_config =3D { + .reg_bits =3D 16, + .val_bits =3D 8, + .max_register =3D 0x100, + .fast_io =3D true, + }; + struct device *dev =3D &pdev->dev; + struct spmi_subdevice *sub_sdev; + struct spmi_device *sparent; struct qcom_pon *pon; long reason_shift; int error; =20 + if (!dev->parent) + return -ENODEV; + pon =3D devm_kzalloc(&pdev->dev, sizeof(*pon), GFP_KERNEL); if (!pon) return -ENOMEM; =20 pon->dev =3D &pdev->dev; =20 - pon->regmap =3D dev_get_regmap(pdev->dev.parent, NULL); - if (!pon->regmap) { - dev_err(&pdev->dev, "failed to locate regmap\n"); + sparent =3D to_spmi_device(dev->parent); + if (!sparent) return -ENODEV; - } =20 - error =3D of_property_read_u32(pdev->dev.of_node, "reg", - &pon->baseaddr); + sub_sdev =3D devm_spmi_subdevice_alloc_and_add(dev, sparent); + if (IS_ERR(sub_sdev)) + return PTR_ERR(sub_sdev); + + error =3D of_property_read_u32(dev->of_node, "reg", + &qcom_pon_regmap_config.reg_base); if (error) return error; =20 + pon->regmap =3D devm_regmap_init_spmi_ext(&sub_sdev->sdev, &qcom_pon_regm= ap_config); + if (!pon->regmap) { + dev_err(&pdev->dev, "failed to locate regmap\n"); + return -ENODEV; + } + reason_shift =3D (long)of_device_get_match_data(&pdev->dev); =20 if (reason_shift !=3D NO_REASON_SHIFT) { @@ -106,3 +126,4 @@ module_platform_driver(qcom_pon_driver); =20 MODULE_DESCRIPTION("Qualcomm Power On driver"); MODULE_LICENSE("GPL v2"); +MODULE_IMPORT_NS("SPMI"); --=20 2.50.1