From nobody Mon Oct 6 13:41:21 2025 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CD8AE2E040A; Tue, 22 Jul 2025 09:52:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753177924; cv=none; b=LqtTt8kqLsJqPkrafc1O/8fgvfDdpWKalYwbZCkCwF657R90kEcyeB9rxXEc7inwP+DmD3G80GloqSDExgxJoN7M6BMswmh1N7Spwbl7tJ8MPhCdoYCv1XHwMlyNYD3MJQwH1hx4IuRT2KMFsKNcYk3XKxjTPL8X68xWP1V7BAs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753177924; c=relaxed/simple; bh=jhYhDX8Y3yD3DCsIEaeAfJm+QwI1Wt1k62NbxOhbG38=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=j5yacn4oF77/QmlLSXF2HyXihMLjAFhhA9qLkUEgKiS/4Dkt9BySQf9m+2Xd2KjNDYTqxid+AjhXwzI7OoLJLX6k74rgP478oeqx4+gTokGDs5NbGpfhkaVY3EqEGOgrb7OzPujY3KKGcc5C2SBEwOMrjtaVdJk1nD0jYcQkqWk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass smtp.mailfrom=aspeedtech.com; arc=none smtp.client-ip=211.20.114.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Tue, 22 Jul 2025 17:51:56 +0800 Received: from twmbx02.aspeed.com (192.168.10.13) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Tue, 22 Jul 2025 17:51:56 +0800 From: Ryan Chen To: ryan_chen , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , Andrew Jeffery , Kevin Chen , , , , Subject: [PATCH v3 1/2] dt-bindings: interrupt-controller: aspeed: Add parent node compatibles and refine documentation Date: Tue, 22 Jul 2025 17:51:55 +0800 Message-ID: <20250722095156.1672873-2-ryan_chen@aspeedtech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250722095156.1672873-1-ryan_chen@aspeedtech.com> References: <20250722095156.1672873-1-ryan_chen@aspeedtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The AST2700 SoC contains two independent top-level interrupt controllers (INTC0 and INTC1), each responsible for handling different peripheral groups and occupying separate register spaces. Above them, PSP(CA35) GIC controller acts as the root interrupt aggregator. Accurately describing this hierarchical hardware structure in the device tree requires distinct compatible strings for the parent nodes of INTC0 and INTC1. - Adds 'aspeed,ast2700-intc0' and 'aspeed,ast2700-intc1' compatible strings for parent interrupt controller nodes. (in addition to the existing 'aspeed,ast2700-intc-ic' for child nodes) - Clarifies the relationship and function of INTC0 parent (intc0_0~x: child), INTC1 parent (intc1_0~x: child), and the GIC in the documentation. - Updates block diagrams and device tree examples to illustrate the hierarchy and compatible usage. - Refines documentation and example formatting. This change allows the device tree and driver to distinguish between parent (top-level) and child (group) interrupt controller nodes, enabling more precise driver matching SOC register space allocation. Signed-off-by: Ryan Chen --- .../aspeed,ast2700-intc.yaml | 158 +++++++++++++----- 1 file changed, 115 insertions(+), 43 deletions(-) diff --git a/Documentation/devicetree/bindings/interrupt-controller/aspeed,= ast2700-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/= aspeed,ast2700-intc.yaml index 55636d06a674..bdc4d8835843 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2700= -intc.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2700= -intc.yaml @@ -10,6 +10,33 @@ description: This interrupt controller hardware is second level interrupt controller = that is hooked to a parent interrupt controller. It's useful to combine multi= ple interrupt sources into 1 interrupt to parent interrupt controller. + Depend to which INTC0 or INTC1 used. + INTC0 and INTC1 are two kinds of interrupt controller with enable and raw + status registers for use. + INTC0 is used to assert GIC if interrupt in INTC1 asserted. + INTC1 is used to assert INTC0 if interrupt of modules asserted. + +-----+ +---------+ + | GIC |---| INTC0 | + +-----+ +---------+ + +---------+ + | |---module0 + | INTC0_0 |---module1 + | |---... + +---------+---module31 + |---.... | + +---------+ + | | +---------+ + | INTC0_11| +---| INTC1 | + | | +---------+ + +---------+ +---------+---module0 + | INTC1_0 |---module1 + | |---... + +---------+---module31 + ... + +---------+---module0 + | INTC1_5 |---module1 + | |---... + +---------+---module31 =20 maintainers: - Kevin Chen @@ -17,49 +44,70 @@ maintainers: properties: compatible: enum: - - aspeed,ast2700-intc-ic + - aspeed,ast2700-intc0 + - aspeed,ast2700-intc1 =20 reg: maxItems: 1 =20 - interrupt-controller: true + '#address-cells': + const: 2 =20 - '#interrupt-cells': + '#size-cells': const: 2 - description: - The first cell is the IRQ number, the second cell is the trigger - type as defined in interrupt.txt in this directory. - - interrupts: - maxItems: 6 - description: | - Depend to which INTC0 or INTC1 used. - INTC0 and INTC1 are two kinds of interrupt controller with enable an= d raw - status registers for use. - INTC0 is used to assert GIC if interrupt in INTC1 asserted. - INTC1 is used to assert INTC0 if interrupt of modules asserted. - +-----+ +-------+ +---------+---module0 - | GIC |---| INTC0 |--+--| INTC1_0 |---module2 - | | | | | | |---... - +-----+ +-------+ | +---------+---module31 - | - | +---------+---module0 - +---| INTC1_1 |---module2 - | | |---... - | +---------+---module31 - ... - | +---------+---module0 - +---| INTC1_5 |---module2 - | |---... - +---------+---module31 =20 + ranges: true + +patternProperties: + "^interrupt-controller@": + type: object + description: Interrupt group child nodes + additionalProperties: false + + properties: + compatible: + enum: + - aspeed,ast2700-intc-ic + + reg: + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + description: | + The first cell is the IRQ number, the second cell is the trigger + type as defined in interrupt.txt in this directory. + + interrupts: + minItems: 1 + maxItems: 6 + description: | + The interrupts provided by this interrupt controller. + + interrupts-extended: + minItems: 1 + maxItems: 6 + description: | + This property is required when defining a cascaded interrupt con= troller + that is connected under another interrupt controller. It specifi= es the + parent interrupt(s) in the upstream controller to which this con= troller + is connected. + + oneOf: + - required: [interrupts] + - required: [interrupts-extended] + + required: + - compatible + - reg + - interrupt-controller + - '#interrupt-cells' =20 required: - compatible - reg - - interrupt-controller - - '#interrupt-cells' - - interrupts =20 additionalProperties: false =20 @@ -68,19 +116,43 @@ examples: #include =20 bus { + #address-cells =3D <2>; + #size-cells =3D <2>; + + intc0: interrupt-controller@12100000 { + compatible =3D "aspeed,ast2700-intc0"; + reg =3D <0 0x12100000 0 0x4000>; + ranges =3D <0x0 0x0 0x0 0x12100000 0x0 0x4000>; + #address-cells =3D <2>; + #size-cells =3D <2>; + + intc0_11: interrupt-controller@1b00 { + compatible =3D "aspeed,ast2700-intc-ic"; + reg =3D <0 0x12101b00 0 0x10>; + #interrupt-cells =3D <2>; + interrupt-controller; + interrupts =3D , + , + , + , + , + ; + }; + }; + + intc1: interrupt-controller@14c18000 { + compatible =3D "aspeed,ast2700-intc1"; + reg =3D <0 0x14c18000 0 0x400>; + ranges =3D <0x0 0x0 0x0 0x14c18000 0x0 0x400>; #address-cells =3D <2>; #size-cells =3D <2>; =20 - interrupt-controller@12101b00 { - compatible =3D "aspeed,ast2700-intc-ic"; - reg =3D <0 0x12101b00 0 0x10>; - #interrupt-cells =3D <2>; - interrupt-controller; - interrupts =3D , - , - , - , - , - ; + intc1_0: interrupt-controller@100 { + compatible =3D "aspeed,ast2700-intc-ic"; + reg =3D <0x0 0x100 0x0 0x10>; + #interrupt-cells =3D <2>; + interrupt-controller; + interrupts-extended =3D <&intc0_11 0 (GIC_CPU_MASK_SIMPLE(4) | I= RQ_TYPE_LEVEL_HIGH)>; }; + }; }; --=20 2.34.1