From nobody Mon Oct 6 12:02:53 2025 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CD8AE2E040A; Tue, 22 Jul 2025 09:52:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753177924; cv=none; b=LqtTt8kqLsJqPkrafc1O/8fgvfDdpWKalYwbZCkCwF657R90kEcyeB9rxXEc7inwP+DmD3G80GloqSDExgxJoN7M6BMswmh1N7Spwbl7tJ8MPhCdoYCv1XHwMlyNYD3MJQwH1hx4IuRT2KMFsKNcYk3XKxjTPL8X68xWP1V7BAs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753177924; c=relaxed/simple; bh=jhYhDX8Y3yD3DCsIEaeAfJm+QwI1Wt1k62NbxOhbG38=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=j5yacn4oF77/QmlLSXF2HyXihMLjAFhhA9qLkUEgKiS/4Dkt9BySQf9m+2Xd2KjNDYTqxid+AjhXwzI7OoLJLX6k74rgP478oeqx4+gTokGDs5NbGpfhkaVY3EqEGOgrb7OzPujY3KKGcc5C2SBEwOMrjtaVdJk1nD0jYcQkqWk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass smtp.mailfrom=aspeedtech.com; arc=none smtp.client-ip=211.20.114.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Tue, 22 Jul 2025 17:51:56 +0800 Received: from twmbx02.aspeed.com (192.168.10.13) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Tue, 22 Jul 2025 17:51:56 +0800 From: Ryan Chen To: ryan_chen , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , Andrew Jeffery , Kevin Chen , , , , Subject: [PATCH v3 1/2] dt-bindings: interrupt-controller: aspeed: Add parent node compatibles and refine documentation Date: Tue, 22 Jul 2025 17:51:55 +0800 Message-ID: <20250722095156.1672873-2-ryan_chen@aspeedtech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250722095156.1672873-1-ryan_chen@aspeedtech.com> References: <20250722095156.1672873-1-ryan_chen@aspeedtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The AST2700 SoC contains two independent top-level interrupt controllers (INTC0 and INTC1), each responsible for handling different peripheral groups and occupying separate register spaces. Above them, PSP(CA35) GIC controller acts as the root interrupt aggregator. Accurately describing this hierarchical hardware structure in the device tree requires distinct compatible strings for the parent nodes of INTC0 and INTC1. - Adds 'aspeed,ast2700-intc0' and 'aspeed,ast2700-intc1' compatible strings for parent interrupt controller nodes. (in addition to the existing 'aspeed,ast2700-intc-ic' for child nodes) - Clarifies the relationship and function of INTC0 parent (intc0_0~x: child), INTC1 parent (intc1_0~x: child), and the GIC in the documentation. - Updates block diagrams and device tree examples to illustrate the hierarchy and compatible usage. - Refines documentation and example formatting. This change allows the device tree and driver to distinguish between parent (top-level) and child (group) interrupt controller nodes, enabling more precise driver matching SOC register space allocation. Signed-off-by: Ryan Chen --- .../aspeed,ast2700-intc.yaml | 158 +++++++++++++----- 1 file changed, 115 insertions(+), 43 deletions(-) diff --git a/Documentation/devicetree/bindings/interrupt-controller/aspeed,= ast2700-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/= aspeed,ast2700-intc.yaml index 55636d06a674..bdc4d8835843 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2700= -intc.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2700= -intc.yaml @@ -10,6 +10,33 @@ description: This interrupt controller hardware is second level interrupt controller = that is hooked to a parent interrupt controller. It's useful to combine multi= ple interrupt sources into 1 interrupt to parent interrupt controller. + Depend to which INTC0 or INTC1 used. + INTC0 and INTC1 are two kinds of interrupt controller with enable and raw + status registers for use. + INTC0 is used to assert GIC if interrupt in INTC1 asserted. + INTC1 is used to assert INTC0 if interrupt of modules asserted. + +-----+ +---------+ + | GIC |---| INTC0 | + +-----+ +---------+ + +---------+ + | |---module0 + | INTC0_0 |---module1 + | |---... + +---------+---module31 + |---.... | + +---------+ + | | +---------+ + | INTC0_11| +---| INTC1 | + | | +---------+ + +---------+ +---------+---module0 + | INTC1_0 |---module1 + | |---... + +---------+---module31 + ... + +---------+---module0 + | INTC1_5 |---module1 + | |---... + +---------+---module31 =20 maintainers: - Kevin Chen @@ -17,49 +44,70 @@ maintainers: properties: compatible: enum: - - aspeed,ast2700-intc-ic + - aspeed,ast2700-intc0 + - aspeed,ast2700-intc1 =20 reg: maxItems: 1 =20 - interrupt-controller: true + '#address-cells': + const: 2 =20 - '#interrupt-cells': + '#size-cells': const: 2 - description: - The first cell is the IRQ number, the second cell is the trigger - type as defined in interrupt.txt in this directory. - - interrupts: - maxItems: 6 - description: | - Depend to which INTC0 or INTC1 used. - INTC0 and INTC1 are two kinds of interrupt controller with enable an= d raw - status registers for use. - INTC0 is used to assert GIC if interrupt in INTC1 asserted. - INTC1 is used to assert INTC0 if interrupt of modules asserted. - +-----+ +-------+ +---------+---module0 - | GIC |---| INTC0 |--+--| INTC1_0 |---module2 - | | | | | | |---... - +-----+ +-------+ | +---------+---module31 - | - | +---------+---module0 - +---| INTC1_1 |---module2 - | | |---... - | +---------+---module31 - ... - | +---------+---module0 - +---| INTC1_5 |---module2 - | |---... - +---------+---module31 =20 + ranges: true + +patternProperties: + "^interrupt-controller@": + type: object + description: Interrupt group child nodes + additionalProperties: false + + properties: + compatible: + enum: + - aspeed,ast2700-intc-ic + + reg: + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + description: | + The first cell is the IRQ number, the second cell is the trigger + type as defined in interrupt.txt in this directory. + + interrupts: + minItems: 1 + maxItems: 6 + description: | + The interrupts provided by this interrupt controller. + + interrupts-extended: + minItems: 1 + maxItems: 6 + description: | + This property is required when defining a cascaded interrupt con= troller + that is connected under another interrupt controller. It specifi= es the + parent interrupt(s) in the upstream controller to which this con= troller + is connected. + + oneOf: + - required: [interrupts] + - required: [interrupts-extended] + + required: + - compatible + - reg + - interrupt-controller + - '#interrupt-cells' =20 required: - compatible - reg - - interrupt-controller - - '#interrupt-cells' - - interrupts =20 additionalProperties: false =20 @@ -68,19 +116,43 @@ examples: #include =20 bus { + #address-cells =3D <2>; + #size-cells =3D <2>; + + intc0: interrupt-controller@12100000 { + compatible =3D "aspeed,ast2700-intc0"; + reg =3D <0 0x12100000 0 0x4000>; + ranges =3D <0x0 0x0 0x0 0x12100000 0x0 0x4000>; + #address-cells =3D <2>; + #size-cells =3D <2>; + + intc0_11: interrupt-controller@1b00 { + compatible =3D "aspeed,ast2700-intc-ic"; + reg =3D <0 0x12101b00 0 0x10>; + #interrupt-cells =3D <2>; + interrupt-controller; + interrupts =3D , + , + , + , + , + ; + }; + }; + + intc1: interrupt-controller@14c18000 { + compatible =3D "aspeed,ast2700-intc1"; + reg =3D <0 0x14c18000 0 0x400>; + ranges =3D <0x0 0x0 0x0 0x14c18000 0x0 0x400>; #address-cells =3D <2>; #size-cells =3D <2>; =20 - interrupt-controller@12101b00 { - compatible =3D "aspeed,ast2700-intc-ic"; - reg =3D <0 0x12101b00 0 0x10>; - #interrupt-cells =3D <2>; - interrupt-controller; - interrupts =3D , - , - , - , - , - ; + intc1_0: interrupt-controller@100 { + compatible =3D "aspeed,ast2700-intc-ic"; + reg =3D <0x0 0x100 0x0 0x10>; + #interrupt-cells =3D <2>; + interrupt-controller; + interrupts-extended =3D <&intc0_11 0 (GIC_CPU_MASK_SIMPLE(4) | I= RQ_TYPE_LEVEL_HIGH)>; }; + }; }; --=20 2.34.1 From nobody Mon Oct 6 12:02:53 2025 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 565532E0909; Tue, 22 Jul 2025 09:52:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753177926; cv=none; b=qrltOZBrGuet0NsyDa1GPnFGQsgGaeFOiIuwsmChk6XH88ByXcwf2CoqqoqeIaOfVQZc10GKS37rj+qq4+WGAfNMZgiYYBvzOfvpo/KhL+srH0ZvwMx9ztbxauXoF/cBVK+qJmF3g7X9alrkaDyS1HRSMU65dDCkrGx/xV+zWm4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753177926; c=relaxed/simple; bh=qGb/ZkmgFjNq7T/topc1r0Q8cQ257wMI3+s1S0GrCk0=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=rqsfDnHFr1t8oA0PYaTMJ/X+sw25QuMeOScYbUlHdF+e7uvCVQhYAEf16iqrv7/hCsACEUamnfi5Rnw8I/uZEWMdCoU8LDTiW3tx3rEhH3ZpTuxbRqLiMyIOagtkMZ1YeUsyROVxRBsQ8fXmHqmbxRvgDaKuB4AN0QsU+LPQbok= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass smtp.mailfrom=aspeedtech.com; arc=none smtp.client-ip=211.20.114.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Tue, 22 Jul 2025 17:51:56 +0800 Received: from twmbx02.aspeed.com (192.168.10.13) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Tue, 22 Jul 2025 17:51:56 +0800 From: Ryan Chen To: ryan_chen , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , Andrew Jeffery , Kevin Chen , , , , Subject: [PATCH v3 2/2] irqchip: aspeed: add debugfs support and AST2700 INTC0/INTC1 routing/protection display Date: Tue, 22 Jul 2025 17:51:56 +0800 Message-ID: <20250722095156.1672873-3-ryan_chen@aspeedtech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250722095156.1672873-1-ryan_chen@aspeedtech.com> References: <20250722095156.1672873-1-ryan_chen@aspeedtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" AST2700 INTC0/INTC1 nodes ("aspeed,ast2700-intc0/1") not only include the interrupt controller child node ("aspeed,ast2700-intc-ic"), but also provide interrupt routing and register protection features. This patch adds debugfs entries for interrupt routing and protection status for AST2700 INTC0/INTC1. - Register platform driver for "aspeed,ast2700-intc0" and "aspeed,ast2700-intc1" compatible nodes. - Add show_routing/show_prot callbacks for both intc0 and intc1, displaying current interrupt routing and protection register status. - Expose routing/protection information via debugfs for debugging and validation. Signed-off-by: Ryan Chen --- drivers/irqchip/irq-aspeed-intc.c | 238 ++++++++++++++++++++++++++++++ 1 file changed, 238 insertions(+) diff --git a/drivers/irqchip/irq-aspeed-intc.c b/drivers/irqchip/irq-aspeed= -intc.c index 8330221799a0..8385f3d5f901 100644 --- a/drivers/irqchip/irq-aspeed-intc.c +++ b/drivers/irqchip/irq-aspeed-intc.c @@ -6,6 +6,7 @@ */ =20 #include +#include #include #include #include @@ -15,6 +16,13 @@ #include #include =20 +#define INTC0_ROUTING0_SEL0 0x200 +#define INTC0_ROUTING0_SEL1 0x300 +#define INTC0_ROUTING0_SEL2 0x400 +#define INTC1_ROUTING0_SEL0 0x80 +#define INTC1_ROUTING0_SEL1 0xa0 +#define INTC1_ROUTING0_SEL2 0xc0 + #define INTC_INT_ENABLE_REG 0x00 #define INTC_INT_STATUS_REG 0x04 #define INTC_IRQS_PER_WORD 32 @@ -137,3 +145,233 @@ static int __init aspeed_intc_ic_of_init(struct devic= e_node *node, } =20 IRQCHIP_DECLARE(ast2700_intc_ic, "aspeed,ast2700-intc-ic", aspeed_intc_ic_= of_init); + +struct aspeed_intc { + void __iomem *base; + struct device *dev; + struct dentry *dbg_root; + int (*show_routing)(struct seq_file *s, void *unused); + int (*show_prot)(struct seq_file *s, void *unused); +}; + +/* + * 000: Route interrupt INTn to PSP GICINT0-31 + * 001: Route interrupt INTn to SSPINT0-31 + * 010: Route interrupt INTn to TSPINT0-31 + */ +static int aspeed_intc0_show_routing(struct seq_file *s, void *unused) +{ + struct aspeed_intc *intc =3D s->private; + int group, bit; + + seq_puts(s, "int | PSP | SSP | TSP\n"); + seq_puts(s, "----+-----+-----+----\n"); + + for (group =3D 0; group < 4; group++) { + u32 reg0 =3D readl(intc->base + INTC0_ROUTING0_SEL0 + group * 4); + u32 reg1 =3D readl(intc->base + INTC0_ROUTING0_SEL1 + group * 4); + u32 reg2 =3D readl(intc->base + INTC0_ROUTING0_SEL2 + group * 4); + + for (bit =3D 0; bit < 32; bit++) { + int idx =3D group * 32 + bit; + u8 routing =3D (((reg2 >> bit) & 0x1) << 2) | + (((reg1 >> bit) & 0x1) << 1) | + (((reg0 >> bit) & 0x1) << 0); + + const char *ca35 =3D (routing =3D=3D 0) ? " O " : " - "; + const char *ssp =3D (routing =3D=3D 1) ? " O " : " - "; + const char *tsp =3D (routing =3D=3D 2) ? " O " : " - "; + + seq_printf(s, "%-4d| %s | %s | %s\n", idx, ca35, ssp, tsp); + } + } + return 0; +} + +static int aspeed_intc0_show_prot(struct seq_file *s, void *unused) +{ + struct aspeed_intc *intc =3D s->private; + u32 prot =3D readl(intc->base + 0x40); + + seq_printf(s, "INTC040 : 0x%08x\n", prot); + + static const char * const prot_bits[] =3D { + "hprot_ca35: Protect INTC010~018,1xxx accessed by PSP only", + "hprot_ssp: Protect INTC020~028,2xxx accessed by SSP only", + "hprot_tsp: Protect INTC030~038,3xxx accessed by TSP only", + "hprot_sirqs: Protect INTC0C0~0D4 to be read only", + "hprot_sirqs_1700: Protect INTC0D8~0DC to be read only", + "hprot_sirqs_ext: Protect INTC0E0 to be read only", + "hprot_reg_prot: Protect INTC044,2xx~3xx to be read only", + "hprot_rd1_prot: Read protect for INTC044,200-438", + "hprot_rd2_prot: Read protect for INTC0C0~164", + "hprot_rd3_prot: Read protect for INTC02x,1xxx to be read by PSP only", + "hprot_rd4_prot: Read protect for INTC03x,2xxx to be read by SSP only", + "hprot_rd5_prot: Read protect for INTC04x,3xxx to be read by TSP only", + "hprot_mcu0: Protect INTC050~054,028 accessed by MCU0 only", + "hprot_ca35p: Protect INTC010~018 accessed by PSP secure only" + }; + + for (int i =3D 0; i < 14; i++) + seq_printf(s, " [%2d] %s: %s\n", i, prot_bits[i], + (prot & BIT(i)) ? "Enable" : "Disable"); + return 0; +} + +/* + * 000: Route interrupt INTi to PSP(default) + * 001: Route interrupt INTi to INTC controller + * 010: Route interrupt INTi to SSP + * 011: Route interrupt INTi to TSP + * 100: Route interrupt INTi to PSP S1 + * 101: Route interrupt INTi to PSP S2 + * 110: Route interrupt INTi to MCU0 + */ +static int aspeed_intc1_show_routing(struct seq_file *s, void *unused) +{ + struct aspeed_intc *intc =3D s->private; + int group, bit; + + seq_puts(s, "index | PSP | INTC| SSP | TSP | S1 | S2 | MCU0\n"); + seq_puts(s, "-----------+-----+-----+-----+-----+-----+-----+-----\n"); + + for (group =3D 0; group < 6; group++) { + u32 reg0 =3D readl(intc->base + INTC1_ROUTING0_SEL0 + group * 4); + u32 reg1 =3D readl(intc->base + INTC1_ROUTING0_SEL1 + group * 4); + u32 reg2 =3D readl(intc->base + INTC1_ROUTING0_SEL2 + group * 4); + + for (bit =3D 0; bit < 32; bit++) { + u8 routing =3D (((reg2 >> bit) & 0x1) << 2) | + (((reg1 >> bit) & 0x1) << 1) | + (((reg0 >> bit) & 0x1) << 0); + + const char *psp =3D (routing =3D=3D 0) ? " O " : " - "; + const char *intc =3D (routing =3D=3D 1) ? " O " : " - "; + const char *ssp =3D (routing =3D=3D 2) ? " O " : " - "; + const char *tsp =3D (routing =3D=3D 3) ? " O " : " - "; + const char *s1 =3D (routing =3D=3D 4) ? " O " : " - "; + const char *s2 =3D (routing =3D=3D 5) ? " O " : " - "; + const char *mcu0 =3D (routing =3D=3D 6) ? " O " : " - "; + + seq_printf(s, "intc1_%d_%02d | %s | %s | %s | %s | %s | %s | %s\n", + group, bit, psp, intc, ssp, tsp, s1, s2, mcu0); + } + } + return 0; +} + +static int aspeed_intc1_show_prot(struct seq_file *s, void *unused) +{ + struct aspeed_intc *intc =3D s->private; + u32 prot =3D readl(intc->base); + + seq_printf(s, "INTC1: 0x%08x\n", prot); + + static const char * const prot_bits[] =3D { + "pprot_ca35: Protect INTC100~150,280~2D0,300~350 write by PSP only", + "pprot_ssp: Protect INTC180~1D0 write by SSP only", + "pprot_tsp: Protect INTC200~250 write by TSP only", + "pprot_reg_prot: Protect INTC080~0D4 to be read only", + "pprot_regrd: Protect INTC080~0D4 to be read protected", + "pprot_regrd2: Protect INTC100~150,280~2D0,300~350 read by PSP only", + "pprot_regrd3: Protect INTC180~1D0 read by SSP only", + "pprot_regrd4: Protect INTC200~250 read by TSP only", + "pprot_mcu0: Protect INTC010,014 write by MCU0 only", + "pprot_regrd5: Protect INTC010,014 read by MCU0 only", + "pprot_treg: Protect INTC040~054 to be read protected" + }; + + for (int i =3D 0; i < 11; i++) + seq_printf(s, " [%2d] %s: %s\n", i, prot_bits[i], + (prot & BIT(i)) ? "Enable" : "Disable"); + return 0; +} + +static int aspeed_intc_open_routing(struct inode *inode, struct file *file) +{ + struct aspeed_intc *intc =3D inode->i_private; + + if (!intc->show_routing) + return -ENODEV; + return single_open(file, intc->show_routing, intc); +} + +static int aspeed_intc_open_prot(struct inode *inode, struct file *file) +{ + struct aspeed_intc *intc =3D inode->i_private; + + if (!intc->show_prot) + return -ENODEV; + return single_open(file, intc->show_prot, intc); +} + +static const struct file_operations aspeed_intc_routing_fops =3D { + .owner =3D THIS_MODULE, + .open =3D aspeed_intc_open_routing, + .read =3D seq_read, + .llseek =3D seq_lseek, + .release =3D single_release, +}; + +static const struct file_operations aspeed_intc_prot_fops =3D { + .owner =3D THIS_MODULE, + .open =3D aspeed_intc_open_prot, + .read =3D seq_read, + .llseek =3D seq_lseek, + .release =3D single_release, +}; + +static int aspeed_intc_probe(struct platform_device *pdev) +{ + struct aspeed_intc *intc; + struct resource *res; + + intc =3D devm_kzalloc(&pdev->dev, sizeof(*intc), GFP_KERNEL); + if (!intc) + return -ENOMEM; + intc->dev =3D &pdev->dev; + + res =3D platform_get_resource(pdev, IORESOURCE_MEM, 0); + intc->base =3D devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(intc->base)) + return PTR_ERR(intc->base); + + if (of_device_is_compatible(pdev->dev.of_node, "aspeed,ast2700-intc0")) { + intc->show_routing =3D aspeed_intc0_show_routing; + intc->show_prot =3D aspeed_intc0_show_prot; + } else if (of_device_is_compatible(pdev->dev.of_node, "aspeed,ast2700-int= c1")) { + intc->show_routing =3D aspeed_intc1_show_routing; + intc->show_prot =3D aspeed_intc1_show_prot; + } else { + intc->show_routing =3D NULL; + intc->show_prot =3D NULL; + } + + platform_set_drvdata(pdev, intc); + + intc->dbg_root =3D debugfs_create_dir(dev_name(&pdev->dev), NULL); + if (intc->dbg_root) { + debugfs_create_file("routing", 0400, intc->dbg_root, intc, + &aspeed_intc_routing_fops); + debugfs_create_file("protection", 0400, intc->dbg_root, intc, + &aspeed_intc_prot_fops); + } + + return 0; +} + +static const struct of_device_id aspeed_intc_of_match[] =3D { + { .compatible =3D "aspeed,ast2700-intc0", }, + { .compatible =3D "aspeed,ast2700-intc1", }, + {}, +}; + +static struct platform_driver aspeed_intc_driver =3D { + .probe =3D aspeed_intc_probe, + .driver =3D { + .name =3D "ast2700-intc", + .of_match_table =3D aspeed_intc_of_match, + }, +}; +builtin_platform_driver(aspeed_intc_driver); + --=20 2.34.1