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charset="utf-8" From: Qiang Yu Add pcie3_port node to represent the PCIe bridge of PCIe3 so that PCI slot voltage rails can be described under this node in the board's dts. Signed-off-by: Qiang Yu Signed-off-by: Wenbin Yao Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/q= com/x1e80100.dtsi index 5e9a8fa3c..c9fea0402 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -3306,6 +3306,17 @@ opp-128000000 { opp-peak-kBps =3D <15753000 1>; }; }; + + pcie3_port: pcie@0 { + device_type =3D "pci"; + compatible =3D "pciclass,0604"; + reg =3D <0x0 0x0 0x0 0x0 0x0>; + bus-range =3D <0x01 0xff>; + + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges; + }; }; =20 pcie3_phy: phy@1be0000 { --=20 2.34.1