From nobody Mon Oct 6 12:06:37 2025 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BF0F52DEA7C; Tue, 22 Jul 2025 09:12:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753175535; cv=none; b=Ow2XPTMK+aBLWjX2XyQrKb66A0bKMC67K7qEB1FulAiWxN0AYwkPv1H09PD9fah5SIAVwyAitCKCAt3uGJ2E79KxQJi8eRO01O5B5bd/XG3RhLuMGxehX9ZUl2e5DJhNUaxw7eqswsGZlc/DpedlQWhWNLdKwWklVS7udj/pTDo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753175535; c=relaxed/simple; bh=VNhPpP9nTZfwcQe50UFfEyJWIJvl18Kke8oJpcNQVy0=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=AZ/zpaz4k7yGlFPVkQ/MkTbDRFJK8kZgaousnWZyqd+QEl9ZlzYqeRN9Ew0/XTbnKaSX75PGIovasrBh+IM8SWSkfYdZFlh+f3GGhpGw08kyKcrJsckkVvSNY4cidmKQ2BFGUomMhfKAw7rhHYICozffJqwvLm2HZ6sJ5dR9Ko0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=qualcomm.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=h66mzq9E; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="h66mzq9E" Received: from pps.filterd (m0279872.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 56M83bY0010113; Tue, 22 Jul 2025 09:12:02 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=qcppdkim1; bh=+zQNPUwt9X9 /JA4U4uF8w68hR2+/013zgDHQgB4OXDU=; b=h66mzq9E/YNFnClTfP0UIN/6etJ c89d5PIeL+ZoKK5D/cY4cSOG7JbL+P8NRjzIfaoHuDTUzMlL20qUmjH1LMKVouME 1ZZrBc6fGe0xbSxymQ0OdP5H7BaeuJWHNkXRncmmYFYBQLq/7dF5GDY4OFEuXkxn +uanrCIhvkBhXX65LLbcDUtYd66W7RCkM9M3vQOmL2rbpkxi0EiRJLi7wj0bX1zT wdY7TAeQYPWfUmIhG7vJcSi1IdcBAthMF+ack9VGAHHBGsU38nD4QG0fiFmplzTH 0dIgXcXGUMKml+EyTaDhlRJlWHmIh52phf9KqW7vJugLgSzwJX+T2merH1w== Received: from aptaippmta01.qualcomm.com (tpe-colo-wan-fw-bordernet.qualcomm.com [103.229.16.4]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4826t1879b-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 22 Jul 2025 09:12:02 +0000 (GMT) Received: from pps.filterd (APTAIPPMTA01.qualcomm.com [127.0.0.1]) by APTAIPPMTA01.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTP id 56M9BxLc003098; Tue, 22 Jul 2025 09:11:59 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APTAIPPMTA01.qualcomm.com (PPS) with ESMTPS id 4804em6q26-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 22 Jul 2025 09:11:59 +0000 Received: from APTAIPPMTA01.qualcomm.com (APTAIPPMTA01.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 56M9BxDX003092; Tue, 22 Jul 2025 09:11:59 GMT Received: from cbsp-sh-gv.ap.qualcomm.com (CBSP-SH-gv.ap.qualcomm.com [10.231.249.68]) by APTAIPPMTA01.qualcomm.com (PPS) with ESMTPS id 56M9BxfF003090 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 22 Jul 2025 09:11:59 +0000 Received: by cbsp-sh-gv.ap.qualcomm.com (Postfix, from userid 4635958) id 6094240D28; Tue, 22 Jul 2025 17:11:58 +0800 (CST) From: Wenbin Yao To: lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org, robh@kernel.org, bhelgaas@google.com, sfr@canb.auug.org.au, qiang.yu@oss.qualcomm.com, quic_wenbyao@quicinc.com, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, andersson@kernel.org, konradybcio@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org Cc: krishna.chundru@oss.qualcomm.com, quic_vbadigan@quicinc.com, quic_mrana@quicinc.com, quic_cang@quicinc.com Subject: [PATCH v5 1/3] PCI: dwc: enable PCI Power Control Slot driver for QCOM Date: Tue, 22 Jul 2025 17:11:49 +0800 Message-Id: <20250722091151.1423332-2-quic_wenbyao@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250722091151.1423332-1-quic_wenbyao@quicinc.com> References: <20250722091151.1423332-1-quic_wenbyao@quicinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: 5D46GenhVRAHMCI0zVlwKsj-njJwf1Mn X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzIyMDA3MyBTYWx0ZWRfX7TNh/q8+UWda 7kyOSX2KUL7HSgQLp0o6ig/Qu6r/Xir6xWoJCCa/AA/Lu38Vm1CjzKnxUDBfM2gCUnTOMlYm8ZU 50J+7GvhFrIGU6YwffU9KlK9MxXifn/+5KymiFfmrMGfvcHT6IToVgEtwygt92dWbrMqxnfp1pG RXdat5ndUv3i7n6cb8ZfkR6zXQ/JdTUQzdfOW6ZHhJ1wuyQ3iYeiLWCa+VGF6yyRKUi/mgUtJob gXSo7c/4VLfkk5lWXfiEe04xbkA2iBAl8tDbBDEcu6w1ugkaW1s24zmsjJeYBa3fNaQ5VGrUN5K XWoQ2H/poLKqIoWHfxDw2pgHM5K0jISlQgKnn8ko48h05JJIxOaud0DUvj2bf4sD56Tblz19hGy WueozI/91oNC+LEN7Hy6po7vnUo/kLDe5sIg7kcZd0ELJOpQwJ4+m4Di/ASUagFtDTvGzf3f X-Authority-Analysis: v=2.4 cv=E8/Npbdl c=1 sm=1 tr=0 ts=687f55e2 cx=c_pps a=nuhDOHQX5FNHPW3J6Bj6AA==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=Wb1JkmetP80A:10 a=EUspDBNiAAAA:8 a=COk6AnOGAAAA:8 a=Ss6HhLVMW9w6KV1y8EMA:9 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-ORIG-GUID: 5D46GenhVRAHMCI0zVlwKsj-njJwf1Mn X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-22_01,2025-07-21_02,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 malwarescore=0 spamscore=0 bulkscore=0 lowpriorityscore=0 priorityscore=1501 adultscore=0 suspectscore=0 clxscore=1011 phishscore=0 mlxlogscore=738 mlxscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507220073 Content-Type: text/plain; charset="utf-8" From: Qiang Yu Enable the pwrctrl driver, which is utilized to manage the power supplies of the devices connected to the PCI slots. This ensures that the voltage rails of the standard PCI slots on some platforms eg. X1E80100-QCP can be correctly turned on/off if they are described under PCIe port device tree node. Signed-off-by: Qiang Yu Signed-off-by: Wenbin Yao --- drivers/pci/controller/dwc/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dw= c/Kconfig index ff6b6d9e1..deafc512b 100644 --- a/drivers/pci/controller/dwc/Kconfig +++ b/drivers/pci/controller/dwc/Kconfig @@ -298,6 +298,7 @@ config PCIE_QCOM select CRC8 select PCIE_QCOM_COMMON select PCI_HOST_COMMON + select PCI_PWRCTRL_SLOT help Say Y here to enable PCIe controller support on Qualcomm SoCs. The PCIe controller uses the DesignWare core plus Qualcomm-specific --=20 2.34.1 From nobody Mon Oct 6 12:06:37 2025 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8F5DD2DCC02; Tue, 22 Jul 2025 09:12:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753175533; cv=none; b=q89F4hOlimBgHy6yu6RD6xt0Jbs7YKjO74lWdDpOtA3GSJ+5cx98bUsYMEk3N5ybFv9bbHyNfPbz3f8SEmifTK9zU0xKybKJkwM5OJSxZIjYsg32J+S4W9yEQ6XwJ6Oh5H+K41uv/4bDabBxat8mquXruF/Q6ySQyk5v6kiUa74= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753175533; c=relaxed/simple; bh=KzHam7BkSFDBK/1DVhgpDKmF9W9tSm54FAWlTeSaygU=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=ZrN5+mR18U16+iThrhSnl4SBAmFgbBSqiVEjg8s3UGUHg1ITd/vmG1PJUErn+DbWOerZ4HtpEh50qjUYteFaO7kxi06TGEMPWPyS6BnDD4WKWVpTJwyz9FGG860wWfnoqiR1jeeE/z8bNGOpdB9XFhFqcE93BZ6/meZ1fUHdaNs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=qualcomm.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=TqN5T3eM; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="TqN5T3eM" Received: from pps.filterd (m0279867.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 56M7KkUW015650; Tue, 22 Jul 2025 09:12:02 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=qcppdkim1; bh=cIRLuoCfzOX BWo70Fo1AfoQKa3KZ8R9OxpxvgV/x0Q8=; b=TqN5T3eMgbG9gF6k2yTmvUVoV55 iofdihGRZXOMYKmczJ0D33TbkBexvR5uMAMhMAVdEP3k6tsOs3miNC2ojrfsTNmK upH7qiotYok912HUrnKsiVt8ZwhkaWp9hY3d8AzNXKHPGJsUCIvxOoaCLYv1KAzC C9uC+0vdwFcZZDGJGy6/s72tu3HWqg4mgYhqc4iKKEa6e4AM/Njbu1mAKPdaKHtc KioIS30F9eHJB30ozipqW1yltr36F9zZ6O6kFtenwCL2AcKbqrgbnJYIA2YDLYsV sjvbGtI5WmCwxKe3rTq3D/5hba5TiirDWEXcWKa9/x1tt+yyu0yWvGfZa0g== Received: from aptaippmta01.qualcomm.com (tpe-colo-wan-fw-bordernet.qualcomm.com [103.229.16.4]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 481t6w1yua-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 22 Jul 2025 09:12:02 +0000 (GMT) Received: from pps.filterd (APTAIPPMTA01.qualcomm.com [127.0.0.1]) by APTAIPPMTA01.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTP id 56M9C0jr003114; Tue, 22 Jul 2025 09:12:00 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APTAIPPMTA01.qualcomm.com (PPS) with ESMTPS id 4804em6q2e-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 22 Jul 2025 09:12:00 +0000 Received: from APTAIPPMTA01.qualcomm.com (APTAIPPMTA01.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 56M9C0GW003105; Tue, 22 Jul 2025 09:12:00 GMT Received: from cbsp-sh-gv.ap.qualcomm.com (CBSP-SH-gv.ap.qualcomm.com [10.231.249.68]) by APTAIPPMTA01.qualcomm.com (PPS) with ESMTPS id 56M9C075003104 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 22 Jul 2025 09:12:00 +0000 Received: by cbsp-sh-gv.ap.qualcomm.com (Postfix, from userid 4635958) id 5933240D2E; Tue, 22 Jul 2025 17:11:59 +0800 (CST) From: Wenbin Yao To: lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org, robh@kernel.org, bhelgaas@google.com, sfr@canb.auug.org.au, qiang.yu@oss.qualcomm.com, quic_wenbyao@quicinc.com, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, andersson@kernel.org, konradybcio@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org Cc: krishna.chundru@oss.qualcomm.com, quic_vbadigan@quicinc.com, quic_mrana@quicinc.com, quic_cang@quicinc.com, Konrad Dybcio Subject: [PATCH v5 2/3] arm64: dts: qcom: x1e80100: add bus topology for PCIe domain 3 Date: Tue, 22 Jul 2025 17:11:50 +0800 Message-Id: <20250722091151.1423332-3-quic_wenbyao@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250722091151.1423332-1-quic_wenbyao@quicinc.com> References: <20250722091151.1423332-1-quic_wenbyao@quicinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Authority-Analysis: v=2.4 cv=SPpCVPvH c=1 sm=1 tr=0 ts=687f55e2 cx=c_pps a=nuhDOHQX5FNHPW3J6Bj6AA==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=Wb1JkmetP80A:10 a=EUspDBNiAAAA:8 a=COk6AnOGAAAA:8 a=ZDVFxM84AbWdf4itxYgA:9 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzIyMDA3NSBTYWx0ZWRfXyJctrKfMbmvQ cHIRYdgLwjv6N/VPHbn/UrOzOILYkxjC/fLchb38gN/C5cdt4po5+vFS+Tyl98Lb3Jhgo8haL+I 7GjZC17rS1qvbIDJbwurC7v5o0dozLeNGP+IvCkY3olM3q0KPlAWOsToJeACTPNQQIYGIuAq96Y 3vM+z5aXDwa8aKR98suKqn+2O2Z9QMpqdSFtooK/TAEz21rG3ygo8EwYPb0PGFd4ZbfxtT1oJFt uRIPUF0o976KXE3It6NUVCj1Z3cpL8+Aaimuy+dlrk5D+TgHhk+kHMg2A3FYO1yEtwl5tG8S9p9 q/tCnGt0UgRAWXicXM9HXjPWsMjsLogOcXtJEQqkmLhr4+U+K4s1JJbvwxpgNY2hqEYygFdMOc6 itcFs9TJhG1qtnXI/bpZUfnVsfv4fTHm6jnrJ1LKt7ngG2AVoENtuJsHhn8XNf9CsTonsdz7 X-Proofpoint-ORIG-GUID: CTUwAWWVG23YO-iatw8_JFKIuzIec9PA X-Proofpoint-GUID: CTUwAWWVG23YO-iatw8_JFKIuzIec9PA X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-22_01,2025-07-21_02,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=0 adultscore=0 phishscore=0 malwarescore=0 mlxscore=0 bulkscore=0 clxscore=1011 priorityscore=1501 impostorscore=0 lowpriorityscore=0 mlxlogscore=922 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507220075 Content-Type: text/plain; charset="utf-8" From: Qiang Yu Add pcie3_port node to represent the PCIe bridge of PCIe3 so that PCI slot voltage rails can be described under this node in the board's dts. Signed-off-by: Qiang Yu Signed-off-by: Wenbin Yao Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/q= com/x1e80100.dtsi index 5e9a8fa3c..c9fea0402 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -3306,6 +3306,17 @@ opp-128000000 { opp-peak-kBps =3D <15753000 1>; }; }; + + pcie3_port: pcie@0 { + device_type =3D "pci"; + compatible =3D "pciclass,0604"; + reg =3D <0x0 0x0 0x0 0x0 0x0>; + bus-range =3D <0x01 0xff>; + + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges; + }; }; =20 pcie3_phy: phy@1be0000 { --=20 2.34.1 From nobody Mon Oct 6 12:06:37 2025 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A1A682DC33F; Tue, 22 Jul 2025 09:12:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753175537; cv=none; b=VAxUruPkI425wC2e9ITBOAfwJuKSg77Q/rU+CBdAWMfLm41ZyyjkC0i6Bad96sFU9WhycZty5vCgIB+Zb/EYIEa9G+rgUlU3fcvp7yT4rEC10V41PnI/xeCTx2m108qQR+HDnWOLUQHFmNuNxqEzu3dzoIAYw/KsOpc9xh1OqqA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753175537; c=relaxed/simple; bh=6l1b7InLD/CO33AXqnUGPVR6oq5wTfk704YDcX5Oxxw=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=EZveseNk9bgOG39Psed14skNdhkyFHWTCZFFhFEQh29hI6YoHsraj3b/iUBSvsD+0xBBL/BpuB4++JCpGnCknorBmn7rsGSoBwz9MNdzfLg1O210T5evKUJ8cBYRfhqkrRB7sgRK6n1PkFwidGTe9fVL9MLLia5D8t11JN/uBnM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=qualcomm.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=SzVKdjg4; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="SzVKdjg4" Received: from pps.filterd (m0279865.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 56M7WdWu009373; Tue, 22 Jul 2025 09:12:04 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=qcppdkim1; bh=jGU4UszTVjl 07iZLTGJkGYdlRfex/TCVBYWysgVcCd8=; b=SzVKdjg4bWVQV31RejnegVX1PMk PMk6Hi0LtfEiqdQAZ7nmc0ParxfzOb13PUXtdb8uaeH1v2+dhDsJI+cgp3gd10G5 T4BjLgteo7N6BnUvhlCJXVUFcey4PIKcR8K84DfekwZaluJNLFGDMbif3aTHHyLQ ensXp2dU+j8ntGkTHGod1NdsubhAglxyduGDAagl0LOnyrLy6KBz5YHds5g/Ea6D QwAn5jgVEKtoeLi297IQFdnSmv6shDpqDuJ3heSzEMSGIp4nDLclB7CNXWZvl8/m w6/j75JgjCGtV96FB/JiuW9ERFMPcKyldGxOMraM8XThWDc0+I0p6xy7myw== Received: from aptaippmta02.qualcomm.com (tpe-colo-wan-fw-bordernet.qualcomm.com [103.229.16.4]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 48045vy6um-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 22 Jul 2025 09:12:04 +0000 (GMT) Received: from pps.filterd (APTAIPPMTA02.qualcomm.com [127.0.0.1]) by APTAIPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTP id 56M9C2q8028242; Tue, 22 Jul 2025 09:12:02 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APTAIPPMTA02.qualcomm.com (PPS) with ESMTPS id 4804em6vqv-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 22 Jul 2025 09:12:02 +0000 Received: from APTAIPPMTA02.qualcomm.com (APTAIPPMTA02.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 56M9C15i028229; Tue, 22 Jul 2025 09:12:02 GMT Received: from cbsp-sh-gv.ap.qualcomm.com (CBSP-SH-gv.ap.qualcomm.com [10.231.249.68]) by APTAIPPMTA02.qualcomm.com (PPS) with ESMTPS id 56M9C1aW028212 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 22 Jul 2025 09:12:01 +0000 Received: by cbsp-sh-gv.ap.qualcomm.com (Postfix, from userid 4635958) id 9538B40D28; Tue, 22 Jul 2025 17:12:00 +0800 (CST) From: Wenbin Yao To: lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org, robh@kernel.org, bhelgaas@google.com, sfr@canb.auug.org.au, qiang.yu@oss.qualcomm.com, quic_wenbyao@quicinc.com, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, andersson@kernel.org, konradybcio@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org Cc: krishna.chundru@oss.qualcomm.com, quic_vbadigan@quicinc.com, quic_mrana@quicinc.com, quic_cang@quicinc.com, Konrad Dybcio Subject: [PATCH v5 3/3] arm64: dts: qcom: x1e80100-qcp: enable pcie3 x8 slot for X1E80100-QCP Date: Tue, 22 Jul 2025 17:11:51 +0800 Message-Id: <20250722091151.1423332-4-quic_wenbyao@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250722091151.1423332-1-quic_wenbyao@quicinc.com> References: <20250722091151.1423332-1-quic_wenbyao@quicinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Authority-Analysis: v=2.4 cv=LL1mQIW9 c=1 sm=1 tr=0 ts=687f55e4 cx=c_pps a=nuhDOHQX5FNHPW3J6Bj6AA==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=Wb1JkmetP80A:10 a=EUspDBNiAAAA:8 a=COk6AnOGAAAA:8 a=I4_V4ABcpVmACwlpt_QA:9 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-GUID: t3NXWUxDLtnjKOFrKloTpIu8AYpNJ5kI X-Proofpoint-ORIG-GUID: t3NXWUxDLtnjKOFrKloTpIu8AYpNJ5kI X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzIyMDA3NSBTYWx0ZWRfX33nhxujHZd5R UhW6Yair9D4HsMKS3jYVeej7m7vetsvaHCmNE4IzqFm2d4jC83V2cKIGqXSixZH6q5j8lmtjApN IWi/nTz5C3oHtS7bBRooN6H1Q9a/JNgnICdjnu1m6VFAmSwfxyCrsOK+Q8k2pakh1w3KXBjMzVs hB3yCsc9HKE73kpgUX0x7s79fOvNb+yACacWfRMZbi6vzOYfAqzgMNkz1RtcBbhtO26WqFs1sGy d3J4bK2cf0VoQBhyh4IFvaM2kSCxZPnwjfUsLnZQJ8zU28uRQwy+12jS6zH7bDrhxs5bV5xuGk4 6rP3CTmyO7qZevlrJS9ClGukT3nQjLXoIFHoVURPn1pG2DlsC2MNwoIjWjZJ8ikA7KZoEpKvnxu ZSZL8fKhBBn0x9Xukc8JgpYGksXccM5losEhI9AU82B0tJRbK5fZCiEb9tBrPjbxVFKcc8S3 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-22_01,2025-07-21_02,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 mlxlogscore=878 clxscore=1011 mlxscore=0 adultscore=0 suspectscore=0 spamscore=0 malwarescore=0 impostorscore=0 bulkscore=0 lowpriorityscore=0 phishscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507220075 Content-Type: text/plain; charset="utf-8" From: Qiang Yu Add perst, wake and clkreq sideband signals and required regulators in PCIe3 controller and PHY device tree node. Describe the voltage rails of the x8 PCI slots for PCIe3 port. Signed-off-by: Qiang Yu Signed-off-by: Wenbin Yao Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/x1e80100-qcp.dts | 118 ++++++++++++++++++++++ 1 file changed, 118 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts b/arch/arm64/boot/dt= s/qcom/x1e80100-qcp.dts index 4dfba835a..71c44e37a 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts @@ -318,6 +318,48 @@ vreg_wcn_3p3: regulator-wcn-3p3 { regulator-boot-on; }; =20 + vreg_pcie_12v: regulator-pcie-12v { + compatible =3D "regulator-fixed"; + + regulator-name =3D "VREG_PCIE_12V"; + regulator-min-microvolt =3D <12000000>; + regulator-max-microvolt =3D <12000000>; + + gpio =3D <&pm8550ve_8_gpios 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 =3D <&pcie_x8_12v>; + pinctrl-names =3D "default"; + }; + + vreg_pcie_3v3_aux: regulator-pcie-3v3-aux { + compatible =3D "regulator-fixed"; + + regulator-name =3D "VREG_PCIE_3P3_AUX"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + + gpio =3D <&pmc8380_3_gpios 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 =3D <&pm_sde7_aux_3p3_en>; + pinctrl-names =3D "default"; + }; + + vreg_pcie_3v3: regulator-pcie-3v3 { + compatible =3D "regulator-fixed"; + + regulator-name =3D "VREG_PCIE_3P3"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + + gpio =3D <&pmc8380_3_gpios 6 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 =3D <&pm_sde7_main_3p3_en>; + pinctrl-names =3D "default"; +}; + usb-1-ss0-sbu-mux { compatible =3D "onnn,fsusb42", "gpio-sbu-mux"; =20 @@ -908,6 +950,59 @@ &mdss_dp3_phy { status =3D "okay"; }; =20 +&pm8550ve_8_gpios { + pcie_x8_12v: pcie-12v-default-state { + pins =3D "gpio8"; + function =3D "normal"; + output-enable; + output-high; + bias-pull-down; + power-source =3D <0>; + }; +}; + +&pmc8380_3_gpios { + pm_sde7_aux_3p3_en: pcie-aux-3p3-default-state { + pins =3D "gpio8"; + function =3D "normal"; + output-enable; + output-high; + bias-pull-down; + power-source =3D <0>; + }; + + pm_sde7_main_3p3_en: pcie-main-3p3-default-state { + pins =3D "gpio6"; + function =3D "normal"; + output-enable; + output-high; + bias-pull-down; + power-source =3D <0>; + }; +}; + +&pcie3 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pcie3_default>; + perst-gpios =3D <&tlmm 143 GPIO_ACTIVE_LOW>; + wake-gpios =3D <&tlmm 145 GPIO_ACTIVE_LOW>; + + status =3D "okay"; +}; + +&pcie3_phy { + vdda-phy-supply =3D <&vreg_l3c_0p8>; + vdda-pll-supply =3D <&vreg_l3e_1p2>; + + status =3D "okay"; +}; + +&pcie3_port { + vpcie12v-supply =3D <&vreg_pcie_12v>; + vpcie3v3-supply =3D <&vreg_pcie_3v3>; + vpcie3v3aux-supply =3D <&vreg_pcie_3v3_aux>; +}; + &pcie4 { perst-gpios =3D <&tlmm 146 GPIO_ACTIVE_LOW>; wake-gpios =3D <&tlmm 148 GPIO_ACTIVE_LOW>; @@ -1119,6 +1214,29 @@ nvme_reg_en: nvme-reg-en-state { bias-disable; }; =20 + pcie3_default: pcie3-default-state { + clkreq-n-pins { + pins =3D "gpio144"; + function =3D "pcie3_clk"; + drive-strength =3D <2>; + bias-pull-up; + }; + + perst-n-pins { + pins =3D "gpio143"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-down; + }; + + wake-n-pins { + pins =3D "gpio145"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-up; + }; + }; + pcie4_default: pcie4-default-state { clkreq-n-pins { pins =3D "gpio147"; --=20 2.34.1