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charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: nalasex01b.na.qualcomm.com (10.47.209.197) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Authority-Analysis: v=2.4 cv=SPpCVPvH c=1 sm=1 tr=0 ts=687f485a cx=c_pps a=ouPCqIW2jiPt+lZRy3xVPw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=3H110R4YSZwA:10 a=IkcTkHD0fZMA:10 a=Wb1JkmetP80A:10 a=COk6AnOGAAAA:8 a=vK_ggAcass-lWF-AxbsA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzIyMDA2NyBTYWx0ZWRfX2kz+7m+/gFh9 78HibWokufBWiemeQT67W8tnsdvW8I2tneaEJZE7ryS8K1xy56oaH+bL7J95K2g6/JFCCTeN2gd kw3+YMjDQ8eMl9m9+MRj+wR8t/rYSjQGZEF4SSLNZlrZRrJ0Zx2M+yFBX+IJIM++gpqtA+DoSf+ ly7+/l2Pl/kH/kq1RnAqtXG3U8IKU2HiuJ1aGE8nIAllImwgVoZfj/m38wsheNBtlc4aMCgkI4i Wnkj4/Eridtsli/SarFsXb5rf0DmnJEOrABhXIMl/lOmg3Kn9KUd6DXGOFUcWiRJ9DDlg/nuFYe oXo4WnGXkdCfpTbS7BOPObs9zClO1qcRWXrgD6PHrxRPxb/9Yb7qU4i/oQREsBW4GDPckP9sye1 U9wzH+LD3RMNGy4BnSPBIVmRoAPInxbLvHr+kfwKX9eBH7vSE/G8yXvI6Q9dAwNtBJsvgFWn X-Proofpoint-ORIG-GUID: IMj0WeNmIRWUAXRk2es5tRz6NtirI6V1 X-Proofpoint-GUID: IMj0WeNmIRWUAXRk2es5tRz6NtirI6V1 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-22_01,2025-07-21_02,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=0 adultscore=0 phishscore=0 malwarescore=0 mlxscore=0 bulkscore=0 clxscore=1015 priorityscore=1501 impostorscore=0 lowpriorityscore=0 mlxlogscore=999 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507220067 From: Yingchao Deng The QCOM extended CTI is a heavily parameterized version of ARM=E2=80=99s C= SCTI. It allows a debugger to send to trigger events to a processor or to send a trigger event to one or more processors when a trigger event occurs on another processor on the same SoC, or even between SoCs. For Qualcomm extended CTI, it supports up to 128 triggers. Signed-off-by: Yingchao Deng Signed-off-by: Mao Jinlong --- .../hwtracing/coresight/coresight-cti-core.c | 127 +++++++++++++---- .../coresight/coresight-cti-platform.c | 16 ++- .../hwtracing/coresight/coresight-cti-sysfs.c | 128 ++++++++++++++---- drivers/hwtracing/coresight/coresight-cti.h | 75 +++++----- 4 files changed, 245 insertions(+), 101 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-cti-core.c b/drivers/hwt= racing/coresight/coresight-cti-core.c index 8fb30dd73fd2..d6a28df48484 100644 --- a/drivers/hwtracing/coresight/coresight-cti-core.c +++ b/drivers/hwtracing/coresight/coresight-cti-core.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -22,6 +23,54 @@ #include "coresight-priv.h" #include "coresight-cti.h" =20 +#define CTI_EXTENDED "qcom,coresight-cti-extended" + +static const int cti_normal_offset[] =3D { + [CTIINTACK] =3D 0x010, + [CTIAPPSET] =3D 0x014, + [CTIAPPCLEAR] =3D 0x018, + [CTIAPPPULSE] =3D 0x01C, + [CTIINEN] =3D 0x020, + [CTIOUTEN] =3D 0x0A0, + [CTITRIGINSTATUS] =3D 0x130, + [CTITRIGOUTSTATUS] =3D 0x134, + [CTICHINSTATUS] =3D 0x138, + [CTICHOUTSTATUS] =3D 0x13C, + [CTIGATE] =3D 0x140, + [ASICCTL] =3D 0x144, + [ITCHINACK] =3D 0xEDC, + [ITTRIGINACK] =3D 0xEE0, + [ITCHOUT] =3D 0xEE4, + [ITTRIGOUT] =3D 0xEE8, + [ITCHOUTACK] =3D 0xEEC, + [ITTRIGOUTACK] =3D 0xEF0, + [ITCHIN] =3D 0xEF4, + [ITTRIGIN] =3D 0xEF8, +}; + +static const int cti_extended_offset[] =3D { + [CTIINTACK] =3D 0x020, + [CTIAPPSET] =3D 0x004, + [CTIAPPCLEAR] =3D 0x008, + [CTIAPPPULSE] =3D 0x00C, + [CTIINEN] =3D 0x400, + [CTIOUTEN] =3D 0x800, + [CTITRIGINSTATUS] =3D 0x040, + [CTITRIGOUTSTATUS] =3D 0x060, + [CTICHINSTATUS] =3D 0x080, + [CTICHOUTSTATUS] =3D 0x084, + [CTIGATE] =3D 0x088, + [ASICCTL] =3D 0x08c, + [ITCHINACK] =3D 0xE70, + [ITTRIGINACK] =3D 0xE80, + [ITCHOUT] =3D 0xE74, + [ITTRIGOUT] =3D 0xEA0, + [ITCHOUTACK] =3D 0xE78, + [ITTRIGOUTACK] =3D 0xEC0, + [ITCHIN] =3D 0xE7C, + [ITTRIGIN] =3D 0xEE0, +}; + /* * CTI devices can be associated with a PE, or be connected to CoreSight * hardware. We have a list of all CTIs irrespective of CPU bound or @@ -57,6 +106,12 @@ static struct cti_drvdata *cti_cpu_drvdata[NR_CPUS]; */ DEFINE_CORESIGHT_DEVLIST(cti_sys_devs, "cti_sys"); =20 +u32 cti_offset(struct cti_drvdata *drvdata, int index, int num) +{ + return (drvdata->is_extended_cti ? cti_extended_offset[index] + : cti_normal_offset[index]) + (4 * num); +} + /* write set of regs to hardware - call with spinlock claimed */ void cti_write_all_hw_regs(struct cti_drvdata *drvdata) { @@ -70,15 +125,15 @@ void cti_write_all_hw_regs(struct cti_drvdata *drvdata) =20 /* write the CTI trigger registers */ for (i =3D 0; i < config->nr_trig_max; i++) { - writel_relaxed(config->ctiinen[i], drvdata->base + CTIINEN(i)); + writel_relaxed(config->ctiinen[i], drvdata->base + cti_offset(drvdata, C= TIINEN, i)); writel_relaxed(config->ctiouten[i], - drvdata->base + CTIOUTEN(i)); + drvdata->base + cti_offset(drvdata, CTIOUTEN, i)); } =20 /* other regs */ - writel_relaxed(config->ctigate, drvdata->base + CTIGATE); - writel_relaxed(config->asicctl, drvdata->base + ASICCTL); - writel_relaxed(config->ctiappset, drvdata->base + CTIAPPSET); + writel_relaxed(config->ctigate, drvdata->base + cti_offset(drvdata, CTIGA= TE, 0)); + writel_relaxed(config->asicctl, drvdata->base + cti_offset(drvdata, ASICC= TL, 0)); + writel_relaxed(config->ctiappset, drvdata->base + cti_offset(drvdata, CTI= APPSET, 0)); =20 /* re-enable CTI */ writel_relaxed(1, drvdata->base + CTICONTROL); @@ -99,10 +154,13 @@ static int cti_enable_hw(struct cti_drvdata *drvdata) if (config->hw_enabled || !config->hw_powered) goto cti_state_unchanged; =20 - /* claim the device */ - rc =3D coresight_claim_device(drvdata->csdev); - if (rc) - goto cti_err_not_enabled; + /* There is no relationship between the CLR and SET pair for extended CTI= . */ + if (!drvdata->is_extended_cti) { + /* claim the device */ + rc =3D coresight_claim_device(drvdata->csdev); + if (rc) + goto cti_err_not_enabled; + } =20 cti_write_all_hw_regs(drvdata); =20 @@ -175,7 +233,8 @@ static int cti_disable_hw(struct cti_drvdata *drvdata) writel_relaxed(0, drvdata->base + CTICONTROL); config->hw_enabled =3D false; =20 - coresight_disclaim_device_unlocked(csdev); + if (!drvdata->is_extended_cti) + coresight_disclaim_device_unlocked(csdev); CS_LOCK(drvdata->base); raw_spin_unlock(&drvdata->spinlock); return ret; @@ -270,8 +329,10 @@ int cti_add_connection_entry(struct device *dev, struc= t cti_drvdata *drvdata, cti_dev->nr_trig_con++; =20 /* add connection usage bit info to overall info */ - drvdata->config.trig_in_use |=3D tc->con_in->used_mask; - drvdata->config.trig_out_use |=3D tc->con_out->used_mask; + bitmap_or(drvdata->config.trig_in_use, drvdata->config.trig_in_use, + tc->con_in->used_mask, drvdata->config.nr_trig_max); + bitmap_or(drvdata->config.trig_out_use, drvdata->config.trig_out_use, + tc->con_out->used_mask, drvdata->config.nr_trig_max); =20 return 0; } @@ -314,7 +375,6 @@ int cti_add_default_connection(struct device *dev, stru= ct cti_drvdata *drvdata) { int ret =3D 0; int n_trigs =3D drvdata->config.nr_trig_max; - u32 n_trig_mask =3D GENMASK(n_trigs - 1, 0); struct cti_trig_con *tc =3D NULL; =20 /* @@ -325,8 +385,9 @@ int cti_add_default_connection(struct device *dev, stru= ct cti_drvdata *drvdata) if (!tc) return -ENOMEM; =20 - tc->con_in->used_mask =3D n_trig_mask; - tc->con_out->used_mask =3D n_trig_mask; + bitmap_fill(tc->con_in->used_mask, n_trigs); + bitmap_fill(tc->con_out->used_mask, n_trigs); + ret =3D cti_add_connection_entry(dev, drvdata, tc, NULL, "default"); return ret; } @@ -339,7 +400,6 @@ int cti_channel_trig_op(struct device *dev, enum cti_ch= an_op op, { struct cti_drvdata *drvdata =3D dev_get_drvdata(dev->parent); struct cti_config *config =3D &drvdata->config; - u32 trig_bitmask; u32 chan_bitmask; u32 reg_value; int reg_offset; @@ -349,25 +409,23 @@ int cti_channel_trig_op(struct device *dev, enum cti_= chan_op op, (trigger_idx >=3D config->nr_trig_max)) return -EINVAL; =20 - trig_bitmask =3D BIT(trigger_idx); - /* ensure registered triggers and not out filtered */ if (direction =3D=3D CTI_TRIG_IN) { - if (!(trig_bitmask & config->trig_in_use)) + if (!(test_bit(trigger_idx, config->trig_in_use))) return -EINVAL; } else { - if (!(trig_bitmask & config->trig_out_use)) + if (!(test_bit(trigger_idx, config->trig_out_use))) return -EINVAL; =20 if ((config->trig_filter_enable) && - (config->trig_out_filter & trig_bitmask)) + test_bit(trigger_idx, config->trig_out_filter)) return -EINVAL; } =20 /* update the local register values */ chan_bitmask =3D BIT(channel_idx); - reg_offset =3D (direction =3D=3D CTI_TRIG_IN ? CTIINEN(trigger_idx) : - CTIOUTEN(trigger_idx)); + reg_offset =3D (direction =3D=3D CTI_TRIG_IN ? cti_offset(drvdata, CTIINE= N, trigger_idx) : + cti_offset(drvdata, CTIOUTEN, trigger_idx)); =20 raw_spin_lock(&drvdata->spinlock); =20 @@ -451,19 +509,19 @@ int cti_channel_setop(struct device *dev, enum cti_ch= an_set_op op, case CTI_CHAN_SET: config->ctiappset |=3D chan_bitmask; reg_value =3D config->ctiappset; - reg_offset =3D CTIAPPSET; + reg_offset =3D cti_offset(drvdata, CTIAPPSET, 0); break; =20 case CTI_CHAN_CLR: config->ctiappset &=3D ~chan_bitmask; reg_value =3D chan_bitmask; - reg_offset =3D CTIAPPCLEAR; + reg_offset =3D cti_offset(drvdata, CTIAPPCLEAR, 0); break; =20 case CTI_CHAN_PULSE: config->ctiappset &=3D ~chan_bitmask; reg_value =3D chan_bitmask; - reg_offset =3D CTIAPPPULSE; + reg_offset =3D cti_offset(drvdata, CTIAPPPULSE, 0); break; =20 default: @@ -857,6 +915,19 @@ static void cti_remove(struct amba_device *adev) coresight_unregister(drvdata->csdev); } =20 +static bool of_is_extended_cti(struct device *dev) +{ + struct fwnode_handle *fwnode =3D dev_fwnode(dev); + + if (is_of_node(fwnode)) { + if (of_device_is_compatible(to_of_node(fwnode), + CTI_EXTENDED)) + return true; + } + + return false; +} + static int cti_probe(struct amba_device *adev, const struct amba_id *id) { int ret =3D 0; @@ -950,9 +1021,11 @@ static int cti_probe(struct amba_device *adev, const = struct amba_id *id) drvdata->csdev_release =3D drvdata->csdev->dev.release; drvdata->csdev->dev.release =3D cti_device_release; =20 + drvdata->is_extended_cti =3D of_is_extended_cti(dev); + /* all done - dec pm refcount */ pm_runtime_put(&adev->dev); - dev_info(&drvdata->csdev->dev, "CTI initialized\n"); + dev_info(&drvdata->csdev->dev, "CTI initialized %d\n", drvdata->is_extend= ed_cti); return 0; =20 pm_release: diff --git a/drivers/hwtracing/coresight/coresight-cti-platform.c b/drivers= /hwtracing/coresight/coresight-cti-platform.c index d0ae10bf6128..4bef860a0484 100644 --- a/drivers/hwtracing/coresight/coresight-cti-platform.c +++ b/drivers/hwtracing/coresight/coresight-cti-platform.c @@ -136,8 +136,8 @@ static int cti_plat_create_v8_etm_connection(struct dev= ice *dev, goto create_v8_etm_out; =20 /* build connection data */ - tc->con_in->used_mask =3D 0xF0; /* sigs <4,5,6,7> */ - tc->con_out->used_mask =3D 0xF0; /* sigs <4,5,6,7> */ + bitmap_set(tc->con_in->used_mask, 4, 4); /* sigs <4,5,6,7> */ + bitmap_set(tc->con_out->used_mask, 4, 4); /* sigs <4,5,6,7> */ =20 /* * The EXTOUT type signals from the ETM are connected to a set of input @@ -194,10 +194,10 @@ static int cti_plat_create_v8_connections(struct devi= ce *dev, goto of_create_v8_out; =20 /* Set the v8 PE CTI connection data */ - tc->con_in->used_mask =3D 0x3; /* sigs <0 1> */ + bitmap_set(tc->con_in->used_mask, 0, 2); /* sigs <0 1> */ tc->con_in->sig_types[0] =3D PE_DBGTRIGGER; tc->con_in->sig_types[1] =3D PE_PMUIRQ; - tc->con_out->used_mask =3D 0x7; /* sigs <0 1 2 > */ + bitmap_set(tc->con_out->used_mask, 0, 3); /* sigs <0 1 2 > */ tc->con_out->sig_types[0] =3D PE_EDBGREQ; tc->con_out->sig_types[1] =3D PE_DBGRESTART; tc->con_out->sig_types[2] =3D PE_CTIIRQ; @@ -213,7 +213,7 @@ static int cti_plat_create_v8_connections(struct device= *dev, goto of_create_v8_out; =20 /* filter pe_edbgreq - PE trigout sig <0> */ - drvdata->config.trig_out_filter |=3D 0x1; + set_bit(0, drvdata->config.trig_out_filter); =20 of_create_v8_out: return ret; @@ -257,7 +257,7 @@ static int cti_plat_read_trig_group(struct cti_trig_grp= *tgrp, if (!err) { /* set the signal usage mask */ for (idx =3D 0; idx < tgrp->nr_sigs; idx++) - tgrp->used_mask |=3D BIT(values[idx]); + set_bit(values[idx], tgrp->used_mask); } =20 kfree(values); @@ -331,7 +331,9 @@ static int cti_plat_process_filter_sigs(struct cti_drvd= ata *drvdata, =20 err =3D cti_plat_read_trig_group(tg, fwnode, CTI_DT_FILTER_OUT_SIGS); if (!err) - drvdata->config.trig_out_filter |=3D tg->used_mask; + bitmap_or(drvdata->config.trig_out_filter, + drvdata->config.trig_out_filter, + tg->used_mask, drvdata->config.nr_trig_max); =20 kfree(tg); return err; diff --git a/drivers/hwtracing/coresight/coresight-cti-sysfs.c b/drivers/hw= tracing/coresight/coresight-cti-sysfs.c index 572b80ee96fb..cc680a4b900a 100644 --- a/drivers/hwtracing/coresight/coresight-cti-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-cti-sysfs.c @@ -172,9 +172,8 @@ static struct attribute *coresight_cti_attrs[] =3D { =20 /* register based attributes */ =20 -/* Read registers with power check only (no enable check). */ -static ssize_t coresight_cti_reg_show(struct device *dev, - struct device_attribute *attr, char *buf) +static ssize_t coresight_cti_mgmt_reg_show(struct device *dev, + struct device_attribute *attr, char *buf) { struct cti_drvdata *drvdata =3D dev_get_drvdata(dev->parent); struct cs_off_attribute *cti_attr =3D container_of(attr, struct cs_off_at= tribute, attr); @@ -189,6 +188,53 @@ static ssize_t coresight_cti_reg_show(struct device *d= ev, return sysfs_emit(buf, "0x%x\n", val); } =20 +/* Read registers with power check only (no enable check). */ +static ssize_t coresight_cti_reg_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct cti_drvdata *drvdata =3D dev_get_drvdata(dev->parent); + struct cs_off_attribute *cti_attr =3D container_of(attr, struct cs_off_at= tribute, attr); + struct cti_config *cfg =3D &drvdata->config; + u32 val =3D 0; + int i, num; + ssize_t size =3D 0; + + pm_runtime_get_sync(dev->parent); + raw_spin_lock(&drvdata->spinlock); + if (drvdata->config.hw_powered) { + switch (cti_attr->off) { + case CTICHINSTATUS: + case CTICHOUTSTATUS: + case ITCHINACK: + case ITCHOUT: + case ITCHOUTACK: + case ITCHIN: + val =3D readl_relaxed(drvdata->base + cti_offset(drvdata, cti_attr->off= , 0)); + size +=3D sysfs_emit(buf, "0x%x\n", val); + break; + + case CTITRIGINSTATUS: + case CTITRIGOUTSTATUS: + case ITTRIGINACK: + case ITTRIGOUT: + case ITTRIGOUTACK: + case ITTRIGIN: + num =3D (cfg->nr_trig_max - 1) / 32; + for (i =3D 0; i <=3D num; i++) { + val =3D readl_relaxed(drvdata->base + + cti_offset(drvdata, cti_attr->off, i)); + size +=3D sysfs_emit_at(buf, size, "0x%x ", val); + } + if (size > 0) + buf[size - 1] =3D '\n'; + break; + } + } + raw_spin_unlock(&drvdata->spinlock); + pm_runtime_put_sync(dev->parent); + return size; +} + /* Write registers with power check only (no enable check). */ static __maybe_unused ssize_t coresight_cti_reg_store(struct device *dev, struct device_attribute *attr, @@ -197,19 +243,45 @@ static __maybe_unused ssize_t coresight_cti_reg_store= (struct device *dev, struct cti_drvdata *drvdata =3D dev_get_drvdata(dev->parent); struct cs_off_attribute *cti_attr =3D container_of(attr, struct cs_off_at= tribute, attr); unsigned long val =3D 0; + int num, i; =20 if (kstrtoul(buf, 0, &val)) return -EINVAL; =20 pm_runtime_get_sync(dev->parent); raw_spin_lock(&drvdata->spinlock); - if (drvdata->config.hw_powered) - cti_write_single_reg(drvdata, cti_attr->off, val); + if (drvdata->config.hw_powered) { + switch (cti_attr->off) { + case ITCHINACK: + case ITCHOUT: + cti_write_single_reg(drvdata, cti_offset(drvdata, cti_attr->off, 0), va= l); + break; + + case ITTRIGINACK: + case ITTRIGOUT: + case ITTRIGOUTACK: + num =3D val / 32; + i =3D val % 32; + for (i =3D 0; i <=3D num; i++) + cti_write_single_reg(drvdata, + cti_offset(drvdata, cti_attr->off, i), BIT(i)); + break; + } + } + raw_spin_unlock(&drvdata->spinlock); pm_runtime_put_sync(dev->parent); return size; } =20 +#define coresight_cti_mgmt_reg(name, offset) = \ + (&((struct cs_off_attribute[]) { \ + { \ + __ATTR(name, 0444, coresight_cti_mgmt_reg_show, NULL), \ + offset \ + } \ + })[0].attr.attr) + #define coresight_cti_reg(name, offset) \ (&((struct cs_off_attribute[]) { \ { \ @@ -237,17 +309,17 @@ static __maybe_unused ssize_t coresight_cti_reg_store= (struct device *dev, =20 /* coresight management registers */ static struct attribute *coresight_cti_mgmt_attrs[] =3D { - coresight_cti_reg(devaff0, CTIDEVAFF0), - coresight_cti_reg(devaff1, CTIDEVAFF1), - coresight_cti_reg(authstatus, CORESIGHT_AUTHSTATUS), - coresight_cti_reg(devarch, CORESIGHT_DEVARCH), - coresight_cti_reg(devid, CORESIGHT_DEVID), - coresight_cti_reg(devtype, CORESIGHT_DEVTYPE), - coresight_cti_reg(pidr0, CORESIGHT_PERIPHIDR0), - coresight_cti_reg(pidr1, CORESIGHT_PERIPHIDR1), - coresight_cti_reg(pidr2, CORESIGHT_PERIPHIDR2), - coresight_cti_reg(pidr3, CORESIGHT_PERIPHIDR3), - coresight_cti_reg(pidr4, CORESIGHT_PERIPHIDR4), + coresight_cti_mgmt_reg(devaff0, CTIDEVAFF0), + coresight_cti_mgmt_reg(devaff1, CTIDEVAFF1), + coresight_cti_mgmt_reg(authstatus, CORESIGHT_AUTHSTATUS), + coresight_cti_mgmt_reg(devarch, CORESIGHT_DEVARCH), + coresight_cti_mgmt_reg(devid, CORESIGHT_DEVID), + coresight_cti_mgmt_reg(devtype, CORESIGHT_DEVTYPE), + coresight_cti_mgmt_reg(pidr0, CORESIGHT_PERIPHIDR0), + coresight_cti_mgmt_reg(pidr1, CORESIGHT_PERIPHIDR1), + coresight_cti_mgmt_reg(pidr2, CORESIGHT_PERIPHIDR2), + coresight_cti_mgmt_reg(pidr3, CORESIGHT_PERIPHIDR3), + coresight_cti_mgmt_reg(pidr4, CORESIGHT_PERIPHIDR4), NULL, }; =20 @@ -284,11 +356,12 @@ static ssize_t cti_reg32_show(struct device *dev, cha= r *buf, * if reg_offset >=3D 0 then write through if enabled. */ static ssize_t cti_reg32_store(struct device *dev, const char *buf, - size_t size, u32 *pcached_val, int reg_offset) + size_t size, u32 *pcached_val, int index) { unsigned long val; struct cti_drvdata *drvdata =3D dev_get_drvdata(dev->parent); struct cti_config *config =3D &drvdata->config; + int reg_offset; =20 if (kstrtoul(buf, 0, &val)) return -EINVAL; @@ -298,6 +371,7 @@ static ssize_t cti_reg32_store(struct device *dev, cons= t char *buf, if (pcached_val) *pcached_val =3D (u32)val; =20 + reg_offset =3D cti_offset(drvdata, index, 0); /* write through if offset and enabled */ if ((reg_offset >=3D 0) && cti_active(config)) cti_write_single_reg(drvdata, reg_offset, val); @@ -306,14 +380,14 @@ static ssize_t cti_reg32_store(struct device *dev, co= nst char *buf, } =20 /* Standard macro for simple rw cti config registers */ -#define cti_config_reg32_rw(name, cfgname, offset) \ +#define cti_config_reg32_rw(name, cfgname, index) \ static ssize_t name##_show(struct device *dev, \ struct device_attribute *attr, \ char *buf) \ { \ struct cti_drvdata *drvdata =3D dev_get_drvdata(dev->parent); \ return cti_reg32_show(dev, buf, \ - &drvdata->config.cfgname, offset); \ + &drvdata->config.cfgname, index); \ } \ \ static ssize_t name##_store(struct device *dev, \ @@ -322,7 +396,7 @@ static ssize_t name##_store(struct device *dev, \ { \ struct cti_drvdata *drvdata =3D dev_get_drvdata(dev->parent); \ return cti_reg32_store(dev, buf, size, \ - &drvdata->config.cfgname, offset); \ + &drvdata->config.cfgname, index); \ } \ static DEVICE_ATTR_RW(name) =20 @@ -389,7 +463,7 @@ static ssize_t inen_store(struct device *dev, =20 /* write through if enabled */ if (cti_active(config)) - cti_write_single_reg(drvdata, CTIINEN(index), val); + cti_write_single_reg(drvdata, cti_offset(drvdata, CTIINEN, index), val); raw_spin_unlock(&drvdata->spinlock); return size; } @@ -428,7 +502,7 @@ static ssize_t outen_store(struct device *dev, =20 /* write through if enabled */ if (cti_active(config)) - cti_write_single_reg(drvdata, CTIOUTEN(index), val); + cti_write_single_reg(drvdata, cti_offset(drvdata, CTIOUTEN, index), val); raw_spin_unlock(&drvdata->spinlock); return size; } @@ -711,10 +785,8 @@ static ssize_t trigout_filtered_show(struct device *de= v, struct cti_drvdata *drvdata =3D dev_get_drvdata(dev->parent); struct cti_config *cfg =3D &drvdata->config; int size =3D 0, nr_trig_max =3D cfg->nr_trig_max; - unsigned long mask =3D cfg->trig_out_filter; =20 - if (mask) - size =3D bitmap_print_to_pagebuf(true, buf, &mask, nr_trig_max); + size =3D bitmap_print_to_pagebuf(true, buf, cfg->trig_out_filter, nr_trig= _max); return size; } static DEVICE_ATTR_RO(trigout_filtered); @@ -926,9 +998,8 @@ static ssize_t trigin_sig_show(struct device *dev, struct cti_trig_con *con =3D (struct cti_trig_con *)ext_attr->var; struct cti_drvdata *drvdata =3D dev_get_drvdata(dev->parent); struct cti_config *cfg =3D &drvdata->config; - unsigned long mask =3D con->con_in->used_mask; =20 - return bitmap_print_to_pagebuf(true, buf, &mask, cfg->nr_trig_max); + return bitmap_print_to_pagebuf(true, buf, con->con_in->used_mask, cfg->nr= _trig_max); } =20 static ssize_t trigout_sig_show(struct device *dev, @@ -940,9 +1011,8 @@ static ssize_t trigout_sig_show(struct device *dev, struct cti_trig_con *con =3D (struct cti_trig_con *)ext_attr->var; struct cti_drvdata *drvdata =3D dev_get_drvdata(dev->parent); struct cti_config *cfg =3D &drvdata->config; - unsigned long mask =3D con->con_out->used_mask; =20 - return bitmap_print_to_pagebuf(true, buf, &mask, cfg->nr_trig_max); + return bitmap_print_to_pagebuf(true, buf, con->con_out->used_mask, cfg->n= r_trig_max); } =20 /* convert a sig type id to a name */ diff --git a/drivers/hwtracing/coresight/coresight-cti.h b/drivers/hwtracin= g/coresight/coresight-cti.h index 8362a47c939c..7d052e76d116 100644 --- a/drivers/hwtracing/coresight/coresight-cti.h +++ b/drivers/hwtracing/coresight/coresight-cti.h @@ -18,46 +18,42 @@ =20 struct fwnode_handle; =20 -/* - * Device registers - * 0x000 - 0x144: CTI programming and status - * 0xEDC - 0xEF8: CTI integration test. - * 0xF00 - 0xFFC: Coresight management registers. - */ -/* CTI programming registers */ -#define CTICONTROL 0x000 -#define CTIINTACK 0x010 -#define CTIAPPSET 0x014 -#define CTIAPPCLEAR 0x018 -#define CTIAPPPULSE 0x01C -#define CTIINEN(n) (0x020 + (4 * n)) -#define CTIOUTEN(n) (0x0A0 + (4 * n)) -#define CTITRIGINSTATUS 0x130 -#define CTITRIGOUTSTATUS 0x134 -#define CTICHINSTATUS 0x138 -#define CTICHOUTSTATUS 0x13C -#define CTIGATE 0x140 -#define ASICCTL 0x144 -/* Integration test registers */ -#define ITCHINACK 0xEDC /* WO CTI CSSoc 400 only*/ -#define ITTRIGINACK 0xEE0 /* WO CTI CSSoc 400 only*/ -#define ITCHOUT 0xEE4 /* WO RW-600 */ -#define ITTRIGOUT 0xEE8 /* WO RW-600 */ -#define ITCHOUTACK 0xEEC /* RO CTI CSSoc 400 only*/ -#define ITTRIGOUTACK 0xEF0 /* RO CTI CSSoc 400 only*/ -#define ITCHIN 0xEF4 /* RO */ -#define ITTRIGIN 0xEF8 /* RO */ -/* management registers */ -#define CTIDEVAFF0 0xFA8 -#define CTIDEVAFF1 0xFAC - /* * CTI CSSoc 600 has a max of 32 trigger signals per direction. * CTI CSSoc 400 has 8 IO triggers - other CTIs can be impl def. * Max of in and out defined in the DEVID register. * - pick up actual number used from .dts parameters if present. */ -#define CTIINOUTEN_MAX 32 +#define CTIINOUTEN_MAX 128 + +#define CTICONTROL 0x000 + +/* management registers */ +#define CTIDEVAFF0 0xFA8 +#define CTIDEVAFF1 0xFAC + +enum cti_offset_index { + CTIINTACK, + CTIAPPSET, + CTIAPPCLEAR, + CTIAPPPULSE, + CTIINEN, + CTIOUTEN, + CTITRIGINSTATUS, + CTITRIGOUTSTATUS, + CTICHINSTATUS, + CTICHOUTSTATUS, + CTIGATE, + ASICCTL, + ITCHINACK, + ITTRIGINACK, + ITCHOUT, + ITTRIGOUT, + ITCHOUTACK, + ITTRIGOUTACK, + ITCHIN, + ITTRIGIN, +}; =20 /** * Group of related trigger signals @@ -68,7 +64,7 @@ struct fwnode_handle; */ struct cti_trig_grp { int nr_sigs; - u32 used_mask; + DECLARE_BITMAP(used_mask, CTIINOUTEN_MAX); int sig_types[]; }; =20 @@ -147,9 +143,10 @@ struct cti_config { bool hw_powered; =20 /* registered triggers and filtering */ - u32 trig_in_use; - u32 trig_out_use; - u32 trig_out_filter; + DECLARE_BITMAP(trig_in_use, CTIINOUTEN_MAX); + DECLARE_BITMAP(trig_out_use, CTIINOUTEN_MAX); + DECLARE_BITMAP(trig_out_filter, CTIINOUTEN_MAX); + bool trig_filter_enable; u8 xtrig_rchan_sel; =20 @@ -180,6 +177,7 @@ struct cti_drvdata { struct cti_config config; struct list_head node; void (*csdev_release)(struct device *dev); + bool is_extended_cti; }; =20 /* @@ -232,6 +230,7 @@ int cti_create_cons_sysfs(struct device *dev, struct ct= i_drvdata *drvdata); struct coresight_platform_data * coresight_cti_get_platform_data(struct device *dev); const char *cti_plat_get_node_name(struct fwnode_handle *fwnode); +u32 cti_offset(struct cti_drvdata *drvdata, int index, int num); =20 /* cti powered and enabled */ static inline bool cti_active(struct cti_config *cfg) --=20 2.25.1