From nobody Mon Oct 6 12:02:53 2025 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DC45B191493; Tue, 22 Jul 2025 01:31:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753147893; cv=none; b=NH9uoVwparCUvlXKYp5oDnv7D6WogEBr4BRZb8pBWJ88U+511mmzPpMjsj7orl4R1FE8t/pnQZqaLQXCr12NW9I9PMtWxz45EcVSLuPsAB6z73Y61/No+uT0JjVJgy8Ba8Uw1FJYV9szFWW08OIWRFSylwLr5Bcz84uq2ymh1rM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753147893; c=relaxed/simple; bh=0CK9F2DV0mEKQY7orzMUVKoGEI8dBukCtuZke0pxzHo=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=tiuwqv6Yr+XHz1NW/ShJOBLnvfFfX0ZLf54TSfbnjUTIvcMRqzc6VZjnMr5z1tKUdtsoGD6TLKohPbiD0CDib2iyBN6A4Ky79ubDv//y9rC4faiSCyabTxeIFFtGk8mlwCh7Ql3o7xokiTr39iFa1TIpP6OZf96kSX3lyNQEEVs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass smtp.mailfrom=aspeedtech.com; arc=none smtp.client-ip=211.20.114.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Tue, 22 Jul 2025 09:31:18 +0800 Received: from mail.aspeedtech.com (192.168.10.13) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Tue, 22 Jul 2025 09:31:18 +0800 From: Jammy Huang To: , , , , , , , , , CC: Krzysztof Kozlowski Subject: [PATCH v7 1/2] dt-bindings: mailbox: Add ASPEED AST2700 series SoC Date: Tue, 22 Jul 2025 09:31:16 +0800 Message-ID: <20250722013117.2561025-2-jammy_huang@aspeedtech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250722013117.2561025-1-jammy_huang@aspeedtech.com> References: <20250722013117.2561025-1-jammy_huang@aspeedtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Introduce the mailbox module for AST27XX series SoC, which is responsible for interchanging messages between asymmetric processors. Signed-off-by: Jammy Huang Reviewed-by: Krzysztof Kozlowski Reviewed-by: Andrew Jeffery --- .../mailbox/aspeed,ast2700-mailbox.yaml | 68 +++++++++++++++++++ 1 file changed, 68 insertions(+) create mode 100644 Documentation/devicetree/bindings/mailbox/aspeed,ast270= 0-mailbox.yaml diff --git a/Documentation/devicetree/bindings/mailbox/aspeed,ast2700-mailb= ox.yaml b/Documentation/devicetree/bindings/mailbox/aspeed,ast2700-mailbox.= yaml new file mode 100644 index 000000000000..600e2d63fccd --- /dev/null +++ b/Documentation/devicetree/bindings/mailbox/aspeed,ast2700-mailbox.yaml @@ -0,0 +1,68 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mailbox/aspeed,ast2700-mailbox.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ASPEED AST2700 mailbox controller + +maintainers: + - Jammy Huang + +description: > + ASPEED AST2700 has multiple processors that need to communicate with each + other. The mailbox controller provides a way for these processors to send + messages to each other. It is a hardware-based inter-processor communica= tion + mechanism that allows processors to send and receive messages through + dedicated channels. + + The mailbox's tx/rx are independent, meaning that one processor can send= a + message while another processor is receiving a message simultaneously. + There are 4 channels available for both tx and rx operations. Each chann= el + has a FIFO buffer that can hold messages of a fixed size (32 bytes in th= is + case). + + The mailbox controller also supports interrupt generation, allowing + processors to notify each other when a message is available or when an e= vent + occurs. + +properties: + compatible: + const: aspeed,ast2700-mailbox + + reg: + items: + - description: TX control register + - description: RX control register + + reg-names: + items: + - const: tx + - const: rx + + interrupts: + maxItems: 1 + + "#mbox-cells": + const: 1 + +required: + - compatible + - reg + - reg-names + - interrupts + - "#mbox-cells" + +additionalProperties: false + +examples: + - | + #include + + mailbox@12c1c200 { + compatible =3D "aspeed,ast2700-mailbox"; + reg =3D <0x12c1c200 0x100>, <0x12c1c300 0x100>; + reg-names =3D "tx", "rx"; + interrupts =3D ; + #mbox-cells =3D <1>; + }; --=20 2.25.1 From nobody Mon Oct 6 12:02:53 2025 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AB6AA1AF0C1; Tue, 22 Jul 2025 01:31:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753147895; cv=none; b=TBhyVEpL2FiC4E8GTGc14oYim6fxFU4oA+K5FoOy/JAZlSzT4M4oSknv9YuiEIc/7P35CuSL65JOTbRHDF+IRqkXumjZ6iCLUIOFyNv3eDc3W1nPYscVvXv6HZyM6r/LgxvX96ayK3/0wb0N0bEvScHxCJIIESSdxM6/9he8Ra0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753147895; c=relaxed/simple; bh=eBifDu0QCFPNhZyiYU102NqNlOWT+PjBWEKTGUaNvus=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=VBTF/J+6ZQCs43YOz1CguRXQsL6Sc+c13QqpZQDRD4ya3+YjPcNhChOv2WuX5lpgcl/mXomhoWx0kr7Nws6UD5/eplXOUD98Z0rjc+/jW6ErcMos3Ue5FJ4xrtACqit/5HwGBlXlpj1cw7yu9jZeQzyfPRzs4C1bo42a6bGn74Y= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass smtp.mailfrom=aspeedtech.com; arc=none smtp.client-ip=211.20.114.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Tue, 22 Jul 2025 09:31:18 +0800 Received: from mail.aspeedtech.com (192.168.10.13) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Tue, 22 Jul 2025 09:31:18 +0800 From: Jammy Huang To: , , , , , , , , , Subject: [PATCH v7 2/2] mailbox: aspeed: add mailbox driver for AST27XX series SoC Date: Tue, 22 Jul 2025 09:31:17 +0800 Message-ID: <20250722013117.2561025-3-jammy_huang@aspeedtech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250722013117.2561025-1-jammy_huang@aspeedtech.com> References: <20250722013117.2561025-1-jammy_huang@aspeedtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add mailbox controller driver for AST27XX SoCs, which provides independent tx/rx mailbox between different processors. There are 4 channels for each tx/rx mailbox and each channel has an 32-byte FIFO. Signed-off-by: Jammy Huang Reviewed-by: Andrew Jeffery --- drivers/mailbox/Kconfig | 8 + drivers/mailbox/Makefile | 2 + drivers/mailbox/ast2700-mailbox.c | 235 ++++++++++++++++++++++++++++++ 3 files changed, 245 insertions(+) create mode 100644 drivers/mailbox/ast2700-mailbox.c diff --git a/drivers/mailbox/Kconfig b/drivers/mailbox/Kconfig index 68eeed660a4a..1c38cd570091 100644 --- a/drivers/mailbox/Kconfig +++ b/drivers/mailbox/Kconfig @@ -340,4 +340,12 @@ config THEAD_TH1520_MBOX kernel is running, and E902 core used for power management among other things. =20 +config AST2700_MBOX + tristate "ASPEED AST2700 IPC driver" + depends on ARCH_ASPEED || COMPILE_TEST + help + Mailbox driver implementation for ASPEED AST27XX SoCs. This driver + can be used to send message between different processors in SoC. + The driver provides mailbox support for sending interrupts to the + clients. Say Y here if you want to build this driver. endif diff --git a/drivers/mailbox/Makefile b/drivers/mailbox/Makefile index 13a3448b3271..9a9add9a7548 100644 --- a/drivers/mailbox/Makefile +++ b/drivers/mailbox/Makefile @@ -72,3 +72,5 @@ obj-$(CONFIG_QCOM_CPUCP_MBOX) +=3D qcom-cpucp-mbox.o obj-$(CONFIG_QCOM_IPCC) +=3D qcom-ipcc.o =20 obj-$(CONFIG_THEAD_TH1520_MBOX) +=3D mailbox-th1520.o + +obj-$(CONFIG_AST2700_MBOX) +=3D ast2700-mailbox.o diff --git a/drivers/mailbox/ast2700-mailbox.c b/drivers/mailbox/ast2700-ma= ilbox.c new file mode 100644 index 000000000000..080fb02c917c --- /dev/null +++ b/drivers/mailbox/ast2700-mailbox.c @@ -0,0 +1,235 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright Aspeed Technology Inc. (C) 2025. All rights reserved + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Each bit in the register represents an IPC ID */ +#define IPCR_TX_TRIG 0x00 +#define IPCR_ENABLE 0x04 +#define IPCR_STATUS 0x08 +#define RX_IRQ(n) BIT(n) +#define RX_IRQ_MASK 0xf +#define IPCR_DATA 0x10 + +struct ast2700_mbox_data { + u8 num_chans; + u8 msg_size; +}; + +struct ast2700_mbox { + struct mbox_controller mbox; + u8 msg_size; + void __iomem *tx_regs; + void __iomem *rx_regs; + spinlock_t lock; +}; + +static inline int ch_num(struct mbox_chan *chan) +{ + return chan - chan->mbox->chans; +} + +static inline bool ast2700_mbox_tx_done(struct ast2700_mbox *mb, int idx) +{ + return !(readl(mb->tx_regs + IPCR_STATUS) & BIT(idx)); +} + +static irqreturn_t ast2700_mbox_irq(int irq, void *p) +{ + struct ast2700_mbox *mb =3D p; + void __iomem *data_reg; + int num_words =3D mb->msg_size / sizeof(u32); + u32 *word_data; + u32 status; + int n, i; + + /* Only examine channels that are currently enabled. */ + status =3D readl(mb->rx_regs + IPCR_ENABLE) & + readl(mb->rx_regs + IPCR_STATUS); + + if (!(status & RX_IRQ_MASK)) + return IRQ_NONE; + + for (n =3D 0; n < mb->mbox.num_chans; ++n) { + struct mbox_chan *chan =3D &mb->mbox.chans[n]; + + if (!(status & RX_IRQ(n))) + continue; + + data_reg =3D mb->rx_regs + IPCR_DATA + mb->msg_size * n; + word_data =3D chan->con_priv; + /* Read the message data */ + for (i =3D 0; i < num_words; i++) + word_data[i] =3D readl(data_reg + i * sizeof(u32)); + + mbox_chan_received_data(chan, chan->con_priv); + + /* The IRQ can be cleared only once the FIFO is empty. */ + writel(RX_IRQ(n), mb->rx_regs + IPCR_STATUS); + } + + return IRQ_HANDLED; +} + +static int ast2700_mbox_send_data(struct mbox_chan *chan, void *data) +{ + struct ast2700_mbox *mb =3D dev_get_drvdata(chan->mbox->dev); + int idx =3D ch_num(chan); + void __iomem *data_reg =3D mb->tx_regs + IPCR_DATA + mb->msg_size * idx; + u32 *word_data =3D data; + int num_words =3D mb->msg_size / sizeof(u32); + int i; + + if (!(readl(mb->tx_regs + IPCR_ENABLE) & BIT(idx))) { + dev_warn(mb->mbox.dev, "%s: Ch-%d not enabled yet\n", __func__, idx); + return -ENODEV; + } + + if (!(ast2700_mbox_tx_done(mb, idx))) { + dev_warn(mb->mbox.dev, "%s: Ch-%d last data has not finished\n", __func_= _, idx); + return -EBUSY; + } + + /* Write the message data */ + for (i =3D 0 ; i < num_words; i++) + writel(word_data[i], data_reg + i * sizeof(u32)); + + writel(BIT(idx), mb->tx_regs + IPCR_TX_TRIG); + dev_dbg(mb->mbox.dev, "%s: Ch-%d sent\n", __func__, idx); + + return 0; +} + +static int ast2700_mbox_startup(struct mbox_chan *chan) +{ + struct ast2700_mbox *mb =3D dev_get_drvdata(chan->mbox->dev); + int idx =3D ch_num(chan); + void __iomem *reg =3D mb->rx_regs + IPCR_ENABLE; + unsigned long flags; + + spin_lock_irqsave(&mb->lock, flags); + writel(readl(reg) | BIT(idx), reg); + spin_unlock_irqrestore(&mb->lock, flags); + + return 0; +} + +static void ast2700_mbox_shutdown(struct mbox_chan *chan) +{ + struct ast2700_mbox *mb =3D dev_get_drvdata(chan->mbox->dev); + int idx =3D ch_num(chan); + void __iomem *reg =3D mb->rx_regs + IPCR_ENABLE; + unsigned long flags; + + spin_lock_irqsave(&mb->lock, flags); + writel(readl(reg) & ~BIT(idx), reg); + spin_unlock_irqrestore(&mb->lock, flags); +} + +static bool ast2700_mbox_last_tx_done(struct mbox_chan *chan) +{ + struct ast2700_mbox *mb =3D dev_get_drvdata(chan->mbox->dev); + int idx =3D ch_num(chan); + + return ast2700_mbox_tx_done(mb, idx); +} + +static const struct mbox_chan_ops ast2700_mbox_chan_ops =3D { + .send_data =3D ast2700_mbox_send_data, + .startup =3D ast2700_mbox_startup, + .shutdown =3D ast2700_mbox_shutdown, + .last_tx_done =3D ast2700_mbox_last_tx_done, +}; + +static int ast2700_mbox_probe(struct platform_device *pdev) +{ + struct ast2700_mbox *mb; + const struct ast2700_mbox_data *dev_data; + struct device *dev =3D &pdev->dev; + int irq, ret; + + if (!pdev->dev.of_node) + return -ENODEV; + + dev_data =3D device_get_match_data(&pdev->dev); + + mb =3D devm_kzalloc(dev, sizeof(*mb), GFP_KERNEL); + if (!mb) + return -ENOMEM; + + mb->mbox.chans =3D devm_kcalloc(&pdev->dev, dev_data->num_chans, + sizeof(*mb->mbox.chans), GFP_KERNEL); + if (!mb->mbox.chans) + return -ENOMEM; + + /* con_priv of each channel is used to store the message received */ + for (int i =3D 0; i < dev_data->num_chans; i++) { + mb->mbox.chans[i].con_priv =3D devm_kcalloc(dev, dev_data->msg_size, + sizeof(u8), GFP_KERNEL); + if (!mb->mbox.chans[i].con_priv) + return -ENOMEM; + } + + platform_set_drvdata(pdev, mb); + + mb->tx_regs =3D devm_platform_ioremap_resource_byname(pdev, "tx"); + if (IS_ERR(mb->tx_regs)) + return PTR_ERR(mb->tx_regs); + + mb->rx_regs =3D devm_platform_ioremap_resource_byname(pdev, "rx"); + if (IS_ERR(mb->rx_regs)) + return PTR_ERR(mb->rx_regs); + + mb->msg_size =3D dev_data->msg_size; + mb->mbox.dev =3D dev; + mb->mbox.num_chans =3D dev_data->num_chans; + mb->mbox.ops =3D &ast2700_mbox_chan_ops; + mb->mbox.txdone_irq =3D false; + mb->mbox.txdone_poll =3D true; + mb->mbox.txpoll_period =3D 5; + spin_lock_init(&mb->lock); + + irq =3D platform_get_irq(pdev, 0); + if (irq < 0) + return irq; + + ret =3D devm_request_irq(dev, irq, ast2700_mbox_irq, 0, dev_name(dev), mb= ); + if (ret) + return ret; + + return devm_mbox_controller_register(dev, &mb->mbox); +} + +static const struct ast2700_mbox_data ast2700_dev_data =3D { + .num_chans =3D 4, + .msg_size =3D 0x20, +}; + +static const struct of_device_id ast2700_mbox_of_match[] =3D { + { .compatible =3D "aspeed,ast2700-mailbox", .data =3D &ast2700_dev_data }, + {} +}; +MODULE_DEVICE_TABLE(of, ast2700_mbox_of_match); + +static struct platform_driver ast2700_mbox_driver =3D { + .driver =3D { + .name =3D "ast2700-mailbox", + .of_match_table =3D ast2700_mbox_of_match, + }, + .probe =3D ast2700_mbox_probe, +}; +module_platform_driver(ast2700_mbox_driver); + +MODULE_AUTHOR("Jammy Huang "); +MODULE_DESCRIPTION("ASPEED AST2700 IPC driver"); +MODULE_LICENSE("GPL"); --=20 2.25.1