From nobody Mon Oct 6 10:17:30 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2893628A1D7; Tue, 22 Jul 2025 15:09:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753196949; cv=none; b=iCtIajG6V0YiBepVYSoT6LgO38wdoNk4Q+BuraIGoeJbECux9E+uQ+n8v32TrsOONwxDCBph4miANe0kl3roQZrF4/X66Zpi1XR02HpK15O4PkwUkeTjwn7tUXj+zkk/C9R+Dd919755EVyF3fVvwIx/sExiluZE4F1yqUCQxak= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753196949; c=relaxed/simple; bh=CLMpKrTrD+1F6YeWwuDcqlirxHopHnUHK3PKeL3Qewc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=eWfQyXmS4pViDvqh+a+Y8ZMdepCUivFXDhYMjKHYeOgeQ8o3HSr2izpFIFeZldA705PE7MAinw1aL1idyyK+r2SWkz5cgUfI4PgPbqs7wJP61u69o3kU912xkhG2LHVux4xh6ZsMx0U4YnBP2wXpWR/ETid1tHwFf/RzcQaWCrA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=eh/ay8Vm; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="eh/ay8Vm" Received: by smtp.kernel.org (Postfix) with ESMTPS id BD9C1C4CEF9; Tue, 22 Jul 2025 15:09:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1753196948; bh=CLMpKrTrD+1F6YeWwuDcqlirxHopHnUHK3PKeL3Qewc=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=eh/ay8VmDClXb6knEPquAy5/Krjf4p0QvRmg6gQWzoFFgn90iy7e1TgMU+nDTMose jYqnWrTQW2rWrVOKeene5q4/VOhfm3VdtvChfP0HGoVoZmaPA/bo2AvYP8izJ6mwao +POfVAqdW9k0TRweRXP8//VPc0vnFx8SBm7hxZTHENZlFI1IZHFERFwbG5S5laPhcF bPR7LNyUUX+t3sGEQZCDdIPc63FNu9kPUu0jcCp/+d0PBAkPEWRDHf/eYGFAHmcEyz G3BkhIvBsSVHAMQpJa51eVIM/bcku0V6lYX0Z/hCVvAr22YzAJoEJ13OGoKA20lHgw q5OlZHUfNB04w== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id AD74CC83F34; Tue, 22 Jul 2025 15:09:08 +0000 (UTC) From: Mahesh Rao via B4 Relay Date: Tue, 22 Jul 2025 23:07:51 +0800 Subject: [PATCH 1/4] dt-bindings: firmware: Add interrupt specification for Intel Stratix 10 Service Layer. Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250722-sip_svc_irq-v1-1-c5b9e02c1ce6@altera.com> References: <20250722-sip_svc_irq-v1-0-c5b9e02c1ce6@altera.com> In-Reply-To: <20250722-sip_svc_irq-v1-0-c5b9e02c1ce6@altera.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Dinh Nguyen Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Mahesh Rao , Matthew Gerlach X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1753196946; l=1851; i=mahesh.rao@altera.com; s=20250107; h=from:subject:message-id; bh=AOemBCgdL+N65O4/Not6GZwfFLWHmbGOTOms8z2w2Jo=; b=NbU81/Kx0NOw/5Nc2eINlzrxJM3M1WUTSRcu0kjIxI++A2pZ/D2r/TRDQFRk5X8JvxWgphsvx jjqdKA8jlVHDEmxYRykg2/bon2PxkSVwbCA5WDvj2kvvAPE/+2yytdN X-Developer-Key: i=mahesh.rao@altera.com; a=ed25519; pk=tQiFUzoKxHrQLDtWeEeaeTeJTl/UfclUHWZy1fjSiyg= X-Endpoint-Received: by B4 Relay for mahesh.rao@altera.com/20250107 with auth_id=337 X-Original-From: Mahesh Rao Reply-To: mahesh.rao@altera.com From: Mahesh Rao Add interrupt specification for Intel Stratix10 Service layer for asynchronous communication. Reviewed-by: Matthew Gerlach Reviewed-by: Rob Herring (Arm) Signed-off-by: Mahesh Rao --- .../devicetree/bindings/firmware/intel,stratix10-svc.yaml | 10 ++++++= ++++ 1 file changed, 10 insertions(+) diff --git a/Documentation/devicetree/bindings/firmware/intel,stratix10-svc= .yaml b/Documentation/devicetree/bindings/firmware/intel,stratix10-svc.yaml index fac1e955852e4f9b966c991dcfac56222c5f7315..656cc50fd08217f270f95ae3901= 0152423315ed1 100644 --- a/Documentation/devicetree/bindings/firmware/intel,stratix10-svc.yaml +++ b/Documentation/devicetree/bindings/firmware/intel,stratix10-svc.yaml @@ -54,6 +54,12 @@ properties: reserved memory region for the service layer driver to communicate with the secure device manager. =20 + interrupts: + maxItems: 1 + description: + This interrupt is used by the Secure Device Manager (SDM) to signal + completion of an asynchronous operation to service layer driver. + fpga-mgr: $ref: /schemas/fpga/intel,stratix10-soc-fpga-mgr.yaml description: Optional child node for fpga manager to perform fabric co= nfiguration. @@ -67,6 +73,8 @@ additionalProperties: false =20 examples: - | + #include + reserved-memory { #address-cells =3D <2>; #size-cells =3D <2>; @@ -84,6 +92,8 @@ examples: compatible =3D "intel,stratix10-svc"; method =3D "smc"; memory-region =3D <&service_reserved>; + interrupts =3D ; + interrupt-parent =3D <&intc0>; =20 fpga-mgr { compatible =3D "intel,stratix10-soc-fpga-mgr"; --=20 2.35.3 From nobody Mon Oct 6 10:17:30 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2899F28B7C7; Tue, 22 Jul 2025 15:09:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753196949; cv=none; b=GpZGYs6kxOFBJ4gn8Kr7MEgv2wuMMl5vbML45EAvDvwtXFiZxFvkIQfViERi68qKrXpnrHl4s4g9Flu7WWOywWwWS6tnScb6ZKkCD7+yfHSNX34pjXKKAG7NNlPhGQpsYbeEdZmHcBXasxnEtjLGjxWztHQjZFfQvFo0k7SH2WQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753196949; c=relaxed/simple; bh=aHN18HPkwCf0LxSHB2eIoBDEjdVHt7XQYvM14GyS9uk=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Nd2L5OJinWfcK5Smbqtpjz1+hkf3x2wR0lMKM1TUJ9dEjq6KToT57ageiJuc9ktXgviW6M1ZlKjHfPV66DTkV5axHe5IFcu8Fu5y3YkcYq+wM5VfSSSgvLdharmBH6vw6/d7ViNiZd0jhGkCfppojr82XS47dtTqQtKBK3rbHS8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=k+Dmi5yW; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="k+Dmi5yW" Received: by smtp.kernel.org (Postfix) with ESMTPS id CA212C4CEF8; Tue, 22 Jul 2025 15:09:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1753196948; bh=aHN18HPkwCf0LxSHB2eIoBDEjdVHt7XQYvM14GyS9uk=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=k+Dmi5yWjjBHSfJSItPo97SKQO+cq4Lanxud1mQZkCT3KRDN5aL3A3s+F4f54vXWL nMG3Oaup2wCmCM3Ts5hp12qHKnni+1qGDAI1Y1dYkl8VNrQdlH0MgLqpi/rQZevjqe YA1Oxfz9SjU9hjm+cZm4WD7cAlTi31QxvxXCG/uKGjdshdGDmTRatBWGOdNbWdea1k him9UoqPS0xOTBf9rIQPwxumeQIw1PV6GVK3y1dk0sjsBb/crHTZ7lP8rgb/7YKZN7 Ajo/TC9QYuERwANTH6foTDkvXzC+bhVHzbeF52yyUQLbJc9ClPOe1L1X+M5M5j5/+B jx0DGvPsZAMNQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id BA8A0C87FC5; Tue, 22 Jul 2025 15:09:08 +0000 (UTC) From: Mahesh Rao via B4 Relay Date: Tue, 22 Jul 2025 23:07:52 +0800 Subject: [PATCH 2/4] dts: stratix10: Add support for SDM mailbox interrupt for Intel Stratix10 SoC FPGA. Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250722-sip_svc_irq-v1-2-c5b9e02c1ce6@altera.com> References: <20250722-sip_svc_irq-v1-0-c5b9e02c1ce6@altera.com> In-Reply-To: <20250722-sip_svc_irq-v1-0-c5b9e02c1ce6@altera.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Dinh Nguyen Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Mahesh Rao X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1753196946; l=1326; i=mahesh.rao@altera.com; s=20250107; h=from:subject:message-id; bh=EyWFuPMqdroUgCXWZr6rl+Afig+2qBq3MLf9ty0RfNw=; b=hPx+iNGCXFxdYOfVUDxINu9LBG9KDVYy8r+6gnqauneL9xWveBSxoby7xpa16PvXLQedrMGJU IazOx9B17ItDm1Hb2CVlX7YpjU/noFyTdjsje6zN2wZq5e6X1NL5GfQ X-Developer-Key: i=mahesh.rao@altera.com; a=ed25519; pk=tQiFUzoKxHrQLDtWeEeaeTeJTl/UfclUHWZy1fjSiyg= X-Endpoint-Received: by B4 Relay for mahesh.rao@altera.com/20250107 with auth_id=337 X-Original-From: Mahesh Rao Reply-To: mahesh.rao@altera.com From: Mahesh Rao Add support for Secure Device Manager (SDM) mailbox doorbell interrupt on Stratix10 SoC FPGA for supporting asynchronous transactions. Signed-off-by: Mahesh Rao --- arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi b/arch/arm64= /boot/dts/altera/socfpga_stratix10.dtsi index 0def0b0daaf73101362eb13e0db5901c6ade06e1..9699b3fe79c89c0af0d00e8f1a5= 548707d01539d 100644 --- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi @@ -1,11 +1,13 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright Altera Corporation (C) 2015. All rights reserved. + * Copyright (C) 2025, Altera Corporation */ =20 /dts-v1/; #include #include +#include #include =20 / { @@ -74,6 +76,8 @@ svc { compatible =3D "intel,stratix10-svc"; method =3D "smc"; memory-region =3D <&service_reserved>; + interrupts =3D ; + interrupt-parent =3D <&intc>; =20 fpga_mgr: fpga-mgr { compatible =3D "intel,stratix10-soc-fpga-mgr"; --=20 2.35.3 From nobody Mon Oct 6 10:17:30 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 288CA273816; Tue, 22 Jul 2025 15:09:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753196949; cv=none; b=QWjgGFL8fQdJkECTkzPZRgIEHG83mAuZIZq/I9fKIgaUm9j5V30qcMvKEmuRBUz4fyNIMOTkasvFqiu6VkMSuOVm/VXnHXEBNC/65v9PWNPwVCkXILL6JD445pE6lunxAmXg4IE29bZkU1Jgmbew9pa5uoGVpiyWgQcpImQHaNM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753196949; c=relaxed/simple; bh=UmKRauBkPwRBEcxzeLfsR2YxRVyU+QCdpvaIF5yeb1A=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=U6Y8bOSgNIHouzANqRIwvqUHM2pc1LqAOiXmh5hu1K+ggtQ/hyESU7SpVmU0YTVtINEUL6oiE3eypmmZ5BpV0XddNBFUgw5vb6220r5Btv08wMMVlHU0OZAiO/kzMYEu+L671UxDLYZNl4bGf5GUBF+XzH4xbwDf7mMsStpM/Wc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=JuuG8Wuu; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="JuuG8Wuu" Received: by smtp.kernel.org (Postfix) with ESMTPS id D945CC4AF0B; Tue, 22 Jul 2025 15:09:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1753196948; bh=UmKRauBkPwRBEcxzeLfsR2YxRVyU+QCdpvaIF5yeb1A=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=JuuG8WuuJlC+TR2KBcY4iI2PVJkrrIXhiAL9k3md+qxPYMoETS6QmTQAnA8cLGAsw vcZ84NgBdzx6JNYmrcw+rJ2jXaM8fDNwxuUyW6pGjD8QDMfdISZ1DPvHNRbTbBNSQJ 9H/EAvLxpEBGe5KMb45jzQ4xV5EO4Iq+h3i0DAlg7xLYZL2hTrD/Z41PRustdXQxL0 Sj2nrx6ujQgtXN7FXUu7utgf7o1G+QQZvUPW6oPByUNP0/6EFAtWrBaCfXM+LD+awa 9Y892bj8OgtOT1GNXRgb84Q4mSsUPTNcaM/+1nOKjiqK907y9X+rT8dJgNS2f40pS8 WredeMKvaQAfQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id C98F9C83F1A; Tue, 22 Jul 2025 15:09:08 +0000 (UTC) From: Mahesh Rao via B4 Relay Date: Tue, 22 Jul 2025 23:07:53 +0800 Subject: [PATCH 3/4] dts: agilex: Add support for SDM mailbox interrupt for Intel Agilex SoC FPGA. Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250722-sip_svc_irq-v1-3-c5b9e02c1ce6@altera.com> References: <20250722-sip_svc_irq-v1-0-c5b9e02c1ce6@altera.com> In-Reply-To: <20250722-sip_svc_irq-v1-0-c5b9e02c1ce6@altera.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Dinh Nguyen Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Mahesh Rao , Matthew Gerlach X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1753196946; l=956; i=mahesh.rao@altera.com; s=20250107; h=from:subject:message-id; bh=qLJL9E6mhNOyiVfHw+nPeNLWSX7L0xd4wCMDiWauGyc=; b=/SOzXqFsdQWRhSBWMsOdPguNNREu4BpMpU0pOPlTo/z4UC7X6csZ8iqTWM3n7hlD9s/Z7OJ9U jbIwpDeNskRB25CJIa4GWmTD93kqEWlXkMleN2foxsrzTR8hVcdXL8o X-Developer-Key: i=mahesh.rao@altera.com; a=ed25519; pk=tQiFUzoKxHrQLDtWeEeaeTeJTl/UfclUHWZy1fjSiyg= X-Endpoint-Received: by B4 Relay for mahesh.rao@altera.com/20250107 with auth_id=337 X-Original-From: Mahesh Rao Reply-To: mahesh.rao@altera.com From: Mahesh Rao Add support for Secure Device Manager (SDM) mailbox doorbell interrupt on Agilex SoC FPGA for supporting asynchronous transactions. Signed-off-by: Mahesh Rao Reviewed-by: Matthew Gerlach --- arch/arm64/boot/dts/intel/socfpga_agilex.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi b/arch/arm64/boo= t/dts/intel/socfpga_agilex.dtsi index a77a504effeab6b487ea0ef4c733f3ed80cad5be..436de1bb18d7a561c169595ad50= d54d8120fdd35 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi +++ b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi @@ -65,6 +65,8 @@ svc { compatible =3D "intel,agilex-svc"; method =3D "smc"; memory-region =3D <&service_reserved>; + interrupts =3D ; + interrupt-parent =3D <&intc>; =20 fpga_mgr: fpga-mgr { compatible =3D "intel,agilex-soc-fpga-mgr"; --=20 2.35.3 From nobody Mon Oct 6 10:17:30 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6079B2EA742; Tue, 22 Jul 2025 15:09:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753196949; cv=none; b=AXwKQIBJo3s3fQ42Nc6h+0i5QQLLAxLaeDusU5oh/vReaFlWZsF/5LnVlFLdzOeWtnnzZGGe1P3Ta9iGjzHxnGYh6VMWAFOXng8CWsVSeXxhSjZbZ1K7R+DHU/6L0od4CcvYZqRsDB+Vfn6CPHq+uam3YfIh6boRkM/no5YYO3g= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753196949; c=relaxed/simple; bh=kb7yQu9cFrXMBq6waUNjUscIziKeLqsouZSE3H5G5s0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=UM1YoQzbQtgAqwwzV68VjtY727QkPeeymSy+2Xdlg91QIv4HO14gAc/k6hoJktIHkUF5f6EuZ7QuGIPm0qQJBknCd2Gmbq7+DIHnGn7qNjw4c+QxIs2XESUPKZo4HDtGFLIu6281l958FWsnnX/HtsrpYaeM4+s4r7z05zdk6bA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=S1fDguDZ; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="S1fDguDZ" Received: by smtp.kernel.org (Postfix) with ESMTPS id 209DCC4CEF7; Tue, 22 Jul 2025 15:09:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1753196949; bh=kb7yQu9cFrXMBq6waUNjUscIziKeLqsouZSE3H5G5s0=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=S1fDguDZ8AoxC5eX6IZL4n1z6q0dcfZowLSi5o1EupjUwGLjBQxS/BVP4xND7K2a8 w29gWcPYrUc04A4wKvDi20wexJa2yTFBDsbKbAIEWF7XKQCBlTH0QwiBuez6JFfjPs OS/gjQnV6WQirz48Lgts88CBaXmiO9BUYqmZq5k/eK/E3/r8Jp9Dznn5OoKpNZcman 86hgqXxY8ArK9Hpi5x0pynflHT6Vjaz3V9ok4izKibACBdkVauFrOpINcLpSCe02tn 819CNSxmpT20PRznwfrSkBw1qLCcIbc5ivXm6x73+tedNAxIY4clEx/zUtCKs+r2pO 5UmakNRxYymGw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 17A05C83F34; Tue, 22 Jul 2025 15:09:09 +0000 (UTC) From: Mahesh Rao via B4 Relay Date: Tue, 22 Jul 2025 23:07:54 +0800 Subject: [PATCH 4/4] firmware: stratix10-svc: Add for SDM mailbox doorbell interrupt Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250722-sip_svc_irq-v1-4-c5b9e02c1ce6@altera.com> References: <20250722-sip_svc_irq-v1-0-c5b9e02c1ce6@altera.com> In-Reply-To: <20250722-sip_svc_irq-v1-0-c5b9e02c1ce6@altera.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Dinh Nguyen Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Mahesh Rao , Matthew Gerlach X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1753196946; l=10436; i=mahesh.rao@altera.com; s=20250107; h=from:subject:message-id; bh=hx3/zwBUt7WiXtNLJ8gUWse7GWY5YI8ZYnNkxjxE7Gw=; b=oXJ2P+IcUmUc3pLrK5YCDxDKYP80B3eGzt7A9Bh6zb1VWvp7MnjrM+FiCGYnHtZonepDgfhPr 5IvfIyLswJ+DWbU3r0DFXuEra0O9Uo0SlBAaaO/Q1grsX3oPPu/cmrB X-Developer-Key: i=mahesh.rao@altera.com; a=ed25519; pk=tQiFUzoKxHrQLDtWeEeaeTeJTl/UfclUHWZy1fjSiyg= X-Endpoint-Received: by B4 Relay for mahesh.rao@altera.com/20250107 with auth_id=337 X-Original-From: Mahesh Rao Reply-To: mahesh.rao@altera.com From: Mahesh Rao Add support for SDM (Secure Device Manager) mailbox doorbell interrupt for async transactions. On interrupt, a workqueue is triggered which polls the ATF for pending responses and retrieves the bitmap of all retrieved and unprocessed transaction ids of mailbox responses from SDM. It then triggers the corresponding registered callbacks. Signed-off-by: Mahesh Rao Reviewed-by: Matthew Gerlach --- drivers/firmware/stratix10-svc.c | 117 +++++++++++++++++++++++= +--- include/linux/firmware/intel/stratix10-smc.h | 23 ++++++ 2 files changed, 130 insertions(+), 10 deletions(-) diff --git a/drivers/firmware/stratix10-svc.c b/drivers/firmware/stratix10-= svc.c index 491a8149033f975d515444f025723658c51aa1fe..807226d5ec53bffe7e7f31b6071= 8703434e94c90 100644 --- a/drivers/firmware/stratix10-svc.c +++ b/drivers/firmware/stratix10-svc.c @@ -9,12 +9,14 @@ #include #include #include +#include #include #include #include #include #include #include +#include #include #include #include @@ -22,6 +24,7 @@ #include #include #include +#include =20 /** * SVC_NUM_DATA_IN_FIFO - number of struct stratix10_svc_data in the FIFO @@ -213,6 +216,7 @@ struct stratix10_async_chan { * asynchronous operations * @initialized: Flag indicating whether the control structure has * been initialized + * @irq: Interrupt request number associated with the asynchronous control * @invoke_fn: Function pointer for invoking Stratix10 service calls * to EL3 secure firmware * @async_id_pool: Pointer to the ID pool used for asynchronous @@ -223,11 +227,13 @@ struct stratix10_async_chan { * structure * @trx_list_wr_lock: Spinlock for protecting the transaction list * write operations + * @async_work: Work structure for scheduling asynchronous work * @trx_list: Hash table for managing asynchronous transactions */ =20 struct stratix10_async_ctrl { bool initialized; + int irq; void (*invoke_fn)(struct stratix10_async_ctrl *actrl, const struct arm_smccc_1_2_regs *args, struct arm_smccc_1_2_regs *res); @@ -236,6 +242,7 @@ struct stratix10_async_ctrl { struct stratix10_async_chan *common_async_chan; /* spinlock to protect the writes to trx_list hash table */ spinlock_t trx_list_wr_lock; + struct work_struct async_work; DECLARE_HASHTABLE(trx_list, ASYNC_TRX_HASH_BITS); }; =20 @@ -1709,14 +1716,81 @@ static inline void stratix10_smc_1_2(struct stratix= 10_async_ctrl *actrl, arm_smccc_1_2_smc(args, res); } =20 +static irqreturn_t stratix10_svc_async_irq_handler(int irq, void *dev_id) +{ + struct stratix10_async_ctrl *actrl =3D &ctrl->actrl; + struct stratix10_svc_controller *ctrl =3D dev_id; + + queue_work(system_bh_wq, &actrl->async_work); + disable_irq_nosync(actrl->irq); + return IRQ_HANDLED; +} +/** + * stratix10_async_workqueue_handler - Handler for the asynchronous + * workqueue in Stratix10 service controller. + * @work: Pointer to the work structure that contains the asynchronous + * workqueue handler. + * This function is the handler for the asynchronous workqueue. It performs + * the following tasks: + * - Invokes the asynchronous polling on interrupt supervisory call. + * - On success,it retrieves the bitmap of pending transactions from mailb= ox + * fifo in ATF. + * - It processes each pending transaction by calling the corresponding + * callback function. + * + * The function ensures that the IRQ is enabled after processing the trans= actions + * and logs the total time taken to handle the transactions along with the= number + * of transactions handled and the CPU on which the handler ran. + */ +static void stratix10_async_workqueue_handler(struct work_struct *work) +{ + struct stratix10_async_ctrl *actrl =3D + container_of(work, struct stratix10_async_ctrl, async_work); + struct arm_smccc_1_2_regs + args =3D { .a0 =3D INTEL_SIP_SMC_ASYNC_POLL_ON_IRQ }, res; + DECLARE_BITMAP(pend_on_irq, TOTAL_TRANSACTION_IDS); + struct stratix10_svc_async_handler *handler; + unsigned long transaction_id =3D 0; + u64 bitmap_array[4]; + + actrl->invoke_fn(actrl, &args, &res); + if (res.a0 =3D=3D INTEL_SIP_SMC_STATUS_OK) { + bitmap_array[0] =3D res.a1; + bitmap_array[1] =3D res.a2; + bitmap_array[2] =3D res.a3; + bitmap_array[3] =3D res.a4; + bitmap_from_arr64(pend_on_irq, bitmap_array, TOTAL_TRANSACTION_IDS); + rcu_read_lock(); + do { + transaction_id =3D find_next_bit(pend_on_irq, + TOTAL_TRANSACTION_IDS, + transaction_id); + if (transaction_id >=3D TOTAL_TRANSACTION_IDS) + break; + hash_for_each_possible_rcu_notrace(actrl->trx_list, + handler, next, + transaction_id) { + if (handler->transaction_id =3D=3D transaction_id) { + handler->cb(handler->cb_arg); + break; + } + } + transaction_id++; + } while (transaction_id < TOTAL_TRANSACTION_IDS); + rcu_read_unlock(); + } + enable_irq(actrl->irq); +} + /** * stratix10_svc_async_init - Initialize the Stratix10 service * controller for asynchronous operations. * @controller: Pointer to the Stratix10 service controller structure. * * This function initializes the asynchronous service controller by - * setting up the necessary data structures and initializing the - * transaction list. + * setting up the necessary data structures ,initializing the + * transaction list and registering the IRQ handler for asynchronous + * transactions. * * Return: 0 on success, -EINVAL if the controller is NULL or already * initialized, -ENOMEM if memory allocation fails, @@ -1728,7 +1802,7 @@ static int stratix10_svc_async_init(struct stratix10_= svc_controller *controller) struct stratix10_async_ctrl *actrl; struct arm_smccc_res res; struct device *dev; - int ret; + int ret, irq; =20 if (!controller) return -EINVAL; @@ -1775,6 +1849,22 @@ static int stratix10_svc_async_init(struct stratix10= _svc_controller *controller) hash_init(actrl->trx_list); atomic_set(&actrl->common_achan_refcount, 0); =20 + irq =3D of_irq_get(dev_of_node(dev), 0); + if (irq < 0) { + dev_warn(dev, "Failed to get IRQ, falling back to polling mode\n"); + } else { + ret =3D devm_request_any_context_irq(dev, irq, stratix10_svc_async_irq_h= andler, + IRQF_NO_AUTOEN, "stratix10_svc", controller); + if (ret =3D=3D 0) { + dev_alert(dev, + "Registered IRQ %d for sip async operations\n", + irq); + actrl->irq =3D irq; + INIT_WORK(&actrl->async_work, stratix10_async_workqueue_handler); + enable_irq(actrl->irq); + } + } + actrl->initialized =3D true; return 0; } @@ -1784,13 +1874,14 @@ static int stratix10_svc_async_init(struct stratix1= 0_svc_controller *controller) * service controller * @ctrl: Pointer to the stratix10_svc_controller structure * - * This function performs the necessary cleanup for the asynchronous - * service controller. It checks if the controller is valid and if it - * has been initialized. It then locks the transaction list and safely - * removes and deallocates each handler in the list. The function also - * removes any asynchronous clients associated with the controller's - * channels and destroys the asynchronous ID pool. Finally, it resets - * the asynchronous ID pool and invoke function pointers to NULL. + * This function performs the necessary cleanup for the asynchronous servi= ce + * controller. It checks if the controller is valid and if it has been + * initialized. Also If the controller has an IRQ assigned, it frees the I= RQ + * and flushes any pending asynchronous work. It then locks the transaction + * list and safely removes and deallocates each handler in the list. + * The function also removes any asynchronous clients associated with the + * controller's channels and destroys the asynchronous ID pool. Finally, it + * resets the asynchronous ID pool and invoke function pointers to NULL. * * Return: 0 on success, -EINVAL if the controller is invalid or not * initialized. @@ -1812,6 +1903,12 @@ static int stratix10_svc_async_exit(struct stratix10= _svc_controller *ctrl) =20 actrl->initialized =3D false; =20 + if (actrl->irq > 0) { + free_irq(actrl->irq, ctrl); + flush_work(&actrl->async_work); + actrl->irq =3D 0; + } + spin_lock(&actrl->trx_list_wr_lock); hash_for_each_safe(actrl->trx_list, i, tmp, handler, next) { stratix10_deallocate_id(handler->achan->job_id_pool, diff --git a/include/linux/firmware/intel/stratix10-smc.h b/include/linux/f= irmware/intel/stratix10-smc.h index f87273af5e284b8912d87eb9d7179eb3d43e40e1..45e9dd4211f4994d67e5a6e00a5= a817e96d42a8d 100644 --- a/include/linux/firmware/intel/stratix10-smc.h +++ b/include/linux/firmware/intel/stratix10-smc.h @@ -645,6 +645,29 @@ INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_FPGA_= CONFIG_COMPLETED_WRITE) #define INTEL_SIP_SMC_ASYNC_POLL \ INTEL_SIP_SMC_ASYNC_VAL(INTEL_SIP_SMC_ASYNC_FUNC_ID_POLL) =20 +/** + * Request INTEL_SIP_SMC_ASYNC_POLL_ON_IRQ + * Async call used by service driver at EL1 to read response from SDM + * mailbox and to retrieve the transaction id's of the read response's. + * + * Call register usage: + * a0 INTEL_SIP_SMC_ASYNC_POLL_ON_IRQ + * a1 transaction job id + * a2-7 will be used to return the response data + * + * Return status + * a0 INTEL_SIP_SMC_STATUS_OK + * a1-a4 will contain bitmap of available responses's transaction id as set + * bit position. + * a5-17 not used + * Or + * a0 INTEL_SIP_SMC_STATUS_NO_RESPONSE + * a1-17 not used + */ +#define INTEL_SIP_SMC_ASYNC_FUNC_ID_IRQ_POLL (0xC9) +#define INTEL_SIP_SMC_ASYNC_POLL_ON_IRQ \ + INTEL_SIP_SMC_ASYNC_VAL(INTEL_SIP_SMC_ASYNC_FUNC_ID_IRQ_POLL) + /** * Request INTEL_SIP_SMC_ASYNC_RSU_GET_SPT * Async call to get RSU SPT from SDM. --=20 2.35.3