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Tue, 22 Jul 2025 15:37:03 +0800 (CST) X-QQ-SSF: 0000000000000000000000000000000 X-QQ-GoodBg: 0 X-BIZMAIL-ID: 8049329439976532994 EX-QQ-RecipientCnt: 16 From: Troy Mitchell Date: Tue, 22 Jul 2025 15:36:30 +0800 Subject: [PATCH v2 1/2] clk: spacemit: fix sspax_clk Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250722-k1-clk-i2s-v2-1-2f8edfe3dab4@linux.spacemit.com> References: <20250722-k1-clk-i2s-v2-0-2f8edfe3dab4@linux.spacemit.com> In-Reply-To: <20250722-k1-clk-i2s-v2-0-2f8edfe3dab4@linux.spacemit.com> To: Michael Turquette , Stephen Boyd , Yixun Lan , Alex Elder , Haylen Chu , Inochi Amaoto , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-clk@vger.kernel.org, linux-riscv@lists.infradead.org, spacemit@lists.linux.dev, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Troy Mitchell , Yao Zi X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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This patch introduces SSPAx_I2S_BCLK as a dummy gate to enable BIT3. Fixes: 1b72c59db0add ("clk: spacemit: Add clock support for SpacemiT K1 SoC= ") Signed-off-by: Troy Mitchell Suggested-by: Yao Zi --- drivers/clk/spacemit/ccu-k1.c | 25 +++++++++++++++++++++---- 1 file changed, 21 insertions(+), 4 deletions(-) diff --git a/drivers/clk/spacemit/ccu-k1.c b/drivers/clk/spacemit/ccu-k1.c index cdde37a0523537c2f436e481ae8d6ec5a581b87e..3b1a861729c6e7ef64bd42b9756= 88058610d8c1c 100644 --- a/drivers/clk/spacemit/ccu-k1.c +++ b/drivers/clk/spacemit/ccu-k1.c @@ -349,7 +349,10 @@ CCU_GATE_DEFINE(aib_clk, CCU_PARENT_NAME(vctcxo_24m), = APBC_AIB_CLK_RST, BIT(1), =20 CCU_GATE_DEFINE(onewire_clk, CCU_PARENT_NAME(vctcxo_24m), APBC_ONEWIRE_CLK= _RST, BIT(1), 0); =20 -static const struct clk_parent_data sspa_parents[] =3D { +CCU_GATE_DEFINE(sspa0_i2s_bclk, CCU_PARENT_HW(i2s_bclk), APBC_SSPA0_CLK_RS= T, BIT(3), 0); +CCU_GATE_DEFINE(sspa1_i2s_bclk, CCU_PARENT_HW(i2s_bclk), APBC_SSPA1_CLK_RS= T, BIT(3), 0); + +static const struct clk_parent_data sspa0_parents[] =3D { CCU_PARENT_HW(pll1_d384_6p4), CCU_PARENT_HW(pll1_d192_12p8), CCU_PARENT_HW(pll1_d96_25p6), @@ -357,10 +360,22 @@ static const struct clk_parent_data sspa_parents[] = =3D { CCU_PARENT_HW(pll1_d768_3p2), CCU_PARENT_HW(pll1_d1536_1p6), CCU_PARENT_HW(pll1_d3072_0p8), - CCU_PARENT_HW(i2s_bclk), + CCU_PARENT_HW(sspa0_i2s_bclk), }; -CCU_MUX_GATE_DEFINE(sspa0_clk, sspa_parents, APBC_SSPA0_CLK_RST, 4, 3, BIT= (1), 0); -CCU_MUX_GATE_DEFINE(sspa1_clk, sspa_parents, APBC_SSPA1_CLK_RST, 4, 3, BIT= (1), 0); +CCU_MUX_GATE_DEFINE(sspa0_clk, sspa0_parents, APBC_SSPA0_CLK_RST, 4, 3, BI= T(1), 0); + +static const struct clk_parent_data sspa1_parents[] =3D { + CCU_PARENT_HW(pll1_d384_6p4), + CCU_PARENT_HW(pll1_d192_12p8), + CCU_PARENT_HW(pll1_d96_25p6), + CCU_PARENT_HW(pll1_d48_51p2), + CCU_PARENT_HW(pll1_d768_3p2), + CCU_PARENT_HW(pll1_d1536_1p6), + CCU_PARENT_HW(pll1_d3072_0p8), + CCU_PARENT_HW(sspa1_i2s_bclk), +}; +CCU_MUX_GATE_DEFINE(sspa1_clk, sspa1_parents, APBC_SSPA1_CLK_RST, 4, 3, BI= T(1), 0); + CCU_GATE_DEFINE(dro_clk, CCU_PARENT_HW(apb_clk), APBC_DRO_CLK_RST, BIT(1),= 0); CCU_GATE_DEFINE(ir_clk, CCU_PARENT_HW(apb_clk), APBC_IR_CLK_RST, BIT(1), 0= ); CCU_GATE_DEFINE(tsen_clk, CCU_PARENT_HW(apb_clk), APBC_TSEN_CLK_RST, BIT(1= ), 0); @@ -909,6 +924,8 @@ static struct clk_hw *k1_ccu_apbc_hws[] =3D { [CLK_TIMERS2] =3D &timers2_clk.common.hw, [CLK_AIB] =3D &aib_clk.common.hw, [CLK_ONEWIRE] =3D &onewire_clk.common.hw, + [CLK_SSPA0_I2S_BCLK] =3D &sspa0_i2s_bclk.common.hw, + [CLK_SSPA1_I2S_BCLK] =3D &sspa1_i2s_bclk.common.hw, [CLK_SSPA0] =3D &sspa0_clk.common.hw, [CLK_SSPA1] =3D &sspa1_clk.common.hw, [CLK_DRO] =3D &dro_clk.common.hw, --=20 2.50.1