From nobody Mon Oct 6 11:55:46 2025 Received: from smtpbgbr1.qq.com (smtpbgbr1.qq.com [54.207.19.206]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5A6ED2E425A; Tue, 22 Jul 2025 07:37:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=54.207.19.206 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753169853; cv=none; b=LJGhu2Dub1ATjmMIABnotWJKM3VKxpKm3hOwCGZ+qDGflvEoZpea+Q/aCBc0kY7/Fst0J64dvoBiCiHOUE7JQTtHld2+ro49KVNNiDCtBPyAfTjtXwyRRAHhCwjHDWI2nCk/SsRw2C/FuRxkfjZ21JUpNwC9fGST8vTLNCaaQEI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753169853; c=relaxed/simple; bh=mh8kXUN6Mr5mFWd7+ckjj2inOSEDYAbx/F4sl0Cobz4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=aJcPU3OHjc5td2Y0hMD7L0N8vqhe8qgyjqg2RpO233OHu/0JGaaMW1m1ah64QDrUBrt70dRSvm9itBt0p7hQGR+xw/NGET6Hf+78ZbMVctEAADwk9S9f0X1/Ta7ZYml1DlqLJZ+Zjp1tISxXAH12DYh/Ck2SoeuOq2tSStpTPo0= ARC-Authentication-Results: i=1; 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Tue, 22 Jul 2025 15:37:03 +0800 (CST) X-QQ-SSF: 0000000000000000000000000000000 X-QQ-GoodBg: 0 X-BIZMAIL-ID: 8049329439976532994 EX-QQ-RecipientCnt: 16 From: Troy Mitchell Date: Tue, 22 Jul 2025 15:36:30 +0800 Subject: [PATCH v2 1/2] clk: spacemit: fix sspax_clk Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250722-k1-clk-i2s-v2-1-2f8edfe3dab4@linux.spacemit.com> References: <20250722-k1-clk-i2s-v2-0-2f8edfe3dab4@linux.spacemit.com> In-Reply-To: <20250722-k1-clk-i2s-v2-0-2f8edfe3dab4@linux.spacemit.com> To: Michael Turquette , Stephen Boyd , Yixun Lan , Alex Elder , Haylen Chu , Inochi Amaoto , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-clk@vger.kernel.org, linux-riscv@lists.infradead.org, spacemit@lists.linux.dev, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Troy Mitchell , Yao Zi X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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This patch introduces SSPAx_I2S_BCLK as a dummy gate to enable BIT3. Fixes: 1b72c59db0add ("clk: spacemit: Add clock support for SpacemiT K1 SoC= ") Signed-off-by: Troy Mitchell Suggested-by: Yao Zi --- drivers/clk/spacemit/ccu-k1.c | 25 +++++++++++++++++++++---- 1 file changed, 21 insertions(+), 4 deletions(-) diff --git a/drivers/clk/spacemit/ccu-k1.c b/drivers/clk/spacemit/ccu-k1.c index cdde37a0523537c2f436e481ae8d6ec5a581b87e..3b1a861729c6e7ef64bd42b9756= 88058610d8c1c 100644 --- a/drivers/clk/spacemit/ccu-k1.c +++ b/drivers/clk/spacemit/ccu-k1.c @@ -349,7 +349,10 @@ CCU_GATE_DEFINE(aib_clk, CCU_PARENT_NAME(vctcxo_24m), = APBC_AIB_CLK_RST, BIT(1), =20 CCU_GATE_DEFINE(onewire_clk, CCU_PARENT_NAME(vctcxo_24m), APBC_ONEWIRE_CLK= _RST, BIT(1), 0); =20 -static const struct clk_parent_data sspa_parents[] =3D { +CCU_GATE_DEFINE(sspa0_i2s_bclk, CCU_PARENT_HW(i2s_bclk), APBC_SSPA0_CLK_RS= T, BIT(3), 0); +CCU_GATE_DEFINE(sspa1_i2s_bclk, CCU_PARENT_HW(i2s_bclk), APBC_SSPA1_CLK_RS= T, BIT(3), 0); + +static const struct clk_parent_data sspa0_parents[] =3D { CCU_PARENT_HW(pll1_d384_6p4), CCU_PARENT_HW(pll1_d192_12p8), CCU_PARENT_HW(pll1_d96_25p6), @@ -357,10 +360,22 @@ static const struct clk_parent_data sspa_parents[] = =3D { CCU_PARENT_HW(pll1_d768_3p2), CCU_PARENT_HW(pll1_d1536_1p6), CCU_PARENT_HW(pll1_d3072_0p8), - CCU_PARENT_HW(i2s_bclk), + CCU_PARENT_HW(sspa0_i2s_bclk), }; -CCU_MUX_GATE_DEFINE(sspa0_clk, sspa_parents, APBC_SSPA0_CLK_RST, 4, 3, BIT= (1), 0); -CCU_MUX_GATE_DEFINE(sspa1_clk, sspa_parents, APBC_SSPA1_CLK_RST, 4, 3, BIT= (1), 0); +CCU_MUX_GATE_DEFINE(sspa0_clk, sspa0_parents, APBC_SSPA0_CLK_RST, 4, 3, BI= T(1), 0); + +static const struct clk_parent_data sspa1_parents[] =3D { + CCU_PARENT_HW(pll1_d384_6p4), + CCU_PARENT_HW(pll1_d192_12p8), + CCU_PARENT_HW(pll1_d96_25p6), + CCU_PARENT_HW(pll1_d48_51p2), + CCU_PARENT_HW(pll1_d768_3p2), + CCU_PARENT_HW(pll1_d1536_1p6), + CCU_PARENT_HW(pll1_d3072_0p8), + CCU_PARENT_HW(sspa1_i2s_bclk), +}; +CCU_MUX_GATE_DEFINE(sspa1_clk, sspa1_parents, APBC_SSPA1_CLK_RST, 4, 3, BI= T(1), 0); + CCU_GATE_DEFINE(dro_clk, CCU_PARENT_HW(apb_clk), APBC_DRO_CLK_RST, BIT(1),= 0); CCU_GATE_DEFINE(ir_clk, CCU_PARENT_HW(apb_clk), APBC_IR_CLK_RST, BIT(1), 0= ); CCU_GATE_DEFINE(tsen_clk, CCU_PARENT_HW(apb_clk), APBC_TSEN_CLK_RST, BIT(1= ), 0); @@ -909,6 +924,8 @@ static struct clk_hw *k1_ccu_apbc_hws[] =3D { [CLK_TIMERS2] =3D &timers2_clk.common.hw, [CLK_AIB] =3D &aib_clk.common.hw, [CLK_ONEWIRE] =3D &onewire_clk.common.hw, + [CLK_SSPA0_I2S_BCLK] =3D &sspa0_i2s_bclk.common.hw, + [CLK_SSPA1_I2S_BCLK] =3D &sspa1_i2s_bclk.common.hw, [CLK_SSPA0] =3D &sspa0_clk.common.hw, [CLK_SSPA1] =3D &sspa1_clk.common.hw, [CLK_DRO] =3D &dro_clk.common.hw, --=20 2.50.1 From nobody Mon Oct 6 11:55:46 2025 Received: from smtpbg151.qq.com (smtpbg151.qq.com [18.169.211.239]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 652E32D3723; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250722-k1-clk-i2s-v2-2-2f8edfe3dab4@linux.spacemit.com> References: <20250722-k1-clk-i2s-v2-0-2f8edfe3dab4@linux.spacemit.com> In-Reply-To: <20250722-k1-clk-i2s-v2-0-2f8edfe3dab4@linux.spacemit.com> To: Michael Turquette , Stephen Boyd , Yixun Lan , Alex Elder , Haylen Chu , Inochi Amaoto , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-clk@vger.kernel.org, linux-riscv@lists.infradead.org, spacemit@lists.linux.dev, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Troy Mitchell X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1753169819; l=3905; i=troy.mitchell@linux.spacemit.com; s=20250710; h=from:subject:message-id; bh=0XUvAvsfHaff6g28QDK8UZbmnijtvMKUzjxWMgcstW0=; b=k5GPBMnuflbw6w5YYY/wSRbxzcKYTo+sAbNQujyR6OtwOjWRfniZlDNr1on6JbxWYRTUA4F5f GD09MtbJb+CC1vZ/84afMi0wLhIAFI0yt6fILL4Gv1ss8U3sJb4ccou X-Developer-Key: i=troy.mitchell@linux.spacemit.com; a=ed25519; pk=lQa7BzLrq8DfZnChqmwJ5qQk8fP2USmY/4xZ2/MSsXc= X-QQ-SENDSIZE: 520 Feedback-ID: esmtpgz:linux.spacemit.com:qybglogicsvrsz:qybglogicsvrsz3a-0 X-QQ-XMAILINFO: MoZqUia8aYdxJYUWpm9FkMaaL3pC8L7ePcF0YGgHG+PA+oca32o406+H RWnDvawZQnyP6zaiui35fGhdFfdCfZ+VEY0SiE+wz/hxI7Ahw6Tz18feGJ7tz6SEVRjveNf F5/1OsjIxrs/NCTZT8k44cFP2t1tabV2/VxukinrCU77whqzF17s97nNC6VezXnLJXo9D+2 sJWO8A1+yUZ0HdDq1BKNIk/A3Yuib1c4jD4GHiHzGa4p2J8eKASxHz+VwA0bmk3yHhH/ke6 3zQRTdPIkuqx8gEQgOecDj43vgGCWxDEkBlTHzZTalF322kaeqfHKf78I9OSblXSe+SP0p8 2FtWspUrxl1TEg0LYOU2HvFWs/BjsJrEvvUVQsNRRiVOwwGnqTLjS5FzXc0ZmBhPVZncKDi 10bCYoLjvs7Iz0w0m92U8DLBk2OA6dV37exv+HiVAwzrpKNwYQMl9+gtJHqCWxw7isJJKrX hyv+wJGYtPybB+5M9eeaZHgyc+cTWyK5ulgUv/rtbKRRJXQc4xIm7M8LZSwZnxhPo8qW6f5 7IL6fa0sUp1BxPLIktvHY8B69L0VcC10D43YV6BSbaWz2cShYaaprlscBdu96AeNib9NiU+ BepfvJDNDTQxs3sX8F9rHu6WMZP2NAbaMjBTrzSCCKuSFw/U8ixDAhWdeIjcv8GH2UmYGyp H9UPvJDVkcnq9XzFQgTTKf4r24QKD7sXCG+Y4P88rnQZWAo8y5DL23h6FZYdK/cNBAa48ck c1v0srNioms6Orkl29/yASgCevREZI7HsJ6k0naO0ninArfr2v6QvzzYjWhAHk0jFEgm3wE j4y9ZYVT4ynbyMlFvPDAYEnz5GzSkEwYxqp1NL12lrpxBJmaXB1mJ3LY5o4dWfeJ4QNKuhq HY78v5Vg/IaRWA0CvS2uYolaGA93NBNObFKHyi4Ez40QUBr/dcmVbb7MfZrj4fH/4s2Jn93 Pu/n1j90TWF0RRJIuNY08iQJFCvlu7xvA1uuYtxcxit0i2Ok0t0E6/HvSNnSLrqum6QU36p Lu3yDRssaDYVANYSsfEv0xYfxLEEGTTZAWeYT18mtT+sSCdWCldjD+u7R8PMBoFKUkk41jw lI1/dQfxDxPFsv3XqoM6CE= X-QQ-XMRINFO: OWPUhxQsoeAVDbp3OJHYyFg= X-QQ-RECHKSPAM: 0 This patch adds macro definitions: SSPAx_I2S_BCLK, to introduce a dummy gate for i2s_bclk. Signed-off-by: Troy Mitchell --- include/dt-bindings/clock/spacemit,k1-syscon.h | 114 +++++++++++++--------= ---- 1 file changed, 58 insertions(+), 56 deletions(-) diff --git a/include/dt-bindings/clock/spacemit,k1-syscon.h b/include/dt-bi= ndings/clock/spacemit,k1-syscon.h index 35968ae98246609c889eb4a7d08b4ff7360de53b..6914ccf5be45a1071d5b6eac354= cacb67888e00c 100644 --- a/include/dt-bindings/clock/spacemit,k1-syscon.h +++ b/include/dt-bindings/clock/spacemit,k1-syscon.h @@ -123,62 +123,64 @@ #define CLK_TIMERS2 41 #define CLK_AIB 42 #define CLK_ONEWIRE 43 -#define CLK_SSPA0 44 -#define CLK_SSPA1 45 -#define CLK_DRO 46 -#define CLK_IR 47 -#define CLK_TSEN 48 -#define CLK_IPC_AP2AUD 49 -#define CLK_CAN0 50 -#define CLK_CAN0_BUS 51 -#define CLK_UART0_BUS 52 -#define CLK_UART2_BUS 53 -#define CLK_UART3_BUS 54 -#define CLK_UART4_BUS 55 -#define CLK_UART5_BUS 56 -#define CLK_UART6_BUS 57 -#define CLK_UART7_BUS 58 -#define CLK_UART8_BUS 59 -#define CLK_UART9_BUS 60 -#define CLK_GPIO_BUS 61 -#define CLK_PWM0_BUS 62 -#define CLK_PWM1_BUS 63 -#define CLK_PWM2_BUS 64 -#define CLK_PWM3_BUS 65 -#define CLK_PWM4_BUS 66 -#define CLK_PWM5_BUS 67 -#define CLK_PWM6_BUS 68 -#define CLK_PWM7_BUS 69 -#define CLK_PWM8_BUS 70 -#define CLK_PWM9_BUS 71 -#define CLK_PWM10_BUS 72 -#define CLK_PWM11_BUS 73 -#define CLK_PWM12_BUS 74 -#define CLK_PWM13_BUS 75 -#define CLK_PWM14_BUS 76 -#define CLK_PWM15_BUS 77 -#define CLK_PWM16_BUS 78 -#define CLK_PWM17_BUS 79 -#define CLK_PWM18_BUS 80 -#define CLK_PWM19_BUS 81 -#define CLK_SSP3_BUS 82 -#define CLK_RTC_BUS 83 -#define CLK_TWSI0_BUS 84 -#define CLK_TWSI1_BUS 85 -#define CLK_TWSI2_BUS 86 -#define CLK_TWSI4_BUS 87 -#define CLK_TWSI5_BUS 88 -#define CLK_TWSI6_BUS 89 -#define CLK_TWSI7_BUS 90 -#define CLK_TWSI8_BUS 91 -#define CLK_TIMERS1_BUS 92 -#define CLK_TIMERS2_BUS 93 -#define CLK_AIB_BUS 94 -#define CLK_ONEWIRE_BUS 95 -#define CLK_SSPA0_BUS 96 -#define CLK_SSPA1_BUS 97 -#define CLK_TSEN_BUS 98 -#define CLK_IPC_AP2AUD_BUS 99 +#define CLK_SSPA0_I2S_BCLK 44 +#define CLK_SSPA1_I2S_BCLK 45 +#define CLK_SSPA0 46 +#define CLK_SSPA1 47 +#define CLK_DRO 48 +#define CLK_IR 49 +#define CLK_TSEN 50 +#define CLK_IPC_AP2AUD 51 +#define CLK_CAN0 52 +#define CLK_CAN0_BUS 53 +#define CLK_UART0_BUS 54 +#define CLK_UART2_BUS 55 +#define CLK_UART3_BUS 56 +#define CLK_UART4_BUS 57 +#define CLK_UART5_BUS 58 +#define CLK_UART6_BUS 59 +#define CLK_UART7_BUS 60 +#define CLK_UART8_BUS 61 +#define CLK_UART9_BUS 62 +#define CLK_GPIO_BUS 63 +#define CLK_PWM0_BUS 64 +#define CLK_PWM1_BUS 65 +#define CLK_PWM2_BUS 66 +#define CLK_PWM3_BUS 67 +#define CLK_PWM4_BUS 68 +#define CLK_PWM5_BUS 69 +#define CLK_PWM6_BUS 70 +#define CLK_PWM7_BUS 71 +#define CLK_PWM8_BUS 72 +#define CLK_PWM9_BUS 73 +#define CLK_PWM10_BUS 74 +#define CLK_PWM11_BUS 75 +#define CLK_PWM12_BUS 76 +#define CLK_PWM13_BUS 77 +#define CLK_PWM14_BUS 78 +#define CLK_PWM15_BUS 79 +#define CLK_PWM16_BUS 80 +#define CLK_PWM17_BUS 81 +#define CLK_PWM18_BUS 82 +#define CLK_PWM19_BUS 83 +#define CLK_SSP3_BUS 84 +#define CLK_RTC_BUS 85 +#define CLK_TWSI0_BUS 86 +#define CLK_TWSI1_BUS 87 +#define CLK_TWSI2_BUS 88 +#define CLK_TWSI4_BUS 89 +#define CLK_TWSI5_BUS 90 +#define CLK_TWSI6_BUS 91 +#define CLK_TWSI7_BUS 92 +#define CLK_TWSI8_BUS 93 +#define CLK_TIMERS1_BUS 94 +#define CLK_TIMERS2_BUS 95 +#define CLK_AIB_BUS 96 +#define CLK_ONEWIRE_BUS 97 +#define CLK_SSPA0_BUS 98 +#define CLK_SSPA1_BUS 99 +#define CLK_TSEN_BUS 100 +#define CLK_IPC_AP2AUD_BUS 101 =20 /* APMU clocks */ #define CLK_CCI550 0 --=20 2.50.1