From nobody Mon Oct 6 10:13:27 2025 Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C59301D6193; Tue, 22 Jul 2025 14:06:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.132.182.106 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753193216; cv=none; b=Lox8vs2qu7cpyKYVUZtLk7i47Skl8QX8FUQmVvUI2KitbsdrFL+eKJgU5zaqDPd/lxB6ZHZALjRmXrdTJWSTU/PvdgU0NY8phiPkPKWi8MefnFVsb0BigVcmYOnCiVKn9MPthFR5rpW9XdjiTP5pAsH3cAmoWVe0353F1NtU5mw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753193216; c=relaxed/simple; bh=Dq2ykfq63wn8VObJtf2Dtv3Y1KpLFKfxnczqmYre38w=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=p3eaFDJ3/zI+j5e1LEYlWtf2BP1cH9235KiWJ9xt7TTLJugGm7KT0Fi7pNZ7WcqVZyWDCa6B5iTftVvlPx8ZTtOkBVClFtKLiyx9VrrxGJ8HWPsHJ9q2iov3jf/innsKDLxTKf4TiVSCW6L9mLN+T3enfklDgZywRE5OCeGM4iM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com; spf=pass smtp.mailfrom=foss.st.com; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b=zK7U4cq3; arc=none smtp.client-ip=185.132.182.106 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=foss.st.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b="zK7U4cq3" Received: from pps.filterd (m0369458.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 56MDdKAF013598; Tue, 22 Jul 2025 16:06:22 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=selector1; bh= 1S+/fxjBGM9OThOsnlJiBdnI+RCOnybmlz6yPJOrPUQ=; b=zK7U4cq3eIBnlomy 7MJ+7nS0AO3BTgn8rSi+m/5o5qJUbYpKBQD+Zr30BWAW817UF946O1q9csOMOKF6 v25Y5LaFOWfEdbMrtQT8sONW52vFg2ipIoXMnQKCTtMygrAO6/4iuHrAoXIGFdnA 4E4uqGXVU3tIuzsZH+vTyQMlvuWLTUX+1HaO2v5QFtDhL2JqMggAHBPuDMQNXXPa XgkEZdwmGZCLmAUEgYyf7weuLBgDvSni/80pbViUIw8GMxX9598Gne67E9tRmBVk 5nZuuc6w8/EKbbbDqogM4vg+/34yhiXefOawmgNTZE4Lmk6UORHOyuw+r91WIGaZ B+96Tw== Received: from beta.dmz-ap.st.com (beta.dmz-ap.st.com [138.198.100.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 480mx4kja0-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 22 Jul 2025 16:06:21 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 1E6ED40046; Tue, 22 Jul 2025 16:05:08 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 1A8CB7A1A57; Tue, 22 Jul 2025 16:03:50 +0200 (CEST) Received: from localhost (10.48.86.185) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Tue, 22 Jul 2025 16:03:49 +0200 From: =?utf-8?q?Cl=C3=A9ment_Le_Goffic?= Date: Tue, 22 Jul 2025 16:03:18 +0200 Subject: [PATCH v3 01/19] bus: firewall: move stm32_firewall header file in include folder Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250722-ddrperfm-upstream-v3-1-7b7a4f3dc8a0@foss.st.com> References: <20250722-ddrperfm-upstream-v3-0-7b7a4f3dc8a0@foss.st.com> In-Reply-To: <20250722-ddrperfm-upstream-v3-0-7b7a4f3dc8a0@foss.st.com> To: Will Deacon , Mark Rutland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Philipp Zabel , Jonathan Corbet , Gatien Chevallier , Michael Turquette , Stephen Boyd , Gabriel Fernandez , Krzysztof Kozlowski , Le Goffic , Julius Werner CC: , , , , , , , =?utf-8?q?Cl=C3=A9ment_Le_Goffic?= X-Mailer: b4 0.15-dev-8018a X-ClientProxiedBy: SHFCAS1NODE2.st.com (10.75.129.73) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-22_02,2025-07-21_02,2025-03-28_01 Other driver than rifsc and etzpc can implement firewall ops, such as rcc. In order for them to have access to the ops and type of this framework, we need to get the `stm32_firewall.h` file in the include/ folder. Signed-off-by: Cl=C3=A9ment Le Goffic --- drivers/bus/stm32_etzpc.c | 3 +-- drivers/bus/stm32_firewall.c | 3 +-- drivers/bus/stm32_rifsc.c | 3 +-- {drivers =3D> include/linux}/bus/stm32_firewall.h | 0 4 files changed, 3 insertions(+), 6 deletions(-) diff --git a/drivers/bus/stm32_etzpc.c b/drivers/bus/stm32_etzpc.c index 7fc0f16960be..4918a14e507e 100644 --- a/drivers/bus/stm32_etzpc.c +++ b/drivers/bus/stm32_etzpc.c @@ -5,6 +5,7 @@ =20 #include #include +#include #include #include #include @@ -16,8 +17,6 @@ #include #include =20 -#include "stm32_firewall.h" - /* * ETZPC registers */ diff --git a/drivers/bus/stm32_firewall.c b/drivers/bus/stm32_firewall.c index 2fc9761dadec..ef4988054b44 100644 --- a/drivers/bus/stm32_firewall.c +++ b/drivers/bus/stm32_firewall.c @@ -5,6 +5,7 @@ =20 #include #include +#include #include #include #include @@ -18,8 +19,6 @@ #include #include =20 -#include "stm32_firewall.h" - /* Corresponds to STM32_FIREWALL_MAX_EXTRA_ARGS + firewall ID */ #define STM32_FIREWALL_MAX_ARGS (STM32_FIREWALL_MAX_EXTRA_ARGS + 1) =20 diff --git a/drivers/bus/stm32_rifsc.c b/drivers/bus/stm32_rifsc.c index 4cf1b60014b7..643ddd0a5f54 100644 --- a/drivers/bus/stm32_rifsc.c +++ b/drivers/bus/stm32_rifsc.c @@ -5,6 +5,7 @@ =20 #include #include +#include #include #include #include @@ -16,8 +17,6 @@ #include #include =20 -#include "stm32_firewall.h" - /* * RIFSC offset register */ diff --git a/drivers/bus/stm32_firewall.h b/include/linux/bus/stm32_firewal= l.h similarity index 100% rename from drivers/bus/stm32_firewall.h rename to include/linux/bus/stm32_firewall.h --=20 2.43.0 From nobody Mon Oct 6 10:13:27 2025 Received: from mx07-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 742D12ED847; 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Allow to query the RCC with a firewall ID. Signed-off-by: Cl=C3=A9ment Le Goffic --- Documentation/devicetree/bindings/clock/st,stm32mp25-rcc.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/st,stm32mp25-rcc.yaml = b/Documentation/devicetree/bindings/clock/st,stm32mp25-rcc.yaml index 88e52f10d1ec..4d471e3d89bc 100644 --- a/Documentation/devicetree/bindings/clock/st,stm32mp25-rcc.yaml +++ b/Documentation/devicetree/bindings/clock/st,stm32mp25-rcc.yaml @@ -31,6 +31,11 @@ properties: '#reset-cells': const: 1 =20 + '#access-controller-cells': + const: 1 + description: + Contains the firewall ID associated to the peripheral. + clocks: items: - description: CK_SCMI_HSE High Speed External oscillator (8 to 48 M= Hz) @@ -123,6 +128,7 @@ required: - reg - '#clock-cells' - '#reset-cells' + - '#access-controller-cells' - clocks =20 additionalProperties: false @@ -136,6 +142,7 @@ examples: reg =3D <0x44200000 0x10000>; #clock-cells =3D <1>; #reset-cells =3D <1>; + #access-controller-cells =3D <1>; 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Tue, 22 Jul 2025 16:03:51 +0200 (CEST) Received: from localhost (10.48.86.185) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Tue, 22 Jul 2025 16:03:51 +0200 From: =?utf-8?q?Cl=C3=A9ment_Le_Goffic?= Date: Tue, 22 Jul 2025 16:03:20 +0200 Subject: [PATCH v3 03/19] clk: stm32mp25: add firewall grant_access ops Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250722-ddrperfm-upstream-v3-3-7b7a4f3dc8a0@foss.st.com> References: <20250722-ddrperfm-upstream-v3-0-7b7a4f3dc8a0@foss.st.com> In-Reply-To: <20250722-ddrperfm-upstream-v3-0-7b7a4f3dc8a0@foss.st.com> To: Will Deacon , Mark Rutland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Philipp Zabel , Jonathan Corbet , Gatien Chevallier , Michael Turquette , Stephen Boyd , Gabriel Fernandez , Krzysztof Kozlowski , Le Goffic , Julius Werner CC: , , , , , , , =?utf-8?q?Cl=C3=A9ment_Le_Goffic?= X-Mailer: b4 0.15-dev-8018a X-ClientProxiedBy: SHFCAS1NODE2.st.com (10.75.129.73) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-22_02,2025-07-21_02,2025-03-28_01 On STM32MP25, the RCC peripheral manages the secure level of resources that are used by other devices such as clocks. Declare this peripheral as a firewall controller. Signed-off-by: Cl=C3=A9ment Le Goffic --- drivers/clk/stm32/clk-stm32mp25.c | 40 +++++++++++++++++++++++++++++++++++= +++- 1 file changed, 39 insertions(+), 1 deletion(-) diff --git a/drivers/clk/stm32/clk-stm32mp25.c b/drivers/clk/stm32/clk-stm3= 2mp25.c index 52f0e8a12926..af4bc06d703a 100644 --- a/drivers/clk/stm32/clk-stm32mp25.c +++ b/drivers/clk/stm32/clk-stm32mp25.c @@ -4,8 +4,10 @@ * Author: Gabriel Fernandez for STMicroel= ectronics. */ =20 +#include #include #include +#include #include #include =20 @@ -1602,6 +1604,11 @@ static int stm32_rcc_get_access(void __iomem *base, = u32 index) return 0; } =20 +static int stm32mp25_rcc_grant_access(struct stm32_firewall_controller *ct= rl, u32 firewall_id) +{ + return stm32_rcc_get_access(ctrl->mmio, firewall_id); +} + static int stm32mp25_check_security(struct device_node *np, void __iomem *= base, const struct clock_config *cfg) { @@ -1970,6 +1977,7 @@ MODULE_DEVICE_TABLE(of, stm32mp25_match_data); =20 static int stm32mp25_rcc_clocks_probe(struct platform_device *pdev) { + struct stm32_firewall_controller *rcc_controller; struct device *dev =3D &pdev->dev; void __iomem *base; int ret; @@ -1982,7 +1990,36 @@ static int stm32mp25_rcc_clocks_probe(struct platfor= m_device *pdev) if (ret) return ret; =20 - return stm32_rcc_init(dev, stm32mp25_match_data, base); + ret =3D stm32_rcc_init(dev, stm32mp25_match_data, base); + if (ret) + return ret; + + rcc_controller =3D devm_kzalloc(&pdev->dev, sizeof(*rcc_controller), GFP_= KERNEL); + if (!rcc_controller) + return -ENOMEM; + + rcc_controller->dev =3D dev; + rcc_controller->mmio =3D base; + rcc_controller->name =3D dev_driver_string(dev); + rcc_controller->type =3D STM32_PERIPHERAL_FIREWALL; + rcc_controller->grant_access =3D stm32mp25_rcc_grant_access; + + platform_set_drvdata(pdev, rcc_controller); + + ret =3D stm32_firewall_controller_register(rcc_controller); + if (ret) { + dev_err(dev, "Couldn't register as a firewall controller: %d\n", ret); + return ret; + } + + return 0; +} + +static void stm32mp25_rcc_clocks_remove(struct platform_device *pdev) +{ + struct stm32_firewall_controller *rcc_controller =3D platform_get_drvdata= (pdev); + + stm32_firewall_controller_unregister(rcc_controller); } =20 static struct platform_driver stm32mp25_rcc_clocks_driver =3D { @@ -1991,6 +2028,7 @@ static struct platform_driver stm32mp25_rcc_clocks_dr= iver =3D { .of_match_table =3D stm32mp25_match_data, }, .probe =3D stm32mp25_rcc_clocks_probe, + .remove =3D stm32mp25_rcc_clocks_remove, }; =20 static int __init stm32mp25_clocks_init(void) --=20 2.43.0 From nobody Mon Oct 6 10:13:27 2025 Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DBE072EE276; Tue, 22 Jul 2025 14:07:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.132.182.106 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753193245; cv=none; b=ZC71PIgBvT2N2oU/UdhUPdtNCjSEujESU1O3mbscMCqYMNd7VupCyE9kBgC1wn79HSTY+YKF/iBcksqvO9lhF5Vl3RSWTqEhct6+fTD178SbllJQsaiKQFpxsil8PgWfa7XFIXDirAifAG/1L93sj0ndICO871nwpwdKaUiKSy0= ARC-Message-Signature: i=1; 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Tue, 22 Jul 2025 16:05:11 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 5922E7A2A44; Tue, 22 Jul 2025 16:03:52 +0200 (CEST) Received: from localhost (10.48.86.185) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Tue, 22 Jul 2025 16:03:52 +0200 From: =?utf-8?q?Cl=C3=A9ment_Le_Goffic?= Date: Tue, 22 Jul 2025 16:03:21 +0200 Subject: [PATCH v3 04/19] arm64: dts: st: set rcc as an access-controller Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250722-ddrperfm-upstream-v3-4-7b7a4f3dc8a0@foss.st.com> References: <20250722-ddrperfm-upstream-v3-0-7b7a4f3dc8a0@foss.st.com> In-Reply-To: <20250722-ddrperfm-upstream-v3-0-7b7a4f3dc8a0@foss.st.com> To: Will Deacon , Mark Rutland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Philipp Zabel , Jonathan Corbet , Gatien Chevallier , Michael Turquette , Stephen Boyd , Gabriel Fernandez , Krzysztof Kozlowski , Le Goffic , Julius Werner CC: , , , , , , , =?utf-8?q?Cl=C3=A9ment_Le_Goffic?= X-Mailer: b4 0.15-dev-8018a X-ClientProxiedBy: SHFCAS1NODE2.st.com (10.75.129.73) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-22_02,2025-07-21_02,2025-03-28_01 RCC now implements firewall access ops to check the access to resources. Allow client nodes to query the RCC with one firewall ID. Signed-off-by: Cl=C3=A9ment Le Goffic --- arch/arm64/boot/dts/st/stm32mp251.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/s= t/stm32mp251.dtsi index 8d87865850a7..0683c2d5cb6f 100644 --- a/arch/arm64/boot/dts/st/stm32mp251.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi @@ -1153,6 +1153,7 @@ rcc: clock-controller@44200000 { reg =3D <0x44200000 0x10000>; #clock-cells =3D <1>; #reset-cells =3D <1>; + #access-controller-cells =3D <1>; clocks =3D <&scmi_clk CK_SCMI_HSE>, <&scmi_clk CK_SCMI_HSI>, <&scmi_clk CK_SCMI_MSI>, --=20 2.43.0 From nobody Mon Oct 6 10:13:27 2025 Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 43DDA2EE980; Tue, 22 Jul 2025 14:07:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.132.182.106 ARC-Seal: i=1; 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Tue, 22 Jul 2025 16:07:07 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 8AC1E4005A; Tue, 22 Jul 2025 16:05:11 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 1EBF87A2A48; Tue, 22 Jul 2025 16:03:53 +0200 (CEST) Received: from localhost (10.48.86.185) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Tue, 22 Jul 2025 16:03:52 +0200 From: =?utf-8?q?Cl=C3=A9ment_Le_Goffic?= Date: Tue, 22 Jul 2025 16:03:22 +0200 Subject: [PATCH v3 05/19] dt-bindings: memory: factorise LPDDR props into memory props Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250722-ddrperfm-upstream-v3-5-7b7a4f3dc8a0@foss.st.com> References: <20250722-ddrperfm-upstream-v3-0-7b7a4f3dc8a0@foss.st.com> In-Reply-To: <20250722-ddrperfm-upstream-v3-0-7b7a4f3dc8a0@foss.st.com> To: Will Deacon , Mark Rutland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Philipp Zabel , Jonathan Corbet , Gatien Chevallier , Michael Turquette , Stephen Boyd , Gabriel Fernandez , Krzysztof Kozlowski , Le Goffic , Julius Werner CC: , , , , , , , =?utf-8?q?Cl=C3=A9ment_Le_Goffic?= X-Mailer: b4 0.15-dev-8018a X-ClientProxiedBy: SHFCAS1NODE2.st.com (10.75.129.73) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-22_02,2025-07-21_02,2025-03-28_01 LPDDR and DDR bindings use the same properties (at least for density, io-width and reg). To avoid bindings duplication, factorise the properties. The compatible description has been updated because the MR (Mode registers) used to get manufacturer ID and revision ID are not present in case of DDR. Those information should be in a SPD (Serial Presence Detect) EEPROM in case of DIMM module or are known in case of soldered memory chips as they are in the datasheet of the memory chips. Signed-off-by: Cl=C3=A9ment Le Goffic --- .../memory-controllers/ddr/jedec,lpddr2.yaml | 2 +- .../memory-controllers/ddr/jedec,lpddr3.yaml | 2 +- .../memory-controllers/ddr/jedec,lpddr4.yaml | 2 +- .../memory-controllers/ddr/jedec,lpddr5.yaml | 2 +- ...ec,lpddr-props.yaml =3D> jedec,memory-props.yaml} | 24 +++++++++++++---= ------ 5 files changed, 18 insertions(+), 14 deletions(-) diff --git a/Documentation/devicetree/bindings/memory-controllers/ddr/jedec= ,lpddr2.yaml b/Documentation/devicetree/bindings/memory-controllers/ddr/jed= ec,lpddr2.yaml index a237bc259273..f290a25675b2 100644 --- a/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr2= .yaml +++ b/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr2= .yaml @@ -10,7 +10,7 @@ maintainers: - Krzysztof Kozlowski =20 allOf: - - $ref: jedec,lpddr-props.yaml# + - $ref: jedec,memory-props.yaml# =20 properties: compatible: diff --git a/Documentation/devicetree/bindings/memory-controllers/ddr/jedec= ,lpddr3.yaml b/Documentation/devicetree/bindings/memory-controllers/ddr/jed= ec,lpddr3.yaml index e328a1195ba6..994127dbcdca 100644 --- a/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr3= .yaml +++ b/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr3= .yaml @@ -10,7 +10,7 @@ maintainers: - Krzysztof Kozlowski =20 allOf: - - $ref: jedec,lpddr-props.yaml# + - $ref: jedec,memory-props.yaml# =20 properties: compatible: diff --git a/Documentation/devicetree/bindings/memory-controllers/ddr/jedec= ,lpddr4.yaml b/Documentation/devicetree/bindings/memory-controllers/ddr/jed= ec,lpddr4.yaml index a078892fecee..753376a3ad1f 100644 --- a/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr4= .yaml +++ b/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr4= .yaml @@ -10,7 +10,7 @@ maintainers: - Krzysztof Kozlowski =20 allOf: - - $ref: jedec,lpddr-props.yaml# + - $ref: jedec,memory-props.yaml# =20 properties: compatible: diff --git a/Documentation/devicetree/bindings/memory-controllers/ddr/jedec= ,lpddr5.yaml b/Documentation/devicetree/bindings/memory-controllers/ddr/jed= ec,lpddr5.yaml index e441dac5f154..27e2bbdb631d 100644 --- a/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr5= .yaml +++ b/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr5= .yaml @@ -10,7 +10,7 @@ maintainers: - Krzysztof Kozlowski =20 allOf: - - $ref: jedec,lpddr-props.yaml# + - $ref: jedec,memory-props.yaml# =20 properties: compatible: diff --git a/Documentation/devicetree/bindings/memory-controllers/ddr/jedec= ,lpddr-props.yaml b/Documentation/devicetree/bindings/memory-controllers/dd= r/jedec,memory-props.yaml similarity index 72% rename from Documentation/devicetree/bindings/memory-controllers/ddr/jedec,= lpddr-props.yaml rename to Documentation/devicetree/bindings/memory-controllers/ddr/jedec,me= mory-props.yaml index 30267ce70124..0bc919fd8b53 100644 --- a/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr-= props.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,memory= -props.yaml @@ -1,16 +1,16 @@ # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- -$id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr-prop= s.yaml# +$id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,memory-pro= ps.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# =20 -title: Common properties for LPDDR types +title: Common properties for memory types =20 description: - Different LPDDR types generally use the same properties and only differ = in the + Different memory types generally use the same properties and only differ= in the range of legal values for each. This file defines the common parts that = can be reused for each type. Nodes using this schema should generally be nested= under - an LPDDR channel node. + an memory channel node. =20 maintainers: - Krzysztof Kozlowski @@ -21,14 +21,15 @@ properties: Compatible strings can be either explicit vendor names and part numb= ers (e.g. elpida,ECB240ABACN), or generated strings of the form lpddrX-YY,ZZZZ where X is the LPDDR version, YY is the manufacturer = ID - (from MR5) and ZZZZ is the revision ID (from MR6 and MR7). Both IDs = are - formatted in lower case hexadecimal representation with leading zero= es. + (from MR5 in case of LPDDR) and ZZZZ is the revision ID (from MR6 an= d MR7 + in case of LPDDR). Both IDs are formatted in lower case hexadecimal + representation with leading zeroes. The latter form can be useful when LPDDR nodes are created at runtim= e by boot firmware that doesn't have access to static part number informa= tion. =20 reg: description: - The rank number of this LPDDR rank when used as a subnode to an LPDDR + The rank number of this memory rank when used as a subnode to an mem= ory channel. minimum: 0 maximum: 3 @@ -36,7 +37,8 @@ properties: revision-id: $ref: /schemas/types.yaml#/definitions/uint32-array description: - Revision IDs read from Mode Register 6 and 7. One byte per uint32 ce= ll (i.e. ). + Revision IDs read from Mode Register 6 and 7 in case of LPDDR. + One byte per uint32 cell (i.e. ). maxItems: 2 items: minimum: 0 @@ -45,7 +47,8 @@ properties: density: $ref: /schemas/types.yaml#/definitions/uint32 description: - Density in megabits of SDRAM chip. Decoded from Mode Register 8. + Density in megabits of SDRAM chip. Decoded from Mode Register 8 in c= ase of + LPDDR. enum: - 64 - 128 @@ -65,7 +68,8 @@ properties: io-width: $ref: /schemas/types.yaml#/definitions/uint32 description: - IO bus width in bits of SDRAM chip. Decoded from Mode Register 8. + IO bus width in bits of SDRAM chip. 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Signed-off-by: Cl=C3=A9ment Le Goffic --- .../memory-controllers/ddr/jedec,ddr4.yaml | 34 ++++++++++++++++++= ++++ 1 file changed, 34 insertions(+) diff --git a/Documentation/devicetree/bindings/memory-controllers/ddr/jedec= ,ddr4.yaml b/Documentation/devicetree/bindings/memory-controllers/ddr/jedec= ,ddr4.yaml new file mode 100644 index 000000000000..117af9ac599b --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,ddr4.y= aml @@ -0,0 +1,34 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,ddr4.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: DDR3 SDRAM compliant to JEDEC JESD79-4D + +maintainers: + - Krzysztof Kozlowski + +allOf: + - $ref: jedec,memory-props.yaml# + +properties: + compatible: + items: + - pattern: "^ddr4-[0-9a-f]{2},[0-9a-f]{4}$" + - const: jedec,ddr4 + +required: + - compatible + - density + - io-width + +unevaluatedProperties: false + +examples: + - | + ddr { + compatible =3D "ddr4-ff,000f", "jedec,ddr4"; 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Signed-off-by: Cl=C3=A9ment Le Goffic --- ...pddr-channel.yaml =3D> jedec,memory-channel.yaml} | 26 +++++++++++-----= ------ 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/Documentation/devicetree/bindings/memory-controllers/ddr/jedec= ,lpddr-channel.yaml b/Documentation/devicetree/bindings/memory-controllers/= ddr/jedec,memory-channel.yaml similarity index 82% rename from Documentation/devicetree/bindings/memory-controllers/ddr/jedec,= lpddr-channel.yaml rename to Documentation/devicetree/bindings/memory-controllers/ddr/jedec,me= mory-channel.yaml index 34b5bd153f63..3bf3a63466eb 100644 --- a/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr-= channel.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,memory= -channel.yaml @@ -1,16 +1,16 @@ # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- -$id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr-chan= nel.yaml# +$id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,memory-cha= nnel.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# =20 -title: LPDDR channel with chip/rank topology description +title: Memory channel with chip/rank topology description =20 description: - An LPDDR channel is a completely independent set of LPDDR pins (DQ, CA, = CS, - CK, etc.) that connect one or more LPDDR chips to a host system. The main - purpose of this node is to overall LPDDR topology of the system, includi= ng the - amount of individual LPDDR chips and the ranks per chip. + A memory channel is a completely independent set of pins (DQ, CA, CS, + CK, etc.) that connect one or more memory chips to a host system. The ma= in + purpose of this node is to overall memory topology of the system, includ= ing the + amount of individual memory chips and the ranks per chip. =20 maintainers: - Julius Werner @@ -26,14 +26,14 @@ properties: io-width: description: The number of DQ pins in the channel. If this number is different - from (a multiple of) the io-width of the LPDDR chip, that means that + from (a multiple of) the io-width of the memory chip, that means that multiple instances of that type of chip are wired in parallel on this channel (with the channel's DQ pins split up between the different chips, and the CA, CS, etc. pins of the different chips all shorted together). This means that the total physical memory controlled by a channel is equal to the sum of the densities of each rank on the - connected LPDDR chip, times the io-width of the channel divided by - the io-width of the LPDDR chip. + connected memory chip, times the io-width of the channel divided by + the io-width of the memory chip. enum: - 8 - 16 @@ -51,8 +51,8 @@ patternProperties: "^rank@[0-9]+$": type: object description: - Each physical LPDDR chip may have one or more ranks. Ranks are - internal but fully independent sub-units of the chip. Each LPDDR bus + Each physical memory chip may have one or more ranks. Ranks are + internal but fully independent sub-units of the chip. Each memory bus transaction on the channel targets exactly one rank, based on the state of the CS pins. Different ranks may have different densities a= nd timing requirements. @@ -107,7 +107,7 @@ additionalProperties: false =20 examples: - | - lpddr-channel0 { + memory-channel0 { #address-cells =3D <1>; #size-cells =3D <0>; compatible =3D "jedec,lpddr3-channel"; @@ -122,7 +122,7 @@ examples: }; }; =20 - lpddr-channel1 { + memory-channel1 { #address-cells =3D <1>; #size-cells =3D <0>; compatible =3D "jedec,lpddr4-channel"; --=20 2.43.0 From nobody Mon Oct 6 10:13:27 2025 Received: from mx07-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 958C02E49AF; Tue, 22 Jul 2025 14:07:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=91.207.212.93 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753193242; cv=none; b=R0xDusrfCxB7XBgY04j43eyhp/WE4MjOrv9cS+YDG4aDW7IyWFrRaUE4gGhh8IPCiAm4ueEA38ok5Aaf1d31aYeFYud1jDJ9+tfFZrP0noT4evB/RReVpn28KcjGkWVputXbN7Mj2F8Knr5xmu7lUW4Y7NFKUutq6b9w+wh83zU= ARC-Message-Signature: i=1; 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Signed-off-by: Cl=C3=A9ment Le Goffic --- .../bindings/memory-controllers/ddr/jedec,memory-channel.yaml | 10 ++++++= ++++ 1 file changed, 10 insertions(+) diff --git a/Documentation/devicetree/bindings/memory-controllers/ddr/jedec= ,memory-channel.yaml b/Documentation/devicetree/bindings/memory-controllers= /ddr/jedec,memory-channel.yaml index 3bf3a63466eb..03252d97ac38 100644 --- a/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,memory= -channel.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,memory= -channel.yaml @@ -18,6 +18,7 @@ maintainers: properties: compatible: enum: + - jedec,ddr4-channel - jedec,lpddr2-channel - jedec,lpddr3-channel - jedec,lpddr4-channel @@ -60,6 +61,15 @@ patternProperties: - reg =20 allOf: + - if: + properties: + compatible: + contains: + const: jedec,ddr4-channel + then: + patternProperties: + "^rank@[0-9]+$": + $ref: /schemas/memory-controllers/ddr/jedec,ddr4.yaml# - if: properties: compatible: --=20 2.43.0 From nobody Mon Oct 6 10:13:27 2025 Received: from mx07-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C3BA52ECE8B; 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Signed-off-by: Cl=C3=A9ment Le Goffic --- arch/arm64/boot/dts/st/stm32mp257f-dk.dts | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp257f-dk.dts b/arch/arm64/boot/dt= s/st/stm32mp257f-dk.dts index a278a1e3ce03..a97b41f14ecc 100644 --- a/arch/arm64/boot/dts/st/stm32mp257f-dk.dts +++ b/arch/arm64/boot/dts/st/stm32mp257f-dk.dts @@ -54,6 +54,13 @@ led-blue { }; }; =20 + lpddr_channel: lpddr4-channel { + #address-cells =3D <1>; + #size-cells =3D <0>; + compatible =3D "jedec,lpddr4-channel"; + io-width =3D <32>; + }; + memory@80000000 { device_type =3D "memory"; reg =3D <0x0 0x80000000 0x1 0x0>; --=20 2.43.0 From nobody Mon Oct 6 10:13:27 2025 Received: from mx08-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CB51B2EAB83; Tue, 22 Jul 2025 14:06:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Signed-off-by: Cl=C3=A9ment Le Goffic --- arch/arm64/boot/dts/st/stm32mp257f-ev1.dts | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts b/arch/arm64/boot/d= ts/st/stm32mp257f-ev1.dts index 2f561ad40665..cd2fe81bf934 100644 --- a/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts +++ b/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts @@ -41,6 +41,13 @@ pad_clk: pad-clk { }; }; =20 + ddr_channel: ddr4-channel { + #address-cells =3D <1>; + #size-cells =3D <0>; + compatible =3D "jedec,ddr4-channel"; + io-width =3D <32>; + }; + imx335_2v9: regulator-2v9 { compatible =3D "regulator-fixed"; regulator-name =3D "imx335-avdd"; --=20 2.43.0 From nobody Mon Oct 6 10:13:27 2025 Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 165602EB5D5; Tue, 22 Jul 2025 14:07:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Tue, 22 Jul 2025 16:06:44 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 1F8134004F; Tue, 22 Jul 2025 16:05:15 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id A79077A31F8; Tue, 22 Jul 2025 16:03:57 +0200 (CEST) Received: from localhost (10.48.86.185) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Tue, 22 Jul 2025 16:03:57 +0200 From: =?utf-8?q?Cl=C3=A9ment_Le_Goffic?= Date: Tue, 22 Jul 2025 16:03:28 +0200 Subject: [PATCH v3 11/19] dt-bindings: perf: stm32: introduce DDRPERFM dt-bindings Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250722-ddrperfm-upstream-v3-11-7b7a4f3dc8a0@foss.st.com> References: <20250722-ddrperfm-upstream-v3-0-7b7a4f3dc8a0@foss.st.com> In-Reply-To: <20250722-ddrperfm-upstream-v3-0-7b7a4f3dc8a0@foss.st.com> To: Will Deacon , Mark Rutland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Philipp Zabel , Jonathan Corbet , Gatien Chevallier , Michael Turquette , Stephen Boyd , Gabriel Fernandez , Krzysztof Kozlowski , Le Goffic , Julius Werner CC: , , , , , , , =?utf-8?q?Cl=C3=A9ment_Le_Goffic?= X-Mailer: b4 0.15-dev-8018a X-ClientProxiedBy: SHFCAS1NODE2.st.com (10.75.129.73) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-22_02,2025-07-21_02,2025-03-28_01 DDRPERFM is the DDR Performance Monitor embedded in STM32MPU SoC. It allows to monitor DDR events that come from the DDR Controller such as read or write events. Signed-off-by: Cl=C3=A9ment Le Goffic --- .../devicetree/bindings/perf/st,stm32-ddr-pmu.yaml | 94 ++++++++++++++++++= ++++ 1 file changed, 94 insertions(+) diff --git a/Documentation/devicetree/bindings/perf/st,stm32-ddr-pmu.yaml b= /Documentation/devicetree/bindings/perf/st,stm32-ddr-pmu.yaml new file mode 100644 index 000000000000..34e1bba65f04 --- /dev/null +++ b/Documentation/devicetree/bindings/perf/st,stm32-ddr-pmu.yaml @@ -0,0 +1,94 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/perf/st,stm32-ddr-pmu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +maintainers: + - Cl=C3=A9ment Le Goffic + +title: STMicroelectronics STM32 DDR Performance Monitor (DDRPERFM) + +properties: + compatible: + oneOf: + - items: + - const: st,stm32mp131-ddr-pmu + - items: + - enum: + - st,stm32mp151-ddr-pmu + - const: st,stm32mp131-ddr-pmu + - items: + - const: st,stm32mp251-ddr-pmu + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + resets: + maxItems: 1 + + access-controllers: + minItems: 1 + maxItems: 2 + + memory-channel: + description: + The memory channel this DDRPERFM is attached to. + $ref: /schemas/types.yaml#/definitions/phandle + +required: + - compatible + - reg + +allOf: + - if: + properties: + compatible: + contains: + const: st,stm32mp131-ddr-pmu + then: + required: + - clocks + - resets + + - if: + properties: + compatible: + contains: + const: st,stm32mp251-ddr-pmu + then: + required: + - access-controllers + - memory-channel + +additionalProperties: false + +examples: + - | + #include + #include + + perf@5a007000 { + compatible =3D "st,stm32mp151-ddr-pmu", "st,stm32mp131-ddr-pmu"; + reg =3D <0x5a007000 0x400>; + clocks =3D <&rcc DDRPERFM>; + resets =3D <&rcc DDRPERFM_R>; + }; + + - | + ddr_channel: ddr3-channel { + #address-cells =3D <1>; + #size-cells =3D <0>; + compatible =3D "jedec,ddr3-channel"; + io-width =3D <16>; + }; + + perf@48041000 { + compatible =3D "st,stm32mp251-ddr-pmu"; + reg =3D <0x48041000 0x400>; + access-controllers =3D <&rcc 104>; + memory-channel =3D <&ddr_channel>; + }; --=20 2.43.0 From nobody Mon Oct 6 10:13:27 2025 Received: from mx07-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7AC2B2EBBA2; Tue, 22 Jul 2025 14:07:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=91.207.212.93 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753193227; cv=none; b=d7tvnykbDsRxfF2Oeqaa2XcgNoAH8bEqUMgN1CT6JYpsWkWkSLk/Qa+epCqQrhtvDimR0z+3mtd8fqW/ngrsVHPhb5gyplG432v77PVv046S+w8my8Ixx49yAMSzopViL2Juz35du6B+76oO4XRmgrcTAzALjLF3VbsG/1C0Ueo= ARC-Message-Signature: i=1; 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Tue, 22 Jul 2025 16:05:08 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 7DFBB7A31F6; Tue, 22 Jul 2025 16:03:58 +0200 (CEST) Received: from localhost (10.48.86.185) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Tue, 22 Jul 2025 16:03:58 +0200 From: =?utf-8?q?Cl=C3=A9ment_Le_Goffic?= Date: Tue, 22 Jul 2025 16:03:29 +0200 Subject: [PATCH v3 12/19] perf: stm32: introduce DDRPERFM driver Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250722-ddrperfm-upstream-v3-12-7b7a4f3dc8a0@foss.st.com> References: <20250722-ddrperfm-upstream-v3-0-7b7a4f3dc8a0@foss.st.com> In-Reply-To: <20250722-ddrperfm-upstream-v3-0-7b7a4f3dc8a0@foss.st.com> To: Will Deacon , Mark Rutland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Philipp Zabel , Jonathan Corbet , Gatien Chevallier , Michael Turquette , Stephen Boyd , Gabriel Fernandez , Krzysztof Kozlowski , Le Goffic , Julius Werner CC: , , , , , , , =?utf-8?q?Cl=C3=A9ment_Le_Goffic?= X-Mailer: b4 0.15-dev-8018a X-ClientProxiedBy: SHFCAS1NODE2.st.com (10.75.129.73) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-22_02,2025-07-21_02,2025-03-28_01 Introduce the driver for the DDR Performance Monitor available on STM32MPU SoC. On STM32MP2 platforms, the DDRPERFM allows to monitor up to 8 DDR events that come from the DDR Controller such as read or write events. On STM32MP1 platforms, the DDRPERFM cannot monitor any event on any counter, there is a notion of set of events. Events from different sets cannot be monitored at the same time. The first chosen event selects the set. The set is coded in the first two bytes of the config value which is on 4 bytes. On STM32MP25x series, the DDRPERFM clock is shared with the DDR controller and may be secured by bootloaders. Access controllers allow to check access to a resource. Use the access controller defined in the devicetree to know about the access to the DDRPERFM clock. Signed-off-by: Cl=C3=A9ment Le Goffic --- drivers/perf/Kconfig | 11 + drivers/perf/Makefile | 1 + drivers/perf/stm32_ddr_pmu.c | 896 +++++++++++++++++++++++++++++++++++++++= ++++ 3 files changed, 908 insertions(+) diff --git a/drivers/perf/Kconfig b/drivers/perf/Kconfig index 278c929dc87a..5118535134ee 100644 --- a/drivers/perf/Kconfig +++ b/drivers/perf/Kconfig @@ -198,6 +198,17 @@ config QCOM_L3_PMU Adds the L3 cache PMU into the perf events subsystem for monitoring L3 cache events. =20 +config STM32_DDR_PMU + tristate "STM32 DDR PMU" + depends on ARCH_STM32 || COMPILE_TEST + default m + help + Provides support for the DDR performance monitor on STM32MPU platforms. + The monitor provides counters for memory related events. + It allows developers to analyze and optimize DDR performance. + Enabling this feature is useful for performance tuning and debugging me= mory + subsystem issues on supported hardware. + config THUNDERX2_PMU tristate "Cavium ThunderX2 SoC PMU UNCORE" depends on ARCH_THUNDER2 || COMPILE_TEST diff --git a/drivers/perf/Makefile b/drivers/perf/Makefile index de71d2574857..7f83b50feb71 100644 --- a/drivers/perf/Makefile +++ b/drivers/perf/Makefile @@ -20,6 +20,7 @@ obj-$(CONFIG_RISCV_PMU) +=3D riscv_pmu.o obj-$(CONFIG_RISCV_PMU_LEGACY) +=3D riscv_pmu_legacy.o obj-$(CONFIG_RISCV_PMU_SBI) +=3D riscv_pmu_sbi.o obj-$(CONFIG_STARFIVE_STARLINK_PMU) +=3D starfive_starlink_pmu.o +obj-$(CONFIG_STM32_DDR_PMU) +=3D stm32_ddr_pmu.o obj-$(CONFIG_THUNDERX2_PMU) +=3D thunderx2_pmu.o obj-$(CONFIG_XGENE_PMU) +=3D xgene_pmu.o obj-$(CONFIG_ARM_SPE_PMU) +=3D arm_spe_pmu.o diff --git a/drivers/perf/stm32_ddr_pmu.c b/drivers/perf/stm32_ddr_pmu.c new file mode 100644 index 000000000000..d09c1375a41f --- /dev/null +++ b/drivers/perf/stm32_ddr_pmu.c @@ -0,0 +1,896 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2025, STMicroelectronics - All Rights Reserved + * Author: Cl=C3=A9ment Le Goffic for STMic= roelectronics. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define DRIVER_NAME "stm32_ddr_pmu" + +/* + * The PMU is able to freeze all counters and generate an interrupt when t= here + * is a counter overflow. But, relying on this means that we lose all the + * events that occur between the freeze and the interrupt handler executio= n. + * So we use a polling mechanism to avoid this lost of information. + * The fastest counter can overflow in ~7s @600MHz (that is the maximum DDR + * frequency supported on STM32MP257), so we poll in 3.5s intervals to ens= ure + * we don't reach this limit. + */ +#define POLL_MS 3500 + +#define DDRPERFM_CTRL 0x000 +#define DDRPERFM_CFG 0x004 +#define DDRPERFM_STATUS 0x008 +#define DDRPERFM_CLR 0x00C +#define DDRPERFM_TCNT 0x020 +#define DDRPERFM_EVCNT(X) (0x030 + 8 * (X)) + +#define DDRPERFM_MP2_CFG0 0x010 +#define DDRPERFM_MP2_CFG1 0x014 +#define DDRPERFM_MP2_CFG5 0x024 +#define DDRPERFM_MP2_DRAMINF 0x028 +#define DDRPERFM_MP2_EVCNT(X) (0x040 + 4 * (X)) +#define DDRPERFM_MP2_TCNT 0x060 +#define DDRPERFM_MP2_STATUS 0x080 + +#define MP1_STATUS_BUSY BIT(16) +#define MP2_STATUS_BUSY BIT(31) + +#define CTRL_START BIT(0) +#define CTRL_STOP BIT(1) + +#define CFG_SEL_MSK GENMASK(17, 16) +#define CFG_SEL_SHIFT 16 +#define CFG_EN_MSK GENMASK(3, 0) + +#define MP1_CLR_CNT GENMASK(3, 0) +#define MP1_CLR_TIME BIT(31) +#define MP2_CLR_CNT GENMASK(7, 0) +#define MP2_CLR_TIME BIT(8) + +/* 4 event counters plus 1 dedicated to time */ +#define MP1_CNT_NB (4 + 1) +/* Index of the time dedicated counter */ +#define MP1_TIME_CNT_IDX 4 + +/* 8 event counters plus 1 dedicated to time */ +#define MP2_CNT_NB (8 + 1) +/* Index of the time dedicated counter */ +#define MP2_TIME_CNT_IDX 8 +/* 4 event counters per register */ +#define MP2_CNT_SEL_PER_REG 4 + +/* Arbitrary value used to identify a time event */ +#define TIME_CNT 64 + +struct stm32_ddr_pmu_reg { + unsigned int reg; + u32 mask; +}; + +struct stm32_ddr_cnt { + int idx; + struct perf_event *evt; + struct list_head cnt_list; +}; + +struct stm32_ddr_pmu_regspec { + const struct stm32_ddr_pmu_reg stop; + const struct stm32_ddr_pmu_reg start; + const struct stm32_ddr_pmu_reg enable; + const struct stm32_ddr_pmu_reg status; + const struct stm32_ddr_pmu_reg clear_cnt; + const struct stm32_ddr_pmu_reg clear_time; + const struct stm32_ddr_pmu_reg cfg; + const struct stm32_ddr_pmu_reg cfg0; + const struct stm32_ddr_pmu_reg cfg1; + const struct stm32_ddr_pmu_reg dram_inf; + const struct stm32_ddr_pmu_reg counter_time; + const struct stm32_ddr_pmu_reg counter_evt[]; +}; + +struct stm32_ddr_pmu { + struct pmu pmu; + void __iomem *membase; + struct device *dev; + struct clk *clk; + const struct stm32_ddr_pmu_cfg *cfg; + struct hrtimer hrtimer; + ktime_t poll_period; + int selected_set; + u32 dram_type; + struct list_head counters[]; +}; + +struct stm32_ddr_pmu_cfg { + const struct stm32_ddr_pmu_regspec *regs; + const struct attribute_group **attribute; + u32 counters_nb; + u32 evt_counters_nb; + u32 time_cnt_idx; + struct stm32_ddr_cnt * (*get_counter)(struct stm32_ddr_pmu *p, struct per= f_event *e); +}; + +#define STM32_DDR_PMU_EVENT_NUMBER(group, index) (((group) << 8) | (index)) +#define STM32_DDR_PMU_GROUP_VALUE(event_number) ((event_number) >> 8) +#define STM32_DDR_PMU_EVENT_INDEX(event_number) ((event_number) & 0xFF) + +/* MP1 ddrperfm events */ +enum stm32_ddr_pmu_events_mp1 { + PERF_OP_IS_RD =3D STM32_DDR_PMU_EVENT_NUMBER(0, 0), + PERF_OP_IS_WR =3D STM32_DDR_PMU_EVENT_NUMBER(0, 1), + PERF_OP_IS_ACTIVATE =3D STM32_DDR_PMU_EVENT_NUMBER(0, 2), + CTL_IDLE =3D STM32_DDR_PMU_EVENT_NUMBER(0, 3), + PERF_HPR_REQ_WITH_NO_CREDIT =3D STM32_DDR_PMU_EVENT_NUMBER(1, 0), + PERF_LPR_REQ_WITH_NO_CREDIT =3D STM32_DDR_PMU_EVENT_NUMBER(1, 1), + CACTIVE_DDRC =3D STM32_DDR_PMU_EVENT_NUMBER(1, 3), + PERF_OP_IS_ENTER_POWERDOWN =3D STM32_DDR_PMU_EVENT_NUMBER(2, 0), + PERF_OP_IS_REFRESH =3D STM32_DDR_PMU_EVENT_NUMBER(2, 1), + PERF_SELFRESH_MODE =3D STM32_DDR_PMU_EVENT_NUMBER(2, 2), + DFI_LP_REQ =3D STM32_DDR_PMU_EVENT_NUMBER(2, 3), + PERF_HPR_XACT_WHEN_CRITICAL =3D STM32_DDR_PMU_EVENT_NUMBER(3, 0), + PERF_LPR_XACT_WHEN_CRITICAL =3D STM32_DDR_PMU_EVENT_NUMBER(3, 1), + PERF_WR_XACT_WHEN_CRITICAL =3D STM32_DDR_PMU_EVENT_NUMBER(3, 2), + DFI_LP_REQ_SCND =3D STM32_DDR_PMU_EVENT_NUMBER(3, 3), +}; + +/* MP2 ddrperfm events */ +enum stm32_ddr_pmu_events_mp2 { + DFI_IS_ACT =3D STM32_DDR_PMU_EVENT_NUMBER(0, 0), + DFI_IS_PREPB =3D STM32_DDR_PMU_EVENT_NUMBER(0, 1), + DFI_IS_PREAB =3D STM32_DDR_PMU_EVENT_NUMBER(0, 2), + DFI_IS_RD =3D STM32_DDR_PMU_EVENT_NUMBER(0, 3), + DFI_IS_RDA =3D STM32_DDR_PMU_EVENT_NUMBER(0, 4), + DFI_IS_WR =3D STM32_DDR_PMU_EVENT_NUMBER(0, 6), + DFI_IS_WRA =3D STM32_DDR_PMU_EVENT_NUMBER(0, 7), + DFI_IS_MWR =3D STM32_DDR_PMU_EVENT_NUMBER(0, 9), + DFI_IS_MWRA =3D STM32_DDR_PMU_EVENT_NUMBER(0, 10), + DFI_IS_MRW =3D STM32_DDR_PMU_EVENT_NUMBER(0, 12), + DFI_IS_MRR =3D STM32_DDR_PMU_EVENT_NUMBER(0, 13), + DFI_IS_REFPB =3D STM32_DDR_PMU_EVENT_NUMBER(0, 14), + DFI_IS_REFAB =3D STM32_DDR_PMU_EVENT_NUMBER(0, 15), + DFI_IS_MPC =3D STM32_DDR_PMU_EVENT_NUMBER(0, 16), + PERF_OP_IS_ACT =3D STM32_DDR_PMU_EVENT_NUMBER(0, 32), + PERF_OP_IS_RD_MP2 =3D STM32_DDR_PMU_EVENT_NUMBER(0, 33), + PERF_OP_IS_WR_MP2 =3D STM32_DDR_PMU_EVENT_NUMBER(0, 34), + PERF_OP_IS_MWR =3D STM32_DDR_PMU_EVENT_NUMBER(0, 35), + PERF_OP_IS_REF =3D STM32_DDR_PMU_EVENT_NUMBER(0, 36), + PERF_OP_IS_CRIT_REF =3D STM32_DDR_PMU_EVENT_NUMBER(0, 37), + PERF_OP_IS_SPEC_REF =3D STM32_DDR_PMU_EVENT_NUMBER(0, 38), + PERF_OP_IS_ZQCAL =3D STM32_DDR_PMU_EVENT_NUMBER(0, 39), + PERF_OP_IS_ENTER_POWDN =3D STM32_DDR_PMU_EVENT_NUMBER(0, 40), + PERF_OP_IS_ENTER_SELFREF =3D STM32_DDR_PMU_EVENT_NUMBER(0, 41), + PERF_OP_IS_PRE =3D STM32_DDR_PMU_EVENT_NUMBER(0, 42), + PERF_OP_IS_PRE_FOR_RDWR =3D STM32_DDR_PMU_EVENT_NUMBER(0, 43), + PERF_OP_IS_PRE_FOR_OTHERS =3D STM32_DDR_PMU_EVENT_NUMBER(0, 44), + PERF_OP_IS_RD_ACTIVATE =3D STM32_DDR_PMU_EVENT_NUMBER(0, 45), + PERF_HPR_REQ_WITH_NOCREDIT =3D STM32_DDR_PMU_EVENT_NUMBER(0, 48), + PERF_LPR_REQ_WITH_NOCREDIT =3D STM32_DDR_PMU_EVENT_NUMBER(0, 49), + PERF_HPR_XACT_WHEN_CRITICAL_MP2 =3D STM32_DDR_PMU_EVENT_NUMBER(0, 50), + PERF_LPR_XACT_WHEN_CRITICAL_MP2 =3D STM32_DDR_PMU_EVENT_NUMBER(0, 51), + PERF_WR_XACT_WHEN_CRITICAL_MP2 =3D STM32_DDR_PMU_EVENT_NUMBER(0, 52), + PERF_RDWR_TRANSITIONS =3D STM32_DDR_PMU_EVENT_NUMBER(0, 53), + PERF_WAR_HAZARD =3D STM32_DDR_PMU_EVENT_NUMBER(0, 54), + PERF_RAW_HAZARD =3D STM32_DDR_PMU_EVENT_NUMBER(0, 55), + PERF_WAW_HAZARD =3D STM32_DDR_PMU_EVENT_NUMBER(0, 56), + PERF_RANK =3D STM32_DDR_PMU_EVENT_NUMBER(0, 58), + PERF_READ_BYPASS =3D STM32_DDR_PMU_EVENT_NUMBER(0, 59), + PERF_ACT_BYPASS =3D STM32_DDR_PMU_EVENT_NUMBER(0, 60), + PERF_WINDOW_LIMIT_REACHED_RD =3D STM32_DDR_PMU_EVENT_NUMBER(0, 61), + PERF_WINDOW_LIMIT_REACHED_WR =3D STM32_DDR_PMU_EVENT_NUMBER(0, 62), + NO_EVENT =3D STM32_DDR_PMU_EVENT_NUMBER(0, 63), +}; + +enum stm32_ddr_pmu_memory_type { + STM32_DDR_PMU_LPDDR4, + STM32_DDR_PMU_LPDDR3, + STM32_DDR_PMU_DDR4, + STM32_DDR_PMU_DDR3, +}; + +static struct stm32_ddr_pmu *to_stm32_ddr_pmu(struct pmu *p) +{ + return container_of(p, struct stm32_ddr_pmu, pmu); +} + +static struct stm32_ddr_pmu *hrtimer_to_stm32_ddr_pmu(struct hrtimer *h) +{ + return container_of(h, struct stm32_ddr_pmu, hrtimer); +} + +static void stm32_ddr_start_counters(struct stm32_ddr_pmu *pmu) +{ + const struct stm32_ddr_pmu_regspec *r =3D pmu->cfg->regs; + + writel_relaxed(r->start.mask, pmu->membase + r->start.reg); +} + +static void stm32_ddr_stop_counters(struct stm32_ddr_pmu *pmu) +{ + const struct stm32_ddr_pmu_regspec *r =3D pmu->cfg->regs; + + writel_relaxed(r->stop.mask, pmu->membase + r->stop.reg); +} + +static void stm32_ddr_clear_time_counter(struct stm32_ddr_pmu *pmu) +{ + const struct stm32_ddr_pmu_regspec *r =3D pmu->cfg->regs; + + writel_relaxed(r->clear_time.mask, pmu->membase + r->clear_time.reg); +} + +static void stm32_ddr_clear_event_counter(struct stm32_ddr_pmu *pmu, struc= t stm32_ddr_cnt *counter) +{ + const struct stm32_ddr_pmu_regspec *r =3D pmu->cfg->regs; + + writel_relaxed(r->clear_cnt.mask & BIT(counter->idx), pmu->membase + r->c= lear_cnt.reg); +} + +static void stm32_ddr_clear_counter(struct stm32_ddr_pmu *pmu, struct stm3= 2_ddr_cnt *counter) +{ + const struct stm32_ddr_pmu_regspec *r =3D pmu->cfg->regs; + u32 status =3D readl_relaxed(pmu->membase + r->status.reg); + + if (counter->idx =3D=3D pmu->cfg->time_cnt_idx) + stm32_ddr_clear_time_counter(pmu); + else + stm32_ddr_clear_event_counter(pmu, counter); + + if (status & r->status.mask) + dev_err(pmu->dev, "Failed to clear counter %i because the PMU is busy\n", + counter->idx); +} + +static void stm32_ddr_counter_enable(struct stm32_ddr_pmu *pmu, struct stm= 32_ddr_cnt *counter) +{ + const struct stm32_ddr_pmu_regspec *r =3D pmu->cfg->regs; + u32 val =3D readl_relaxed(pmu->membase + r->enable.reg); + + val |=3D BIT(counter->idx); + writel_relaxed(val, pmu->membase + r->enable.reg); +} + +static void stm32_ddr_counter_disable(struct stm32_ddr_pmu *pmu, struct st= m32_ddr_cnt *counter) +{ + const struct stm32_ddr_pmu_regspec *r =3D pmu->cfg->regs; + u32 val =3D readl_relaxed(pmu->membase + r->enable.reg); + + val &=3D ~BIT(counter->idx); + writel_relaxed(val, pmu->membase + r->enable.reg); +} + +static int stm32_ddr_sel_evnt(struct stm32_ddr_pmu *pmu, struct stm32_ddr_= cnt *counter) +{ + const struct stm32_ddr_pmu_regspec *r =3D pmu->cfg->regs; + u32 cnt_sel_val; + + u32 group_val =3D STM32_DDR_PMU_GROUP_VALUE(counter->evt->attr.config); + u32 evt_val =3D STM32_DDR_PMU_EVENT_INDEX(counter->evt->attr.config); + + if (pmu->selected_set !=3D -1 && pmu->selected_set !=3D group_val) { + dev_err(pmu->dev, "Selected events are from different set\n"); + return -EINVAL; + } + pmu->selected_set =3D group_val; + + if (pmu->cfg->regs->cfg.reg) { + cnt_sel_val =3D readl_relaxed(pmu->membase + r->cfg.reg); + cnt_sel_val &=3D ~CFG_SEL_MSK; + cnt_sel_val |=3D (CFG_SEL_MSK & (group_val << CFG_SEL_SHIFT)); + writel_relaxed(cnt_sel_val, pmu->membase + r->cfg.reg); + + return 0; + } + + /* We assume cfg0 and cfg1 are filled in the match data */ + u32 cnt_idx =3D counter->idx; + u32 cnt_sel_evt_reg =3D r->cfg0.reg; + + if (!(cnt_idx < MP2_CNT_SEL_PER_REG)) { + cnt_sel_evt_reg =3D r->cfg1.reg; + cnt_idx -=3D MP2_CNT_SEL_PER_REG; + } + + cnt_sel_val =3D readl_relaxed(pmu->membase + cnt_sel_evt_reg); + cnt_sel_val &=3D ~GENMASK(8 * cnt_idx + 7, 8 * cnt_idx); + cnt_sel_val |=3D evt_val << (8 * cnt_idx); + + writel_relaxed(cnt_sel_val, pmu->membase + cnt_sel_evt_reg); + + return 0; +} + +static struct stm32_ddr_cnt *stm32_ddr_pmu_get_event_counter_mp1(struct st= m32_ddr_pmu *pmu, + struct perf_event *event) +{ + u32 config =3D event->attr.config; + u32 event_idx =3D STM32_DDR_PMU_EVENT_INDEX(config); + struct stm32_ddr_cnt *cnt; + + cnt =3D kzalloc(sizeof(*cnt), GFP_KERNEL); + if (!cnt) + return ERR_PTR(-ENOMEM); + + cnt->evt =3D event; + cnt->idx =3D event_idx; + event->pmu_private =3D cnt; + list_add(&cnt->cnt_list, &pmu->counters[event_idx]); + + return cnt; +} + +static struct stm32_ddr_cnt *stm32_ddr_pmu_get_event_counter_mp2(struct st= m32_ddr_pmu *pmu, + struct perf_event *event) +{ + struct stm32_ddr_cnt *cnt; + int idx =3D -1; + + /* Loop on all the counters except TIME_CNT_IDX */ + for (int i =3D 0; i < pmu->cfg->evt_counters_nb; i++) { + u64 config; + + if (list_empty(&pmu->counters[i])) { + idx =3D i; + continue; + } + config =3D list_first_entry(&pmu->counters[i], struct stm32_ddr_cnt, + cnt_list)->evt->attr.config; + if (config =3D=3D event->attr.config) { + idx =3D i; + break; + } + } + + if (idx =3D=3D -1) + return ERR_PTR(-ENOENT); + + cnt =3D kzalloc(sizeof(*cnt), GFP_KERNEL); + if (!cnt) + return ERR_PTR(-ENOMEM); + + cnt->evt =3D event; + cnt->idx =3D idx; + event->pmu_private =3D cnt; + + list_add(&cnt->cnt_list, &pmu->counters[idx]); + + return cnt; +} + +static inline struct stm32_ddr_cnt *stm32_get_event_counter(struct stm32_d= dr_pmu *pmu, + struct perf_event *event) +{ + return pmu->cfg->get_counter(pmu, event); +} + +static int stm32_ddr_pmu_get_counter(struct stm32_ddr_pmu *pmu, struct per= f_event *event) +{ + u32 time_cnt_idx =3D pmu->cfg->time_cnt_idx; + u32 config =3D event->attr.config; + struct stm32_ddr_cnt *cnt; + + pmu->selected_set =3D STM32_DDR_PMU_GROUP_VALUE(config); + + if (config =3D=3D TIME_CNT) { + cnt =3D kzalloc(sizeof(*cnt), GFP_KERNEL); + if (!cnt) + return -ENOMEM; + + cnt->evt =3D event; + cnt->idx =3D time_cnt_idx; + event->pmu_private =3D cnt; + list_add(&cnt->cnt_list, &pmu->counters[time_cnt_idx]); + + return 0; + } + + cnt =3D stm32_get_event_counter(pmu, event); + if (IS_ERR(cnt)) + return PTR_ERR(cnt); + + if (list_count_nodes(&cnt->cnt_list) =3D=3D 1) { + stm32_ddr_stop_counters(pmu); + stm32_ddr_sel_evnt(pmu, cnt); + stm32_ddr_counter_enable(pmu, cnt); + stm32_ddr_start_counters(pmu); + } + + return 0; +} + +static void stm32_ddr_pmu_free_counter(struct stm32_ddr_pmu *pmu, + struct stm32_ddr_cnt *counter) +{ + size_t count =3D list_count_nodes(&counter->cnt_list); + + if (counter->evt->attr.config !=3D TIME_CNT && count =3D=3D 1) + stm32_ddr_counter_disable(pmu, counter); + + list_del(&counter->cnt_list); + kfree(counter); +} + +static void stm32_ddr_pmu_event_update_list(struct stm32_ddr_pmu *pmu, str= uct list_head *list) +{ + struct stm32_ddr_cnt *counter =3D list_first_entry(list, struct stm32_ddr= _cnt, cnt_list); + const struct stm32_ddr_pmu_regspec *r =3D pmu->cfg->regs; + u32 val; + + if (counter->evt->attr.config !=3D TIME_CNT) + val =3D readl_relaxed(pmu->membase + r->counter_evt[counter->idx].reg); + else + val =3D readl_relaxed(pmu->membase + r->counter_time.reg); + + stm32_ddr_clear_counter(pmu, counter); + + list_for_each_entry(counter, list, cnt_list) + local64_add(val, &counter->evt->count); +} + +static void stm32_ddr_pmu_event_read(struct perf_event *event) +{ + struct stm32_ddr_pmu *pmu =3D to_stm32_ddr_pmu(event->pmu); + struct stm32_ddr_cnt *cnt =3D event->pmu_private; + + hrtimer_start(&pmu->hrtimer, pmu->poll_period, HRTIMER_MODE_REL_PINNED); + + stm32_ddr_stop_counters(pmu); + + stm32_ddr_pmu_event_update_list(pmu, &pmu->counters[cnt->idx]); + + stm32_ddr_start_counters(pmu); +} + +static void stm32_ddr_pmu_event_start(struct perf_event *event, int flags) +{ + struct stm32_ddr_pmu *pmu =3D to_stm32_ddr_pmu(event->pmu); + struct stm32_ddr_cnt *counter =3D event->pmu_private; + struct hw_perf_event *hw =3D &event->hw; + + if (WARN_ON_ONCE(!(hw->state & PERF_HES_STOPPED))) + return; + + if (flags & PERF_EF_RELOAD) + WARN_ON_ONCE(!(hw->state & PERF_HES_UPTODATE)); + + stm32_ddr_stop_counters(pmu); + + if (list_count_nodes(&counter->cnt_list) =3D=3D 1) + stm32_ddr_clear_counter(pmu, counter); + else + stm32_ddr_pmu_event_update_list(pmu, &pmu->counters[counter->idx]); + + stm32_ddr_start_counters(pmu); + local64_set(&hw->prev_count, 0); + hw->state =3D 0; +} + +static void stm32_ddr_pmu_event_stop(struct perf_event *event, int flags) +{ + struct hw_perf_event *hw =3D &event->hw; + + if (WARN_ON_ONCE(hw->state & PERF_HES_STOPPED)) + return; + + hw->state |=3D PERF_HES_STOPPED; + + if (flags & PERF_EF_UPDATE) { + stm32_ddr_pmu_event_read(event); + hw->state |=3D PERF_HES_UPTODATE; + } +} + +static int stm32_ddr_pmu_event_add(struct perf_event *event, int flags) +{ + struct stm32_ddr_pmu *pmu =3D to_stm32_ddr_pmu(event->pmu); + int ret; + + clk_enable(pmu->clk); + + hrtimer_start(&pmu->hrtimer, pmu->poll_period, HRTIMER_MODE_REL_PINNED); + + ret =3D stm32_ddr_pmu_get_counter(pmu, event); + if (ret) + return ret; + + event->hw.state =3D PERF_HES_STOPPED | PERF_HES_UPTODATE; + + if (flags & PERF_EF_START) + stm32_ddr_pmu_event_start(event, flags); + + return 0; +} + +static void stm32_ddr_pmu_event_del(struct perf_event *event, int flags) +{ + struct stm32_ddr_pmu *pmu =3D to_stm32_ddr_pmu(event->pmu); + struct stm32_ddr_cnt *counter =3D event->pmu_private; + bool events =3D true; + + stm32_ddr_pmu_event_stop(event, PERF_EF_UPDATE); + + stm32_ddr_pmu_free_counter(pmu, counter); + + for (int i =3D 0; i < pmu->cfg->counters_nb; i++) + events =3D !list_empty(&pmu->counters[i]); + + /* If there is activity nothing to do */ + if (events) + return; + + hrtimer_cancel(&pmu->hrtimer); + stm32_ddr_stop_counters(pmu); + + pmu->selected_set =3D -1; + + clk_disable(pmu->clk); +} + +static int stm32_ddr_pmu_event_init(struct perf_event *event) +{ + if (event->attr.type !=3D event->pmu->type) + return -ENOENT; + + if (is_sampling_event(event) || event->attach_state & PERF_ATTACH_TASK) + return -EINVAL; + + return 0; +} + +static enum hrtimer_restart stm32_ddr_pmu_poll(struct hrtimer *hrtimer) +{ + struct stm32_ddr_pmu *pmu =3D hrtimer_to_stm32_ddr_pmu(hrtimer); + + stm32_ddr_stop_counters(pmu); + + for (int i =3D 0; i < MP2_CNT_NB; i++) + if (!list_empty(&pmu->counters[i])) + stm32_ddr_pmu_event_update_list(pmu, &pmu->counters[i]); + + if (list_empty(&pmu->counters[pmu->cfg->time_cnt_idx])) + stm32_ddr_clear_time_counter(pmu); + + stm32_ddr_start_counters(pmu); + + hrtimer_forward_now(hrtimer, pmu->poll_period); + + return HRTIMER_RESTART; +} + +static ssize_t stm32_ddr_pmu_sysfs_show(struct device *dev, struct device_= attribute *attr, + char *buf) +{ + struct perf_pmu_events_attr *pmu_attr; + + pmu_attr =3D container_of(attr, struct perf_pmu_events_attr, attr); + + return sysfs_emit(buf, "event=3D0x%02llx\n", pmu_attr->id); +} + +static int stm32_ddr_pmu_get_memory_type(struct stm32_ddr_pmu *pmu) +{ + struct platform_device *pdev =3D to_platform_device(pmu->dev); + struct device_node *memchan; + + memchan =3D of_parse_phandle(pdev->dev.of_node, "memory-channel", 0); + if (!memchan) + return dev_err_probe(&pdev->dev, -EINVAL, + "Missing device-tree property 'memory-channel'\n"); + + if (of_device_is_compatible(memchan, "jedec,lpddr4-channel")) + pmu->dram_type =3D STM32_DDR_PMU_LPDDR4; + else if (of_device_is_compatible(memchan, "jedec,lpddr3-channel")) + pmu->dram_type =3D STM32_DDR_PMU_LPDDR3; + else if (of_device_is_compatible(memchan, "jedec,ddr4-channel")) + pmu->dram_type =3D STM32_DDR_PMU_DDR4; + else if (of_device_is_compatible(memchan, "jedec,ddr3-channel")) + pmu->dram_type =3D STM32_DDR_PMU_DDR3; + else + return dev_err_probe(&pdev->dev, -EINVAL, "Unsupported memory channel ty= pe\n"); + + if (pmu->dram_type =3D=3D STM32_DDR_PMU_LPDDR3) + dev_warn(&pdev->dev, + "LPDDR3 supported by DDRPERFM but not supported by DDRCTRL/DDRPHY\n"); + + return 0; +} + +#define STM32_DDR_PMU_EVENT_ATTR(_name, _id) \ + PMU_EVENT_ATTR_ID(_name, stm32_ddr_pmu_sysfs_show, _id) + +static struct attribute *stm32_ddr_pmu_events_attrs_mp[] =3D { + STM32_DDR_PMU_EVENT_ATTR(perf_op_is_rd, PERF_OP_IS_RD), + STM32_DDR_PMU_EVENT_ATTR(perf_op_is_wr, PERF_OP_IS_WR), + STM32_DDR_PMU_EVENT_ATTR(perf_op_is_activate, PERF_OP_IS_ACTIVATE), + STM32_DDR_PMU_EVENT_ATTR(ctl_idle, CTL_IDLE), + STM32_DDR_PMU_EVENT_ATTR(perf_hpr_req_with_no_credit, PERF_HPR_REQ_WITH_N= O_CREDIT), + STM32_DDR_PMU_EVENT_ATTR(perf_lpr_req_with_no_credit, PERF_LPR_REQ_WITH_N= O_CREDIT), + STM32_DDR_PMU_EVENT_ATTR(cactive_ddrc, CACTIVE_DDRC), + STM32_DDR_PMU_EVENT_ATTR(perf_op_is_enter_powerdown, PERF_OP_IS_ENTER_POW= ERDOWN), + STM32_DDR_PMU_EVENT_ATTR(perf_op_is_refresh, PERF_OP_IS_REFRESH), + STM32_DDR_PMU_EVENT_ATTR(perf_selfresh_mode, PERF_SELFRESH_MODE), + STM32_DDR_PMU_EVENT_ATTR(dfi_lp_req, DFI_LP_REQ), + STM32_DDR_PMU_EVENT_ATTR(perf_hpr_xact_when_critical, PERF_HPR_XACT_WHEN_= CRITICAL), + STM32_DDR_PMU_EVENT_ATTR(perf_lpr_xact_when_critical, PERF_LPR_XACT_WHEN_= CRITICAL), + STM32_DDR_PMU_EVENT_ATTR(perf_wr_xact_when_critical, PERF_WR_XACT_WHEN_CR= ITICAL), + STM32_DDR_PMU_EVENT_ATTR(dfi_lp_req_cpy, DFI_LP_REQ), /* Suffixed '_cpy'= to allow the + * choice between sets 2 and 3 + */ + STM32_DDR_PMU_EVENT_ATTR(time_cnt, TIME_CNT), + NULL, +}; + +static struct attribute_group stm32_ddr_pmu_events_attrs_group_mp =3D { + .name =3D "events", + .attrs =3D stm32_ddr_pmu_events_attrs_mp, +}; + +static struct attribute *stm32_ddr_pmu_events_attrs_mp2[] =3D { + STM32_DDR_PMU_EVENT_ATTR(dfi_is_act, DFI_IS_ACT), + STM32_DDR_PMU_EVENT_ATTR(dfi_is_prepb, DFI_IS_PREPB), + STM32_DDR_PMU_EVENT_ATTR(dfi_is_preab, DFI_IS_PREAB), + STM32_DDR_PMU_EVENT_ATTR(dfi_is_rd, DFI_IS_RD), + STM32_DDR_PMU_EVENT_ATTR(dfi_is_rda, DFI_IS_RDA), + STM32_DDR_PMU_EVENT_ATTR(dfi_is_wr, DFI_IS_WR), + STM32_DDR_PMU_EVENT_ATTR(dfi_is_wra, DFI_IS_WRA), + STM32_DDR_PMU_EVENT_ATTR(dfi_is_mwr, DFI_IS_MWR), + STM32_DDR_PMU_EVENT_ATTR(dfi_is_mwra, DFI_IS_MWRA), + STM32_DDR_PMU_EVENT_ATTR(dfi_is_mrw, DFI_IS_MRW), + STM32_DDR_PMU_EVENT_ATTR(dfi_is_mrr, DFI_IS_MRR), + STM32_DDR_PMU_EVENT_ATTR(dfi_is_refpb, DFI_IS_REFPB), + STM32_DDR_PMU_EVENT_ATTR(dfi_is_refab, DFI_IS_REFAB), + STM32_DDR_PMU_EVENT_ATTR(dfi_is_mpc, DFI_IS_MPC), + STM32_DDR_PMU_EVENT_ATTR(perf_op_is_act, PERF_OP_IS_ACT), + STM32_DDR_PMU_EVENT_ATTR(perf_op_is_rd, PERF_OP_IS_RD), + STM32_DDR_PMU_EVENT_ATTR(perf_op_is_wr, PERF_OP_IS_WR), + STM32_DDR_PMU_EVENT_ATTR(perf_op_is_mwr, PERF_OP_IS_MWR), + STM32_DDR_PMU_EVENT_ATTR(perf_op_is_ref, PERF_OP_IS_REF), + STM32_DDR_PMU_EVENT_ATTR(perf_op_is_crit_ref, PERF_OP_IS_CRIT_REF), + STM32_DDR_PMU_EVENT_ATTR(perf_op_is_spec_ref, PERF_OP_IS_SPEC_REF), + STM32_DDR_PMU_EVENT_ATTR(perf_op_is_zqcal, PERF_OP_IS_ZQCAL), + STM32_DDR_PMU_EVENT_ATTR(perf_op_is_enter_powdn, PERF_OP_IS_ENTER_POWDN), + STM32_DDR_PMU_EVENT_ATTR(perf_op_is_enter_selfref, PERF_OP_IS_ENTER_SELFR= EF), + STM32_DDR_PMU_EVENT_ATTR(perf_op_is_pre, PERF_OP_IS_PRE), + STM32_DDR_PMU_EVENT_ATTR(perf_op_is_pre_for_rdwr, PERF_OP_IS_PRE_FOR_RDWR= ), + STM32_DDR_PMU_EVENT_ATTR(perf_op_is_pre_for_others, PERF_OP_IS_PRE_FOR_OT= HERS), + STM32_DDR_PMU_EVENT_ATTR(perf_op_is_rd_activate, PERF_OP_IS_RD_ACTIVATE), + STM32_DDR_PMU_EVENT_ATTR(perf_hpr_req_with_nocredit, PERF_HPR_REQ_WITH_NO= CREDIT), + STM32_DDR_PMU_EVENT_ATTR(perf_lpr_req_with_nocredit, PERF_LPR_REQ_WITH_NO= CREDIT), + STM32_DDR_PMU_EVENT_ATTR(perf_hpr_xact_when_critical, PERF_HPR_XACT_WHEN_= CRITICAL), + STM32_DDR_PMU_EVENT_ATTR(perf_lpr_xact_when_critical, PERF_LPR_XACT_WHEN_= CRITICAL), + STM32_DDR_PMU_EVENT_ATTR(perf_wr_xact_when_critical, PERF_WR_XACT_WHEN_CR= ITICAL), + STM32_DDR_PMU_EVENT_ATTR(perf_rdwr_transitions, PERF_RDWR_TRANSITIONS), + STM32_DDR_PMU_EVENT_ATTR(perf_war_hazard, PERF_WAR_HAZARD), + STM32_DDR_PMU_EVENT_ATTR(perf_raw_hazard, PERF_RAW_HAZARD), + STM32_DDR_PMU_EVENT_ATTR(perf_waw_hazard, PERF_WAW_HAZARD), + STM32_DDR_PMU_EVENT_ATTR(perf_rank, PERF_RANK), + STM32_DDR_PMU_EVENT_ATTR(perf_read_bypass, PERF_READ_BYPASS), + STM32_DDR_PMU_EVENT_ATTR(perf_act_bypass, PERF_ACT_BYPASS), + STM32_DDR_PMU_EVENT_ATTR(perf_window_limit_reached_rd, PERF_WINDOW_LIMIT_= REACHED_RD), + STM32_DDR_PMU_EVENT_ATTR(perf_window_limit_reached_wr, PERF_WINDOW_LIMIT_= REACHED_WR), + STM32_DDR_PMU_EVENT_ATTR(time_cnt, TIME_CNT), + NULL +}; + +static struct attribute_group stm32_ddr_pmu_events_attrs_group_mp2 =3D { + .name =3D "events", + .attrs =3D stm32_ddr_pmu_events_attrs_mp2, +}; + +PMU_FORMAT_ATTR(event, "config:0-8"); + +static struct attribute *stm32_ddr_pmu_format_attrs[] =3D { + &format_attr_event.attr, + NULL +}; + +static const struct attribute_group stm32_ddr_pmu_format_attr_group =3D { + .name =3D "format", + .attrs =3D stm32_ddr_pmu_format_attrs, +}; + +static const struct attribute_group *stm32_ddr_pmu_attr_groups_mp1[] =3D { + &stm32_ddr_pmu_events_attrs_group_mp, + &stm32_ddr_pmu_format_attr_group, + NULL +}; + +static const struct attribute_group *stm32_ddr_pmu_attr_groups_mp2[] =3D { + &stm32_ddr_pmu_events_attrs_group_mp2, + &stm32_ddr_pmu_format_attr_group, + NULL +}; + +static int stm32_ddr_pmu_device_probe(struct platform_device *pdev) +{ + struct stm32_firewall firewall; + struct stm32_ddr_pmu *pmu; + struct reset_control *rst; + struct resource *res; + int ret; + + pmu =3D devm_kzalloc(&pdev->dev, struct_size(pmu, counters, MP2_CNT_NB), = GFP_KERNEL); + if (!pmu) + return -ENOMEM; + + platform_set_drvdata(pdev, pmu); + pmu->dev =3D &pdev->dev; + + pmu->cfg =3D device_get_match_data(pmu->dev); + + pmu->membase =3D devm_platform_get_and_ioremap_resource(pdev, 0, &res); + if (IS_ERR(pmu->membase)) + return PTR_ERR(pmu->membase); + + if (of_property_present(pmu->dev->of_node, "access-controllers")) { + ret =3D stm32_firewall_get_firewall(pmu->dev->of_node, &firewall, 1); + if (ret) + return dev_err_probe(pmu->dev, ret, "Failed to get firewall\n"); + ret =3D stm32_firewall_grant_access_by_id(&firewall, firewall.firewall_i= d); + if (ret) + return dev_err_probe(pmu->dev, ret, "Failed to grant access\n"); + } + + pmu->clk =3D devm_clk_get_optional_enabled(pmu->dev, NULL); + if (IS_ERR(pmu->clk)) + return dev_err_probe(pmu->dev, PTR_ERR(pmu->clk), "Failed to get prepare= clock\n"); + + rst =3D devm_reset_control_get_optional_exclusive(pmu->dev, NULL); + if (IS_ERR(rst)) + return dev_err_probe(pmu->dev, PTR_ERR(rst), "Failed to get reset\n"); + + reset_control_assert(rst); + reset_control_deassert(rst); + + pmu->poll_period =3D ms_to_ktime(POLL_MS); + hrtimer_setup(&pmu->hrtimer, stm32_ddr_pmu_poll, CLOCK_MONOTONIC, HRTIMER= _MODE_REL); + + for (int i =3D 0; i < MP2_CNT_NB; i++) + INIT_LIST_HEAD(&pmu->counters[i]); + + pmu->selected_set =3D -1; + + pmu->pmu =3D (struct pmu) { + .task_ctx_nr =3D perf_invalid_context, + .start =3D stm32_ddr_pmu_event_start, + .stop =3D stm32_ddr_pmu_event_stop, + .add =3D stm32_ddr_pmu_event_add, + .del =3D stm32_ddr_pmu_event_del, + .read =3D stm32_ddr_pmu_event_read, + .event_init =3D stm32_ddr_pmu_event_init, + .attr_groups =3D pmu->cfg->attribute, + .module =3D THIS_MODULE, + }; + + if (pmu->cfg->regs->dram_inf.reg) { + ret =3D stm32_ddr_pmu_get_memory_type(pmu); + if (ret) + return dev_err_probe(pmu->dev, ret, "Failed to get memory type\n"); + + writel_relaxed(pmu->dram_type, pmu->membase + pmu->cfg->regs->dram_inf.r= eg); + } + + ret =3D perf_pmu_register(&pmu->pmu, DRIVER_NAME, -1); + if (ret) + return dev_err_probe(pmu->dev, ret, + "Couldn't register DDRPERFM driver as a PMU\n"); + + clk_disable(pmu->clk); + + return 0; +} + +static void stm32_ddr_pmu_device_remove(struct platform_device *pdev) +{ + struct stm32_ddr_pmu *stm32_ddr_pmu =3D platform_get_drvdata(pdev); + + perf_pmu_unregister(&stm32_ddr_pmu->pmu); +} + +static int __maybe_unused stm32_ddr_pmu_device_resume(struct device *dev) +{ + struct stm32_ddr_pmu *pmu =3D dev_get_drvdata(dev); + + clk_enable(pmu->clk); + writel_relaxed(pmu->dram_type, pmu->membase + pmu->cfg->regs->dram_inf.re= g); + clk_disable(pmu->clk); + + return 0; +} + +static const struct stm32_ddr_pmu_regspec stm32_ddr_pmu_regspec_mp1 =3D { + .stop =3D { DDRPERFM_CTRL, CTRL_STOP }, + .start =3D { DDRPERFM_CTRL, CTRL_START }, + .enable =3D { DDRPERFM_CFG }, + .cfg =3D { DDRPERFM_CFG }, + .status =3D { DDRPERFM_STATUS, MP1_STATUS_BUSY }, + .clear_cnt =3D { DDRPERFM_CLR, MP1_CLR_CNT }, + .clear_time =3D { DDRPERFM_CLR, MP1_CLR_TIME }, + .counter_time =3D { DDRPERFM_TCNT }, + .counter_evt =3D { + { DDRPERFM_EVCNT(0) }, + { DDRPERFM_EVCNT(1) }, + { DDRPERFM_EVCNT(2) }, + { DDRPERFM_EVCNT(3) }, + }, +}; + +static const struct stm32_ddr_pmu_regspec stm32_ddr_pmu_regspec_mp2 =3D { + .stop =3D { DDRPERFM_CTRL, CTRL_STOP }, + .start =3D { DDRPERFM_CTRL, CTRL_START }, + .status =3D { DDRPERFM_MP2_STATUS, MP2_STATUS_BUSY }, + .clear_cnt =3D { DDRPERFM_CLR, MP2_CLR_CNT }, + .clear_time =3D { DDRPERFM_CLR, MP2_CLR_TIME }, + .cfg0 =3D { DDRPERFM_MP2_CFG0 }, + .cfg1 =3D { DDRPERFM_MP2_CFG1 }, + .enable =3D { DDRPERFM_MP2_CFG5 }, + .dram_inf =3D { DDRPERFM_MP2_DRAMINF }, + .counter_time =3D { DDRPERFM_MP2_TCNT }, + .counter_evt =3D { + { DDRPERFM_MP2_EVCNT(0) }, + { DDRPERFM_MP2_EVCNT(1) }, + { DDRPERFM_MP2_EVCNT(2) }, + { DDRPERFM_MP2_EVCNT(3) }, + { DDRPERFM_MP2_EVCNT(4) }, + { DDRPERFM_MP2_EVCNT(5) }, + { DDRPERFM_MP2_EVCNT(6) }, + { DDRPERFM_MP2_EVCNT(7) }, + }, +}; + +static const struct stm32_ddr_pmu_cfg stm32_ddr_pmu_cfg_mp1 =3D { + .regs =3D &stm32_ddr_pmu_regspec_mp1, + .attribute =3D stm32_ddr_pmu_attr_groups_mp1, + .counters_nb =3D MP1_CNT_NB, + .evt_counters_nb =3D MP1_CNT_NB - 1, /* Time counter is not an event coun= ter */ + .time_cnt_idx =3D MP1_TIME_CNT_IDX, + .get_counter =3D stm32_ddr_pmu_get_event_counter_mp1, +}; + +static const struct stm32_ddr_pmu_cfg stm32_ddr_pmu_cfg_mp2 =3D { + .regs =3D &stm32_ddr_pmu_regspec_mp2, + .attribute =3D stm32_ddr_pmu_attr_groups_mp2, + .counters_nb =3D MP2_CNT_NB, + .evt_counters_nb =3D MP2_CNT_NB - 1, /* Time counter is an event counter = */ + .time_cnt_idx =3D MP2_TIME_CNT_IDX, + .get_counter =3D stm32_ddr_pmu_get_event_counter_mp2, +}; + +static DEFINE_SIMPLE_DEV_PM_OPS(stm32_ddr_pmu_pm_ops, NULL, stm32_ddr_pmu_= device_resume); + +static const struct of_device_id stm32_ddr_pmu_of_match[] =3D { + { + .compatible =3D "st,stm32mp131-ddr-pmu", + .data =3D &stm32_ddr_pmu_cfg_mp1 + }, + { + .compatible =3D "st,stm32mp251-ddr-pmu", + .data =3D &stm32_ddr_pmu_cfg_mp2 + }, + { } +}; +MODULE_DEVICE_TABLE(of, stm32_ddr_pmu_of_match); + +static struct platform_driver stm32_ddr_pmu_driver =3D { + .driver =3D { + .name =3D DRIVER_NAME, + .pm =3D pm_sleep_ptr(&stm32_ddr_pmu_pm_ops), + .of_match_table =3D stm32_ddr_pmu_of_match, + }, + .probe =3D stm32_ddr_pmu_device_probe, + .remove =3D stm32_ddr_pmu_device_remove, +}; + +module_platform_driver(stm32_ddr_pmu_driver); + +MODULE_AUTHOR("Cl=C3=A9ment Le Goffic"); +MODULE_DESCRIPTION("STMicroelectronics STM32 DDR performance monitor drive= r"); +MODULE_LICENSE("GPL"); --=20 2.43.0 From nobody Mon Oct 6 10:13:27 2025 Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DFA132EE962; Tue, 22 Jul 2025 14:07:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.132.182.106 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753193247; cv=none; b=QaksPLqbDpV10wWZT3hY/mcZi5IhhikYb6zvvOg907ash4pBE78XubX/ksHiB1Or/L1WJ/XOhi3sPI35/aWslgo/zo8qZ+Z1/puqy+9e2ro5UiB9CEuIyw9LQuqbcFyIrB6TRiaRB+mmdjLCO8wsQRKHuQrzYOH84H0f4sqLRtY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753193247; c=relaxed/simple; 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Tue, 22 Jul 2025 16:05:20 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 3B9987A3203; Tue, 22 Jul 2025 16:03:59 +0200 (CEST) Received: from localhost (10.48.86.185) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Tue, 22 Jul 2025 16:03:58 +0200 From: =?utf-8?q?Cl=C3=A9ment_Le_Goffic?= Date: Tue, 22 Jul 2025 16:03:30 +0200 Subject: [PATCH v3 13/19] Documentation: perf: stm32: add ddrperfm support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250722-ddrperfm-upstream-v3-13-7b7a4f3dc8a0@foss.st.com> References: <20250722-ddrperfm-upstream-v3-0-7b7a4f3dc8a0@foss.st.com> In-Reply-To: <20250722-ddrperfm-upstream-v3-0-7b7a4f3dc8a0@foss.st.com> To: Will Deacon , Mark Rutland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Philipp Zabel , Jonathan Corbet , Gatien Chevallier , Michael Turquette , Stephen Boyd , Gabriel Fernandez , Krzysztof Kozlowski , Le Goffic , Julius Werner CC: , , , , , , , =?utf-8?q?Cl=C3=A9ment_Le_Goffic?= X-Mailer: b4 0.15-dev-8018a X-ClientProxiedBy: SHFCAS1NODE2.st.com (10.75.129.73) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-22_02,2025-07-21_02,2025-03-28_01 The DDRPERFM is the DDR Performance Monitor embedded in STM32MPU SoC. This documentation introduces the DDRPERFM, the stm32-ddr-pmu driver supporting it and how to use it with the perf tool. Signed-off-by: Cl=C3=A9ment Le Goffic --- Documentation/admin-guide/perf/index.rst | 1 + Documentation/admin-guide/perf/stm32-ddr-pmu.rst | 86 ++++++++++++++++++++= ++++ 2 files changed, 87 insertions(+) diff --git a/Documentation/admin-guide/perf/index.rst b/Documentation/admin= -guide/perf/index.rst index 072b510385c4..33aedc4ee5c3 100644 --- a/Documentation/admin-guide/perf/index.rst +++ b/Documentation/admin-guide/perf/index.rst @@ -29,3 +29,4 @@ Performance monitor support cxl ampere_cspmu mrvl-pem-pmu + stm32-ddr-pmu diff --git a/Documentation/admin-guide/perf/stm32-ddr-pmu.rst b/Documentati= on/admin-guide/perf/stm32-ddr-pmu.rst new file mode 100644 index 000000000000..5b02bf44dd7a --- /dev/null +++ b/Documentation/admin-guide/perf/stm32-ddr-pmu.rst @@ -0,0 +1,86 @@ +.. SPDX-License-Identifier: GPL-2.0 + +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +STM32 DDR Performance Monitor (DDRPERFM) +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +The DDRPERFM is the DDR Performance Monitor embedded in STM32MPU SoC. +The DDR controller provides events to DDRPERFM, once selected they are cou= nted in the DDRPERFM +peripheral. + +In MP1 family, the DDRPERFM is able to count 4 different events at the sam= e time. +However, the 4 events must belong to the same set. +One hardware counter is dedicated to the time counter, `time_cnt`. + +In MP2 family, the DDRPERFM is able to select between 44 different DDR eve= nts. +As for MP1, there is a dedicated hardware counter for the time. +It is incremented every 4 DDR clock cycles. +All the other counters can be freely allocated to count any other DDR even= t. + +The stm32-ddr-pmu driver relies on the perf PMU framework to expose the co= unters via sysfs: + +On MP1: + + .. code-block:: bash + + $ ls /sys/bus/event_source/devices/stm32_ddr_pmu/events/ + cactive_ddrc perf_lpr_req_with_no_credit perf_op_= is_wr + ctl_idle perf_lpr_xact_when_critical perf_sel= fresh_mode + dfi_lp_req perf_op_is_activate perf_wr_= xact_when_critical + dfi_lp_req_cpy perf_op_is_enter_powerdown time_cnt + perf_hpr_req_with_no_credit perf_op_is_rd + perf_hpr_xact_when_critical perf_op_is_refresh + +On MP2: + + .. code-block:: bash + + $ ls /sys/bus/event_source/devices/stm32_ddr_pmu/events/ + dfi_is_act perf_hpr_req_with_nocredit perf_op_is_spec_ref + dfi_is_mpc perf_hpr_xact_when_critical perf_op_is_wr + dfi_is_mrr perf_lpr_req_with_nocredit perf_op_is_zqcal + dfi_is_mrw perf_lpr_xact_when_critical perf_rank + dfi_is_mwr perf_op_is_act perf_raw_hazard + dfi_is_mwra perf_op_is_crit_ref perf_rdwr_transitions + dfi_is_preab perf_op_is_enter_powdn perf_read_bypass + dfi_is_prepb perf_op_is_enter_selfref perf_war_hazard + dfi_is_rd perf_op_is_mwr perf_waw_hazard + dfi_is_rda perf_op_is_pre perf_window_limit_re= ached_rd + dfi_is_refab perf_op_is_pre_for_others perf_window_limit_re= ached_wr + dfi_is_refpb perf_op_is_pre_for_rdwr perf_wr_xact_when_cr= itical + dfi_is_wr perf_op_is_rd time_cnt + dfi_is_wra perf_op_is_rd_activate + perf_act_bypass perf_op_is_ref + + +The perf PMU framework is usually invoked via the 'perf stat' tool. + + +Example: + + .. code-block:: bash + + $ perf stat --timeout 60000 -e stm32_ddr_pmu/dfi_is_act/,\ + > stm32_ddr_pmu/dfi_is_rd/,\ + > stm32_ddr_pmu/dfi_is_wr/,\ + > stm32_ddr_pmu/dfi_is_refab/,\ + > stm32_ddr_pmu/dfi_is_mrw/,\ + > stm32_ddr_pmu/dfi_is_rda/,\ + > stm32_ddr_pmu/dfi_is_wra/,\ + > stm32_ddr_pmu/dfi_is_mrr/,\ + > stm32_ddr_pmu/time_cnt/ \ + > -a sleep 5 + + Performance counter stats for 'system wide': + + 481025 stm32_ddr_pmu/dfi_is_act/ + 732166 stm32_ddr_pmu/dfi_is_rd/ + 144926 stm32_ddr_pmu/dfi_is_wr/ + 644154 stm32_ddr_pmu/dfi_is_refab/ + 0 stm32_ddr_pmu/dfi_is_mrw/ + 0 stm32_ddr_pmu/dfi_is_rda/ + 0 stm32_ddr_pmu/dfi_is_wra/ + 0 stm32_ddr_pmu/dfi_is_mrr/ + 752347686 stm32_ddr_pmu/time_cnt/ + + 5.014910750 seconds time elapsed --=20 2.43.0 From nobody Mon Oct 6 10:13:27 2025 Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 64CDB2EA140; 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Signed-off-by: Cl=C3=A9ment Le Goffic --- MAINTAINERS | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 10850512c118..247f07ae4176 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -23487,6 +23487,13 @@ S: Maintained F: Documentation/devicetree/bindings/power/supply/st,stc3117.yaml F: drivers/power/supply/stc3117_fuel_gauge.c =20 +ST STM32 DDR PMU +M: Cl=C3=A9ment Le Goffic +S: Maintained +F: Documentation/admin-guide/perf/stm32-ddr-pmu.rst +F: Documentation/devicetree/bindings/perf/st,stm32-ddr-pmu.yaml +F: drivers/perf/stm32_ddr-pmu.c + ST STM32 FIREWALL M: Gatien Chevallier S: Maintained --=20 2.43.0 From nobody Mon Oct 6 10:13:27 2025 Received: from mx07-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 167B42EE26E; Tue, 22 Jul 2025 14:07:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Tue, 22 Jul 2025 16:07:10 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id A8BBA40047; Tue, 22 Jul 2025 16:05:23 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id B50297A31FC; Tue, 22 Jul 2025 16:04:00 +0200 (CEST) Received: from localhost (10.48.86.185) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Tue, 22 Jul 2025 16:04:00 +0200 From: =?utf-8?q?Cl=C3=A9ment_Le_Goffic?= Date: Tue, 22 Jul 2025 16:03:32 +0200 Subject: [PATCH v3 15/19] ARM: dts: stm32: add ddrperfm on stm32mp131 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250722-ddrperfm-upstream-v3-15-7b7a4f3dc8a0@foss.st.com> References: <20250722-ddrperfm-upstream-v3-0-7b7a4f3dc8a0@foss.st.com> In-Reply-To: <20250722-ddrperfm-upstream-v3-0-7b7a4f3dc8a0@foss.st.com> To: Will Deacon , Mark Rutland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Philipp Zabel , Jonathan Corbet , Gatien Chevallier , Michael Turquette , Stephen Boyd , Gabriel Fernandez , Krzysztof Kozlowski , Le Goffic , Julius Werner CC: , , , , , , , =?utf-8?q?Cl=C3=A9ment_Le_Goffic?= X-Mailer: b4 0.15-dev-8018a X-ClientProxiedBy: SHFCAS1NODE2.st.com (10.75.129.73) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-22_02,2025-07-21_02,2025-03-28_01 The DDRPERFM is the DDR Performance Monitor embedded in STM32MP131 SoC. Signed-off-by: Cl=C3=A9ment Le Goffic --- arch/arm/boot/dts/st/stm32mp131.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/boot/dts/st/stm32mp131.dtsi b/arch/arm/boot/dts/st/st= m32mp131.dtsi index 492bcf586361..e097723789aa 100644 --- a/arch/arm/boot/dts/st/stm32mp131.dtsi +++ b/arch/arm/boot/dts/st/stm32mp131.dtsi @@ -998,6 +998,13 @@ iwdg2: watchdog@5a002000 { status =3D "disabled"; }; =20 + ddrperfm: perf@5a007000 { + compatible =3D "st,stm32mp131-ddr-pmu"; + reg =3D <0x5a007000 0x400>; + clocks =3D <&rcc DDRPERFM>; + resets =3D <&rcc DDRPERFM_R>; + }; + rtc: rtc@5c004000 { compatible =3D "st,stm32mp1-rtc"; reg =3D <0x5c004000 0x400>; --=20 2.43.0 From nobody Mon Oct 6 10:13:27 2025 Received: from mx08-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E627B2EE5E6; Tue, 22 Jul 2025 14:07:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Signed-off-by: Cl=C3=A9ment Le Goffic --- arch/arm/boot/dts/st/stm32mp151.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/boot/dts/st/stm32mp151.dtsi b/arch/arm/boot/dts/st/st= m32mp151.dtsi index 0daa8ffe2ff5..e121de52a054 100644 --- a/arch/arm/boot/dts/st/stm32mp151.dtsi +++ b/arch/arm/boot/dts/st/stm32mp151.dtsi @@ -383,6 +383,13 @@ usbphyc_port1: usb-phy@1 { }; }; =20 + ddrperfm: perf@5a007000 { + compatible =3D "st,stm32mp151-ddr-pmu", "st,stm32mp131-ddr-pmu"; + reg =3D <0x5a007000 0x400>; + clocks =3D <&rcc DDRPERFM>; + resets =3D <&rcc DDRPERFM_R>; + }; + rtc: rtc@5c004000 { compatible =3D "st,stm32mp1-rtc"; reg =3D <0x5c004000 0x400>; --=20 2.43.0 From nobody Mon Oct 6 10:13:27 2025 Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C6C462EE29E; Tue, 22 Jul 2025 14:07:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Tue, 22 Jul 2025 16:07:07 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 26DDA40060; Tue, 22 Jul 2025 16:05:24 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 326967A3206; Tue, 22 Jul 2025 16:04:02 +0200 (CEST) Received: from localhost (10.48.86.185) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Tue, 22 Jul 2025 16:04:01 +0200 From: =?utf-8?q?Cl=C3=A9ment_Le_Goffic?= Date: Tue, 22 Jul 2025 16:03:34 +0200 Subject: [PATCH v3 17/19] arm64: dts: st: add ddrperfm on stm32mp251 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250722-ddrperfm-upstream-v3-17-7b7a4f3dc8a0@foss.st.com> References: <20250722-ddrperfm-upstream-v3-0-7b7a4f3dc8a0@foss.st.com> In-Reply-To: <20250722-ddrperfm-upstream-v3-0-7b7a4f3dc8a0@foss.st.com> To: Will Deacon , Mark Rutland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Philipp Zabel , Jonathan Corbet , Gatien Chevallier , Michael Turquette , Stephen Boyd , Gabriel Fernandez , Krzysztof Kozlowski , Le Goffic , Julius Werner CC: , , , , , , , =?utf-8?q?Cl=C3=A9ment_Le_Goffic?= X-Mailer: b4 0.15-dev-8018a X-ClientProxiedBy: SHFCAS1NODE2.st.com (10.75.129.73) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-22_02,2025-07-21_02,2025-03-28_01 The DDRPERFM is the DDR Performance Monitor embedded in STM32MP251 SoC. Keep the node disabled at SoC level as it requires the property `st,dram-type` which is provided in board dtsi file. Signed-off-by: Cl=C3=A9ment Le Goffic --- arch/arm64/boot/dts/st/stm32mp251.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/s= t/stm32mp251.dtsi index 0683c2d5cb6f..7f138324610a 100644 --- a/arch/arm64/boot/dts/st/stm32mp251.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi @@ -1577,5 +1577,12 @@ exti2: interrupt-controller@46230000 { <0>, <&intc GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>; /* EXTI_70 */ }; + + ddrperfm: perf@48041000 { + compatible =3D "st,stm32mp251-ddr-pmu"; + reg =3D <0x48041000 0x400>; + access-controllers =3D <&rcc 104>; + status =3D "disabled"; + }; }; }; --=20 2.43.0 From nobody Mon Oct 6 10:13:27 2025 Received: from mx07-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 774EB2B9A5; Tue, 22 Jul 2025 14:06:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Disable the node as DDRPERFM will produce an error message if it's clock (shared with the DDRCTRL on STM32MP25x) is secured by common bootloaders. Signed-off-by: Cl=C3=A9ment Le Goffic --- arch/arm64/boot/dts/st/stm32mp257f-dk.dts | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp257f-dk.dts b/arch/arm64/boot/dt= s/st/stm32mp257f-dk.dts index a97b41f14ecc..d236ebf2bb10 100644 --- a/arch/arm64/boot/dts/st/stm32mp257f-dk.dts +++ b/arch/arm64/boot/dts/st/stm32mp257f-dk.dts @@ -84,6 +84,11 @@ &arm_wdt { status =3D "okay"; }; =20 +&ddrperfm { + memory-channel =3D <&lpddr_channel>; + status =3D "disabled"; +}; + &scmi_regu { scmi_vddio1: regulator@0 { regulator-min-microvolt =3D <1800000>; --=20 2.43.0 From nobody Mon Oct 6 10:13:27 2025 Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 28C132EB5B2; Tue, 22 Jul 2025 14:06:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.132.182.106 ARC-Seal: i=1; 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Tue, 22 Jul 2025 16:06:42 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 0CF7640048; Tue, 22 Jul 2025 16:05:28 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id A2D70768F78; Tue, 22 Jul 2025 16:04:03 +0200 (CEST) Received: from localhost (10.48.86.185) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Tue, 22 Jul 2025 16:04:03 +0200 From: =?utf-8?q?Cl=C3=A9ment_Le_Goffic?= Date: Tue, 22 Jul 2025 16:03:36 +0200 Subject: [PATCH v3 19/19] arm64: dts: st: support ddrperfm on stm32mp257f-ev1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250722-ddrperfm-upstream-v3-19-7b7a4f3dc8a0@foss.st.com> References: <20250722-ddrperfm-upstream-v3-0-7b7a4f3dc8a0@foss.st.com> In-Reply-To: <20250722-ddrperfm-upstream-v3-0-7b7a4f3dc8a0@foss.st.com> To: Will Deacon , Mark Rutland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Philipp Zabel , Jonathan Corbet , Gatien Chevallier , Michael Turquette , Stephen Boyd , Gabriel Fernandez , Krzysztof Kozlowski , Le Goffic , Julius Werner CC: , , , , , , , =?utf-8?q?Cl=C3=A9ment_Le_Goffic?= X-Mailer: b4 0.15-dev-8018a X-ClientProxiedBy: SHFCAS1NODE2.st.com (10.75.129.73) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-22_02,2025-07-21_02,2025-03-28_01 Configure DDRPERFM node on stm32mp257f-ev1 board. Disable the node as DDRPERFM will produce an error message if it's clock (shared with the DDRCTRL on STM32MP25x) is secured by common bootloaders. Signed-off-by: Cl=C3=A9ment Le Goffic --- arch/arm64/boot/dts/st/stm32mp257f-ev1.dts | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts b/arch/arm64/boot/d= ts/st/stm32mp257f-ev1.dts index cd2fe81bf934..f81ea794771d 100644 --- a/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts +++ b/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts @@ -130,6 +130,11 @@ csi_source: endpoint { }; }; =20 +&ddrperfm { + memory-channel =3D <&ddr_channel>; + status =3D "disabled"; +}; + &dcmipp { status =3D "okay"; port { --=20 2.43.0