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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-31cc3e45e6csm7490753a91.3.2025.07.22.00.22.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Jul 2025 00:22:44 -0700 (PDT) From: Xiangxu Yin Date: Tue, 22 Jul 2025 15:22:04 +0800 Subject: [PATCH v2 03/13] dt-bindings: phy: qcom,msm8998-qmp-usb3-phy: support dual TCSR registers Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250722-add-displayport-support-for-qcs615-platform-v2-3-42b4037171f8@oss.qualcomm.com> References: <20250722-add-displayport-support-for-qcs615-platform-v2-0-42b4037171f8@oss.qualcomm.com> In-Reply-To: <20250722-add-displayport-support-for-qcs615-platform-v2-0-42b4037171f8@oss.qualcomm.com> To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Kuogee Hsieh , Vinod Koul , Kishon Vijay Abraham I Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, dmitry.baryshkov@oss.qualcomm.com, konrad.dybcio@oss.qualcomm.com, fange.zhang@oss.qualcomm.com, quic_lliu6@quicinc.com, quic_yongmou@quicinc.com, Xiangxu Yin X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1753168937; l=2537; i=xiangxu.yin@oss.qualcomm.com; s=20241125; h=from:subject:message-id; bh=71nsNROW8nOruef5bHMWdW3ozXU/NjQImv6aKmL0T24=; b=dLa0B1WM5pUjkW4SwnkHpZoEZpTLwSATWGvvZEls9+EyqvaTXc0lRt/0UyqWmrJRqq5wLe/z9 j/MpgPhJxb5CZpHDFqsNvkHX+TzWVnCqfLppugMnbDEfKk+5I/8/cZX X-Developer-Key: i=xiangxu.yin@oss.qualcomm.com; a=ed25519; pk=F1TwipJzpywfbt3n/RPi4l/A4AVF+QC89XzCHgZYaOc= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzIyMDA1OSBTYWx0ZWRfX0S4+ChcIOxPP MsMMIoqdrUoQwPyJ4Mq8J1/qqedG5fi0twtLxi2UbyI8lx1FVSaoD4jQztXfocKIioVsJq8FOdH 0b4uJzSKyNX5efj1a911HOYIW2yjeRM5xzbjzmKj0Ktn93sg4TjWdzk9fwZsW5211hk6/fdp4+R Ent+1hoD8RBILD9lAm+NWajV9Dm/bwBXqDFbVOqAKE+96avENYu6hWVLpd1ZaLRitim/oTmB7HQ Im9xanbehHCVuOqwdJgQyzXdiGqCNn583irAqFoGvyx6ZCzQ8S5V1siuMLDRItROF6yW5sHLiZq M4qwYgMlUCZLeNZrq2cg+VpUd+SPjQ0/bJWBEeNBFVpz7v+3hWf4RzDxVTDIQ9oTZL+gohQKh68 usOxpFVuBe7UZTRHTCoAhbYEpdz8zpNUOO+7oT+oqWQlqW9Z3smcHS+tfG1J7CdJ7022zuNk X-Proofpoint-ORIG-GUID: pfH0T4EOhFI69tpLcC0Kiy_hEb8MJuVR X-Proofpoint-GUID: pfH0T4EOhFI69tpLcC0Kiy_hEb8MJuVR X-Authority-Analysis: v=2.4 cv=IrMecK/g c=1 sm=1 tr=0 ts=687f3c46 cx=c_pps a=IZJwPbhc+fLeJZngyXXI0A==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=Wb1JkmetP80A:10 a=EUspDBNiAAAA:8 a=nxDEYaoXc1MktuKintAA:9 a=QEXdDO2ut3YA:10 a=uG9DUKGECoFWVXl0Dc02:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-22_01,2025-07-21_02,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 lowpriorityscore=0 malwarescore=0 adultscore=0 clxscore=1015 priorityscore=1501 spamscore=0 mlxscore=0 mlxlogscore=999 phishscore=0 impostorscore=0 bulkscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507220059 Add support for specifying two TCSR register addresses in the qcom,tcsr-reg property to enable DP-only mode switching. This change maintains backward compatibility with the original single-register format. Also update #clock-cells and #phy-cells to <1> to support clock and PHY provider interfaces, respectively. This is required for platforms that consume the PHY clock and select PHY mode dynamically. Signed-off-by: Xiangxu Yin --- .../bindings/phy/qcom,msm8998-qmp-usb3-phy.yaml | 28 +++++++++++++++++-= ---- 1 file changed, 22 insertions(+), 6 deletions(-) diff --git a/Documentation/devicetree/bindings/phy/qcom,msm8998-qmp-usb3-ph= y.yaml b/Documentation/devicetree/bindings/phy/qcom,msm8998-qmp-usb3-phy.ya= ml index 1636285fbe535c430fdf792b33a5e9c523de323b..badfc46cda6c3a128688ac63b00= d97dc2ba742d6 100644 --- a/Documentation/devicetree/bindings/phy/qcom,msm8998-qmp-usb3-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,msm8998-qmp-usb3-phy.yaml @@ -44,13 +44,21 @@ properties: vdda-pll-supply: true =20 "#clock-cells": - const: 0 + oneOf: + - description: Set to 0 for legacy platforms without clock provider + const: 0 + - description: Set to 1 to expose PHY pipe clock. + const: 1 =20 clock-output-names: maxItems: 1 =20 "#phy-cells": - const: 0 + oneOf: + - description: Set to 0 for legacy platforms + const: 0 + - description: Set to 1 to supports mode selection (e.g. USB/DP) + const: 1 =20 orientation-switch: description: @@ -59,11 +67,19 @@ properties: =20 qcom,tcsr-reg: $ref: /schemas/types.yaml#/definitions/phandle-array - items: + description: Clamp and PHY mode register present in the TCSR + oneOf: + - items: + - items: + - description: phandle to TCSR hardware block + - description: offset of the VLS CLAMP register - items: - - description: phandle to TCSR hardware block - - description: offset of the VLS CLAMP register - description: Clamp register present in the TCSR + - items: + - description: phandle to TCSR hardware block + - description: offset of the VLS CLAMP register + - items: + - description: phandle to TCSR hardware block + - description: offset of the DP PHY mode register =20 ports: $ref: /schemas/graph.yaml#/properties/ports --=20 2.34.1