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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-31cc3e45e6csm7490753a91.3.2025.07.22.00.22.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Jul 2025 00:22:37 -0700 (PDT) From: Xiangxu Yin Date: Tue, 22 Jul 2025 15:22:03 +0800 Subject: [PATCH v2 02/13] dt-bindings: phy: Add binding for QCS615 standalone QMP DP PHY Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250722-add-displayport-support-for-qcs615-platform-v2-2-42b4037171f8@oss.qualcomm.com> References: <20250722-add-displayport-support-for-qcs615-platform-v2-0-42b4037171f8@oss.qualcomm.com> In-Reply-To: <20250722-add-displayport-support-for-qcs615-platform-v2-0-42b4037171f8@oss.qualcomm.com> To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Kuogee Hsieh , Vinod Koul , Kishon Vijay Abraham I Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, dmitry.baryshkov@oss.qualcomm.com, konrad.dybcio@oss.qualcomm.com, fange.zhang@oss.qualcomm.com, quic_lliu6@quicinc.com, quic_yongmou@quicinc.com, Xiangxu Yin X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1753168937; l=3578; i=xiangxu.yin@oss.qualcomm.com; s=20241125; h=from:subject:message-id; bh=UDTnjCmveSMGSp/9NQ1xFqa1/QflcdbQxJ1GccXnTeo=; b=YoL+Xx1wzPD3/qIMkTLFdtwm8HNMkESmMYELfdTMUCrTewkhorshB/5RAVcHRq4SwdOiu3BPo lXKaRSJmwq6BcU6iUavW+f2u7KPzXVqQYTEjJo8QVt0uEvrlQAZKJks X-Developer-Key: i=xiangxu.yin@oss.qualcomm.com; a=ed25519; pk=F1TwipJzpywfbt3n/RPi4l/A4AVF+QC89XzCHgZYaOc= X-Authority-Analysis: v=2.4 cv=CZ4I5Krl c=1 sm=1 tr=0 ts=687f3c3f cx=c_pps a=UNFcQwm+pnOIJct1K4W+Mw==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=Wb1JkmetP80A:10 a=gEfo2CItAAAA:8 a=EUspDBNiAAAA:8 a=VwQbUJbxAAAA:8 a=vvfQ0qTNUOrexlX-OJMA:9 a=QEXdDO2ut3YA:10 a=uKXjsCUrEbL0IQVhDsJ9:22 a=sptkURWiP4Gy88Gu7hUp:22 X-Proofpoint-ORIG-GUID: xjtcptUzaA4dS_hdNjBqVT0wA4qobRuy X-Proofpoint-GUID: xjtcptUzaA4dS_hdNjBqVT0wA4qobRuy X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzIyMDA1OSBTYWx0ZWRfXxA06uogtp6Jh XNOFSvfzsq+dMJ/q7vgChJJXK7wuTbN9vBF8rs3f5v4rXBYS6sKjVOapim2tlv4h+s+WjD76lOS qWVwWYpXrIon8aHneT5M0rbuH3AF09ZTz0S2OSmB5mkdOk7gHd6NJUmWIscuxUYHd+VGmOf76nf hFye1zfnqRnZAZF4wnhYS1iqMApdTBCDItyuUAHQRdjG64MJXqul0ABTLnB3zfe9lO0v7tAp4vu WbjHzpvhQYKjWtrS8V0JbNGsAoccAKJ3cWQcnXNh4ae7RWGAAhob505tKJYNDx2a6MPwfKMIe83 a97q2uexyoX65rqCvcu2vNF8evBXnL0j0o9EXsf5oJleIR1xHisIb8SpFB3MuoECDTTkA+mLjWM EtsGo207BaRehcQLTaxqLFjZZAgeIQyhctosXckl90Yrv53evOsD2ifiutoRgzc7XyA07qEc X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-22_01,2025-07-21_02,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 suspectscore=0 mlxlogscore=999 impostorscore=0 clxscore=1015 mlxscore=0 lowpriorityscore=0 phishscore=0 adultscore=0 bulkscore=0 spamscore=0 malwarescore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507220059 Introduce device tree binding documentation for the Qualcomm QMP DP PHY on QCS615 SoCs. This PHY supports DisplayPort functionality and is designed to operate independently from the USB3 PHY. Unlike combo PHYs found on other platforms, the QCS615 DP PHY is standalone and does not support USB/DP multiplexing. The binding describes the required clocks, resets, TCSR configuration, and clock/PHY cells for proper integration. Signed-off-by: Xiangxu Yin --- .../bindings/phy/qcom,qcs615-qmp-dp-phy.yaml | 111 +++++++++++++++++= ++++ 1 file changed, 111 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/qcom,qcs615-qmp-dp-phy.y= aml b/Documentation/devicetree/bindings/phy/qcom,qcs615-qmp-dp-phy.yaml new file mode 100644 index 0000000000000000000000000000000000000000..17e37c1df7b61dc2f7aa35ee106= fd94ee2829c5f --- /dev/null +++ b/Documentation/devicetree/bindings/phy/qcom,qcs615-qmp-dp-phy.yaml @@ -0,0 +1,111 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/qcom,qcs615-qmp-dp-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm QMP PHY controller (DP, QCS615) + +maintainers: + - Vinod Koul + +description: + The QMP DP PHY controller supports DisplayPort physical layer functional= ity + on Qualcomm QCS615 SoCs. This PHY is independent from USB3 PHY and does = not + support combo mode. + +properties: + compatible: + enum: + - qcom,qcs615-qmp-dp-phy + + reg: + maxItems: 4 + + clocks: + maxItems: 2 + + clock-names: + items: + - const: cfg_ahb + - const: ref + + clock-output-names: + maxItems: 2 + description: + Names of the clocks provided by the PHY. + + qcom,tcsr-reg: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: phandle to TCSR hardware block + - description: offset of the DP PHY moode register + description: + DP PHY moode register present in the TCSR + + resets: + maxItems: 1 + + reset-names: + items: + - const: phy + + vdda-phy-supply: true + + vdda-pll-supply: true + + "#clock-cells": + const: 1 + description: + See include/dt-bindings/phy/phy-qcom-qmp.h + + "#phy-cells": + const: 1 + description: + See include/dt-bindings/phy/phy-qcom-qmp.h + +required: + - compatible + - reg + - clocks + - clock-names + - clock-output-names + - qcom,tcsr-reg + - resets + - reset-names + - vdda-phy-supply + - vdda-pll-supply + - "#clock-cells" + - "#phy-cells" + +additionalProperties: false + +examples: + - | + #include + #include + + phy@88e9000 { + compatible =3D "qcom,qcs615-qmp-dp-phy"; + reg =3D <0x088e9000 0x200>, + <0x088e9400 0x10c>, + <0x088e9800 0x10c>, + <0x088e9c00 0x200>; + + clocks =3D <&gcc GCC_AHB2PHY_WEST_CLK>, + <&gcc GCC_USB3_SEC_CLKREF_CLK>; + clock-names =3D "cfg_ahb", "ref"; + clock-output-names =3D "dp_phy_link_clk", "dp_phy_vco_div_clk"; + + qcom,tcsr-reg =3D <&tcsr 0xb24c>; + + resets =3D <&gcc GCC_USB3_DP_PHY_SEC_BCR>; + reset-names =3D "phy"; + + vdda-phy-supply =3D <&vreg_l11a>; + vdda-pll-supply =3D <&vreg_l5a>; + + #clock-cells =3D <1>; + #phy-cells =3D <1>; + }; --=20 2.34.1