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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-31cc3e45e6csm7490753a91.3.2025.07.22.00.22.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Jul 2025 00:22:31 -0700 (PDT) From: Xiangxu Yin Date: Tue, 22 Jul 2025 15:22:02 +0800 Subject: [PATCH v2 01/13] dt-bindings: display/msm: Document DP on QCS615 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250722-add-displayport-support-for-qcs615-platform-v2-1-42b4037171f8@oss.qualcomm.com> References: <20250722-add-displayport-support-for-qcs615-platform-v2-0-42b4037171f8@oss.qualcomm.com> In-Reply-To: <20250722-add-displayport-support-for-qcs615-platform-v2-0-42b4037171f8@oss.qualcomm.com> To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Kuogee Hsieh , Vinod Koul , Kishon Vijay Abraham I Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, dmitry.baryshkov@oss.qualcomm.com, konrad.dybcio@oss.qualcomm.com, fange.zhang@oss.qualcomm.com, quic_lliu6@quicinc.com, quic_yongmou@quicinc.com, Xiangxu Yin X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1753168937; l=986; i=xiangxu.yin@oss.qualcomm.com; s=20241125; h=from:subject:message-id; bh=flVURwsSNZtWM0+fUgJqZKMxwfIi346lSujUoU8vBq4=; b=lFF3TC9IzWFZbCphEU+PcIbJicZ2nH4+jooaIfp3H+fpT8Ugr8/Lcb6A7g1w4zevBtfnOQzlG sTyaMHC/WnDCxaIyrA03rD90NFGzdqeY660ykfSFBWrYsobnqaFRMrc X-Developer-Key: i=xiangxu.yin@oss.qualcomm.com; a=ed25519; pk=F1TwipJzpywfbt3n/RPi4l/A4AVF+QC89XzCHgZYaOc= X-Authority-Analysis: v=2.4 cv=BJ6zrEQG c=1 sm=1 tr=0 ts=687f3c39 cx=c_pps a=MTSHoo12Qbhz2p7MsH1ifg==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=Wb1JkmetP80A:10 a=EUspDBNiAAAA:8 a=CFpH1fyJroaNsTO7nwQA:9 a=QEXdDO2ut3YA:10 a=GvdueXVYPmCkWapjIL-Q:22 X-Proofpoint-GUID: PyPCpRtaDtIihImXMUgcMexdplVoIK8R X-Proofpoint-ORIG-GUID: PyPCpRtaDtIihImXMUgcMexdplVoIK8R X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzIyMDA1OSBTYWx0ZWRfX784BEhdDdTOL uv5k0fl56txR8xME1++kdozhz7r4vudIMYOnKMQoPLrld1gF0Ha2ArSHVua5l5aPiEQncdPA/dl svp2kzHvAvc8lZ2LX8QnyWGxFML7ZNPRj5+eHCH3jeMPArgHxY6gY5h1+yPjnFkonOZ9XfTwUYT TJhbm0IaRiBNVuHZoF1+vqNwQNrUoemNhlI3YDKipzrJSG/p0QAiL4JvcfZD0bZQBEmF4PQqdNs a+GDurgqPxacxwu+mYtBI0y0nnnb1YwUoOlSCER4vTWMnl7MrRxStgBb3hqucIsuHKANGHApWTJ CX4U+Msq9BN1JvYo5wK9rG/+fGnVO9eW07Fv3VBRFB0jAQYWr9ujZjaeaOFXUU0fvk2rAC1GkcJ vE6Ctni1iMLuIvv5GWxdEHt884j8U/MKkQ/bGuE6cl3kp0vvDZ3kOtKV30fSrt5rId30O5hd X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-22_01,2025-07-21_02,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 lowpriorityscore=0 clxscore=1015 spamscore=0 mlxlogscore=933 suspectscore=0 impostorscore=0 phishscore=0 adultscore=0 mlxscore=0 malwarescore=0 bulkscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507220059 The QCS615 platform is based on the SM6150 SoC. Since the DP hardware is shared with SM6150, the compatible string qcom,sm6150-dp is used to represent the DP controller on QCS615. Signed-off-by: Xiangxu Yin --- Documentation/devicetree/bindings/display/msm/dp-controller.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/msm/dp-controller.ya= ml b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml index 9923b065323bbab99de5079b674a0317f3074373..996d0132e084d401db85014a1a4= e445d00d62ed8 100644 --- a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml +++ b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml @@ -27,6 +27,7 @@ properties: - qcom,sc8280xp-dp - qcom,sc8280xp-edp - qcom,sdm845-dp + - qcom,sm6150-dp - qcom,sm8350-dp - qcom,sm8650-dp - items: --=20 2.34.1 From nobody Mon Oct 6 11:57:30 2025 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D75B328DB46 for ; Tue, 22 Jul 2025 07:22:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-31cc3e45e6csm7490753a91.3.2025.07.22.00.22.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Jul 2025 00:22:37 -0700 (PDT) From: Xiangxu Yin Date: Tue, 22 Jul 2025 15:22:03 +0800 Subject: [PATCH v2 02/13] dt-bindings: phy: Add binding for QCS615 standalone QMP DP PHY Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250722-add-displayport-support-for-qcs615-platform-v2-2-42b4037171f8@oss.qualcomm.com> References: <20250722-add-displayport-support-for-qcs615-platform-v2-0-42b4037171f8@oss.qualcomm.com> In-Reply-To: <20250722-add-displayport-support-for-qcs615-platform-v2-0-42b4037171f8@oss.qualcomm.com> To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Kuogee Hsieh , Vinod Koul , Kishon Vijay Abraham I Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, dmitry.baryshkov@oss.qualcomm.com, konrad.dybcio@oss.qualcomm.com, fange.zhang@oss.qualcomm.com, quic_lliu6@quicinc.com, quic_yongmou@quicinc.com, Xiangxu Yin X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1753168937; l=3578; i=xiangxu.yin@oss.qualcomm.com; s=20241125; h=from:subject:message-id; bh=UDTnjCmveSMGSp/9NQ1xFqa1/QflcdbQxJ1GccXnTeo=; b=YoL+Xx1wzPD3/qIMkTLFdtwm8HNMkESmMYELfdTMUCrTewkhorshB/5RAVcHRq4SwdOiu3BPo lXKaRSJmwq6BcU6iUavW+f2u7KPzXVqQYTEjJo8QVt0uEvrlQAZKJks X-Developer-Key: i=xiangxu.yin@oss.qualcomm.com; a=ed25519; pk=F1TwipJzpywfbt3n/RPi4l/A4AVF+QC89XzCHgZYaOc= X-Authority-Analysis: v=2.4 cv=CZ4I5Krl c=1 sm=1 tr=0 ts=687f3c3f cx=c_pps a=UNFcQwm+pnOIJct1K4W+Mw==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=Wb1JkmetP80A:10 a=gEfo2CItAAAA:8 a=EUspDBNiAAAA:8 a=VwQbUJbxAAAA:8 a=vvfQ0qTNUOrexlX-OJMA:9 a=QEXdDO2ut3YA:10 a=uKXjsCUrEbL0IQVhDsJ9:22 a=sptkURWiP4Gy88Gu7hUp:22 X-Proofpoint-ORIG-GUID: xjtcptUzaA4dS_hdNjBqVT0wA4qobRuy X-Proofpoint-GUID: xjtcptUzaA4dS_hdNjBqVT0wA4qobRuy X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzIyMDA1OSBTYWx0ZWRfXxA06uogtp6Jh XNOFSvfzsq+dMJ/q7vgChJJXK7wuTbN9vBF8rs3f5v4rXBYS6sKjVOapim2tlv4h+s+WjD76lOS qWVwWYpXrIon8aHneT5M0rbuH3AF09ZTz0S2OSmB5mkdOk7gHd6NJUmWIscuxUYHd+VGmOf76nf hFye1zfnqRnZAZF4wnhYS1iqMApdTBCDItyuUAHQRdjG64MJXqul0ABTLnB3zfe9lO0v7tAp4vu WbjHzpvhQYKjWtrS8V0JbNGsAoccAKJ3cWQcnXNh4ae7RWGAAhob505tKJYNDx2a6MPwfKMIe83 a97q2uexyoX65rqCvcu2vNF8evBXnL0j0o9EXsf5oJleIR1xHisIb8SpFB3MuoECDTTkA+mLjWM EtsGo207BaRehcQLTaxqLFjZZAgeIQyhctosXckl90Yrv53evOsD2ifiutoRgzc7XyA07qEc X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-22_01,2025-07-21_02,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 suspectscore=0 mlxlogscore=999 impostorscore=0 clxscore=1015 mlxscore=0 lowpriorityscore=0 phishscore=0 adultscore=0 bulkscore=0 spamscore=0 malwarescore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507220059 Introduce device tree binding documentation for the Qualcomm QMP DP PHY on QCS615 SoCs. This PHY supports DisplayPort functionality and is designed to operate independently from the USB3 PHY. Unlike combo PHYs found on other platforms, the QCS615 DP PHY is standalone and does not support USB/DP multiplexing. The binding describes the required clocks, resets, TCSR configuration, and clock/PHY cells for proper integration. Signed-off-by: Xiangxu Yin --- .../bindings/phy/qcom,qcs615-qmp-dp-phy.yaml | 111 +++++++++++++++++= ++++ 1 file changed, 111 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/qcom,qcs615-qmp-dp-phy.y= aml b/Documentation/devicetree/bindings/phy/qcom,qcs615-qmp-dp-phy.yaml new file mode 100644 index 0000000000000000000000000000000000000000..17e37c1df7b61dc2f7aa35ee106= fd94ee2829c5f --- /dev/null +++ b/Documentation/devicetree/bindings/phy/qcom,qcs615-qmp-dp-phy.yaml @@ -0,0 +1,111 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/qcom,qcs615-qmp-dp-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm QMP PHY controller (DP, QCS615) + +maintainers: + - Vinod Koul + +description: + The QMP DP PHY controller supports DisplayPort physical layer functional= ity + on Qualcomm QCS615 SoCs. This PHY is independent from USB3 PHY and does = not + support combo mode. + +properties: + compatible: + enum: + - qcom,qcs615-qmp-dp-phy + + reg: + maxItems: 4 + + clocks: + maxItems: 2 + + clock-names: + items: + - const: cfg_ahb + - const: ref + + clock-output-names: + maxItems: 2 + description: + Names of the clocks provided by the PHY. + + qcom,tcsr-reg: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: phandle to TCSR hardware block + - description: offset of the DP PHY moode register + description: + DP PHY moode register present in the TCSR + + resets: + maxItems: 1 + + reset-names: + items: + - const: phy + + vdda-phy-supply: true + + vdda-pll-supply: true + + "#clock-cells": + const: 1 + description: + See include/dt-bindings/phy/phy-qcom-qmp.h + + "#phy-cells": + const: 1 + description: + See include/dt-bindings/phy/phy-qcom-qmp.h + +required: + - compatible + - reg + - clocks + - clock-names + - clock-output-names + - qcom,tcsr-reg + - resets + - reset-names + - vdda-phy-supply + - vdda-pll-supply + - "#clock-cells" + - "#phy-cells" + +additionalProperties: false + +examples: + - | + #include + #include + + phy@88e9000 { + compatible =3D "qcom,qcs615-qmp-dp-phy"; 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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-31cc3e45e6csm7490753a91.3.2025.07.22.00.22.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Jul 2025 00:22:44 -0700 (PDT) From: Xiangxu Yin Date: Tue, 22 Jul 2025 15:22:04 +0800 Subject: [PATCH v2 03/13] dt-bindings: phy: qcom,msm8998-qmp-usb3-phy: support dual TCSR registers Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250722-add-displayport-support-for-qcs615-platform-v2-3-42b4037171f8@oss.qualcomm.com> References: <20250722-add-displayport-support-for-qcs615-platform-v2-0-42b4037171f8@oss.qualcomm.com> In-Reply-To: <20250722-add-displayport-support-for-qcs615-platform-v2-0-42b4037171f8@oss.qualcomm.com> To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Kuogee Hsieh , Vinod Koul , Kishon Vijay Abraham I Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, dmitry.baryshkov@oss.qualcomm.com, konrad.dybcio@oss.qualcomm.com, fange.zhang@oss.qualcomm.com, quic_lliu6@quicinc.com, quic_yongmou@quicinc.com, Xiangxu Yin X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1753168937; l=2537; i=xiangxu.yin@oss.qualcomm.com; s=20241125; h=from:subject:message-id; bh=71nsNROW8nOruef5bHMWdW3ozXU/NjQImv6aKmL0T24=; b=dLa0B1WM5pUjkW4SwnkHpZoEZpTLwSATWGvvZEls9+EyqvaTXc0lRt/0UyqWmrJRqq5wLe/z9 j/MpgPhJxb5CZpHDFqsNvkHX+TzWVnCqfLppugMnbDEfKk+5I/8/cZX X-Developer-Key: i=xiangxu.yin@oss.qualcomm.com; a=ed25519; pk=F1TwipJzpywfbt3n/RPi4l/A4AVF+QC89XzCHgZYaOc= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzIyMDA1OSBTYWx0ZWRfX0S4+ChcIOxPP MsMMIoqdrUoQwPyJ4Mq8J1/qqedG5fi0twtLxi2UbyI8lx1FVSaoD4jQztXfocKIioVsJq8FOdH 0b4uJzSKyNX5efj1a911HOYIW2yjeRM5xzbjzmKj0Ktn93sg4TjWdzk9fwZsW5211hk6/fdp4+R Ent+1hoD8RBILD9lAm+NWajV9Dm/bwBXqDFbVOqAKE+96avENYu6hWVLpd1ZaLRitim/oTmB7HQ Im9xanbehHCVuOqwdJgQyzXdiGqCNn583irAqFoGvyx6ZCzQ8S5V1siuMLDRItROF6yW5sHLiZq M4qwYgMlUCZLeNZrq2cg+VpUd+SPjQ0/bJWBEeNBFVpz7v+3hWf4RzDxVTDIQ9oTZL+gohQKh68 usOxpFVuBe7UZTRHTCoAhbYEpdz8zpNUOO+7oT+oqWQlqW9Z3smcHS+tfG1J7CdJ7022zuNk X-Proofpoint-ORIG-GUID: pfH0T4EOhFI69tpLcC0Kiy_hEb8MJuVR X-Proofpoint-GUID: pfH0T4EOhFI69tpLcC0Kiy_hEb8MJuVR X-Authority-Analysis: v=2.4 cv=IrMecK/g c=1 sm=1 tr=0 ts=687f3c46 cx=c_pps a=IZJwPbhc+fLeJZngyXXI0A==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=Wb1JkmetP80A:10 a=EUspDBNiAAAA:8 a=nxDEYaoXc1MktuKintAA:9 a=QEXdDO2ut3YA:10 a=uG9DUKGECoFWVXl0Dc02:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-22_01,2025-07-21_02,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 lowpriorityscore=0 malwarescore=0 adultscore=0 clxscore=1015 priorityscore=1501 spamscore=0 mlxscore=0 mlxlogscore=999 phishscore=0 impostorscore=0 bulkscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507220059 Add support for specifying two TCSR register addresses in the qcom,tcsr-reg property to enable DP-only mode switching. This change maintains backward compatibility with the original single-register format. Also update #clock-cells and #phy-cells to <1> to support clock and PHY provider interfaces, respectively. This is required for platforms that consume the PHY clock and select PHY mode dynamically. Signed-off-by: Xiangxu Yin --- .../bindings/phy/qcom,msm8998-qmp-usb3-phy.yaml | 28 +++++++++++++++++-= ---- 1 file changed, 22 insertions(+), 6 deletions(-) diff --git a/Documentation/devicetree/bindings/phy/qcom,msm8998-qmp-usb3-ph= y.yaml b/Documentation/devicetree/bindings/phy/qcom,msm8998-qmp-usb3-phy.ya= ml index 1636285fbe535c430fdf792b33a5e9c523de323b..badfc46cda6c3a128688ac63b00= d97dc2ba742d6 100644 --- a/Documentation/devicetree/bindings/phy/qcom,msm8998-qmp-usb3-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,msm8998-qmp-usb3-phy.yaml @@ -44,13 +44,21 @@ properties: vdda-pll-supply: true =20 "#clock-cells": - const: 0 + oneOf: + - description: Set to 0 for legacy platforms without clock provider + const: 0 + - description: Set to 1 to expose PHY pipe clock. + const: 1 =20 clock-output-names: maxItems: 1 =20 "#phy-cells": - const: 0 + oneOf: + - description: Set to 0 for legacy platforms + const: 0 + - description: Set to 1 to supports mode selection (e.g. USB/DP) + const: 1 =20 orientation-switch: description: @@ -59,11 +67,19 @@ properties: =20 qcom,tcsr-reg: $ref: /schemas/types.yaml#/definitions/phandle-array - items: + description: Clamp and PHY mode register present in the TCSR + oneOf: + - items: + - items: + - description: phandle to TCSR hardware block + - description: offset of the VLS CLAMP register - items: - - description: phandle to TCSR hardware block - - description: offset of the VLS CLAMP register - description: Clamp register present in the TCSR + - items: + - description: phandle to TCSR hardware block + - description: offset of the VLS CLAMP register + - items: + - description: phandle to TCSR hardware block + - description: offset of the DP PHY mode register =20 ports: $ref: /schemas/graph.yaml#/properties/ports --=20 2.34.1 From nobody Mon Oct 6 11:57:30 2025 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 19D4B2C326E for ; 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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-31cc3e45e6csm7490753a91.3.2025.07.22.00.22.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Jul 2025 00:22:51 -0700 (PDT) From: Xiangxu Yin Date: Tue, 22 Jul 2025 15:22:05 +0800 Subject: [PATCH v2 04/13] phy: qcom: qmp-usbc: Rename USB structs and reorganize layout Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250722-add-displayport-support-for-qcs615-platform-v2-4-42b4037171f8@oss.qualcomm.com> References: <20250722-add-displayport-support-for-qcs615-platform-v2-0-42b4037171f8@oss.qualcomm.com> In-Reply-To: <20250722-add-displayport-support-for-qcs615-platform-v2-0-42b4037171f8@oss.qualcomm.com> To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Kuogee Hsieh , Vinod Koul , Kishon Vijay Abraham I Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, dmitry.baryshkov@oss.qualcomm.com, konrad.dybcio@oss.qualcomm.com, fange.zhang@oss.qualcomm.com, quic_lliu6@quicinc.com, quic_yongmou@quicinc.com, Xiangxu Yin X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1753168937; l=22783; i=xiangxu.yin@oss.qualcomm.com; s=20241125; h=from:subject:message-id; bh=/OA0ztxkzyXnLTIQb/ySHhp10s9CoyKZiV0nYWPw3dg=; b=OO/Ot8YZgcdAKooSn5Aa7AducGO1EtUC563ThCERQtLyz+OgvhPlIy+rGQDLp2Wu/kEFmSCTk P9YQejg+W1SBa94bqIU4uXRczchq/hRWS3+65mORWs3JWcstapMjkIB X-Developer-Key: i=xiangxu.yin@oss.qualcomm.com; a=ed25519; pk=F1TwipJzpywfbt3n/RPi4l/A4AVF+QC89XzCHgZYaOc= X-Authority-Analysis: v=2.4 cv=EIMG00ZC c=1 sm=1 tr=0 ts=687f3c4d cx=c_pps a=vVfyC5vLCtgYJKYeQD43oA==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=Wb1JkmetP80A:10 a=EUspDBNiAAAA:8 a=eeARFrWrdhb-Nk5A1FAA:9 a=QEXdDO2ut3YA:10 a=rl5im9kqc5Lf4LNbBjHf:22 X-Proofpoint-ORIG-GUID: -VKVFkURyNiCnmP4lzkwa47S5GMzhBu- X-Proofpoint-GUID: -VKVFkURyNiCnmP4lzkwa47S5GMzhBu- X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzIyMDA1OSBTYWx0ZWRfX5cZBruu0izPu 1LwaQYqL8UcBj6/uKeovxWFYako8qMe8gHAVocPSUFd83G7LU0M6UeQM9Wn4bUMvF07CjZDN1pc Atj2kiqwmzTmHEkqfb0d14IQpemOhJWwy1E06KNb9OqDFX5SKOCCUkbWl3yrhO0u3FfzesH9vzz CKKB7FMhLn5SxBpWDoaeK0eth9H2Az9xWt3XRKClllL+FbgtlYJhlTxHzmb40e6Uy4qyMA6sX47 ooMaGoN647weu5I2xUkgSG469ZpU1dRv1eHJ5X86qPKgcPkiUwjw4Oeofa7zpvYQcqy/LA3hI7v 5FkvYk4VuppGKRbT+zrbRQfBHy0QxzPYWjdu+dqCBV4qZ/Kv7sXsrx7SEAcbZoZcSt7BxnGXFQg +Rmex9Ijz+KTvn4UFdNRs+CMq01N4JkNQGpmJnUuMK65JDKEmuJgouHT4WhozzzZdp79eQGf X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-22_01,2025-07-21_02,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 impostorscore=0 lowpriorityscore=0 bulkscore=0 adultscore=0 priorityscore=1501 mlxlogscore=999 phishscore=0 mlxscore=0 clxscore=1015 suspectscore=0 malwarescore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507220059 Refactor the USB PHY data structures to improve modularity and prepare for multi-mode PHY support. (e.g., DP). - Rename `qmp_phy_cfg` to `qmp_phy_usb_cfg` and `qmp_usbc_offsets` to `qmp_usbc_usb_offsets`. - Introduce `qmp_phy_usb_layout` to encapsulate USB-specific register mappings. - Move USB-specific members out of the shared `qmp_usbc` structure. No functional changes; this is a preparatory cleanup for DP PHY support. Signed-off-by: Xiangxu Yin --- drivers/phy/qualcomm/phy-qcom-qmp-usbc.c | 304 +++++++++++++++++----------= ---- 1 file changed, 163 insertions(+), 141 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c b/drivers/phy/qualcom= m/phy-qcom-qmp-usbc.c index 5e7fcb26744a4401c3076960df9c0dcbec7fdef7..078752dbc66f9b9844c003e7755= fff6466ea1d6c 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c @@ -29,6 +29,8 @@ #include "phy-qcom-qmp-pcs-misc-v3.h" =20 #define PHY_INIT_COMPLETE_TIMEOUT 10000 +#define SW_PORTSELECT_VAL BIT(0) +#define SW_PORTSELECT_MUX BIT(1) =20 /* set of registers with offsets different per-PHY */ enum qphy_reg_layout { @@ -284,7 +286,7 @@ static const struct qmp_phy_init_tbl qcm2290_usb3_pcs_t= bl[] =3D { QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88), }; =20 -struct qmp_usbc_offsets { +struct qmp_usbc_usb_offsets { u16 serdes; u16 pcs; u16 pcs_misc; @@ -295,9 +297,8 @@ struct qmp_usbc_offsets { u16 rx2; }; =20 -/* struct qmp_phy_cfg - per-PHY initialization config */ -struct qmp_phy_cfg { - const struct qmp_usbc_offsets *offsets; +struct qmp_phy_usb_cfg { + const struct qmp_usbc_usb_offsets *offsets; =20 /* Init sequence for PHY blocks - serdes, tx, rx, pcs */ const struct qmp_phy_init_tbl *serdes_tbl; @@ -317,11 +318,7 @@ struct qmp_phy_cfg { const unsigned int *regs; }; =20 -struct qmp_usbc { - struct device *dev; - - const struct qmp_phy_cfg *cfg; - +struct qmp_phy_usb_layout { void __iomem *serdes; void __iomem *pcs; void __iomem *pcs_misc; @@ -329,11 +326,14 @@ struct qmp_usbc { void __iomem *rx; void __iomem *tx2; void __iomem *rx2; - - struct regmap *tcsr_map; - u32 vls_clamp_reg; - + enum phy_mode mode; struct clk *pipe_clk; + struct clk_fixed_rate pipe_clk_fixed; +}; + +struct qmp_usbc { + struct device *dev; + int type; struct clk_bulk_data *clks; int num_clks; int num_resets; @@ -341,16 +341,16 @@ struct qmp_usbc { struct regulator_bulk_data *vregs; =20 struct mutex phy_mutex; - - enum phy_mode mode; - unsigned int usb_init_count; - struct phy *phy; + enum typec_orientation orientation; + unsigned int init_count; + const void *cfg; + void *layout; =20 - struct clk_fixed_rate pipe_clk_fixed; + struct regmap *tcsr_map; + u32 vls_clamp_reg; =20 struct typec_switch_dev *sw; - enum typec_orientation orientation; }; =20 static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val) @@ -392,11 +392,11 @@ static const char * const usb3phy_reset_l[] =3D { }; =20 /* list of regulators */ -static const char * const qmp_phy_vreg_l[] =3D { +static const char * const qmp_phy_usb_vreg_l[] =3D { "vdda-phy", "vdda-pll", }; =20 -static const struct qmp_usbc_offsets qmp_usbc_offsets_v3_qcm2290 =3D { +static const struct qmp_usbc_usb_offsets qmp_usbc_usb_offsets_v3_qcm2290 = =3D { .serdes =3D 0x0, .pcs =3D 0xc00, .pcs_misc =3D 0xa00, @@ -406,8 +406,8 @@ static const struct qmp_usbc_offsets qmp_usbc_offsets_v= 3_qcm2290 =3D { .rx2 =3D 0x800, }; =20 -static const struct qmp_phy_cfg msm8998_usb3phy_cfg =3D { - .offsets =3D &qmp_usbc_offsets_v3_qcm2290, +static const struct qmp_phy_usb_cfg msm8998_usb3phy_cfg =3D { + .offsets =3D &qmp_usbc_usb_offsets_v3_qcm2290, =20 .serdes_tbl =3D msm8998_usb3_serdes_tbl, .serdes_tbl_num =3D ARRAY_SIZE(msm8998_usb3_serdes_tbl), @@ -417,13 +417,13 @@ static const struct qmp_phy_cfg msm8998_usb3phy_cfg = =3D { .rx_tbl_num =3D ARRAY_SIZE(msm8998_usb3_rx_tbl), .pcs_tbl =3D msm8998_usb3_pcs_tbl, .pcs_tbl_num =3D ARRAY_SIZE(msm8998_usb3_pcs_tbl), - .vreg_list =3D qmp_phy_vreg_l, - .num_vregs =3D ARRAY_SIZE(qmp_phy_vreg_l), + .vreg_list =3D qmp_phy_usb_vreg_l, + .num_vregs =3D ARRAY_SIZE(qmp_phy_usb_vreg_l), .regs =3D qmp_v3_usb3phy_regs_layout, }; =20 -static const struct qmp_phy_cfg qcm2290_usb3phy_cfg =3D { - .offsets =3D &qmp_usbc_offsets_v3_qcm2290, +static const struct qmp_phy_usb_cfg qcm2290_usb3phy_cfg =3D { + .offsets =3D &qmp_usbc_usb_offsets_v3_qcm2290, =20 .serdes_tbl =3D qcm2290_usb3_serdes_tbl, .serdes_tbl_num =3D ARRAY_SIZE(qcm2290_usb3_serdes_tbl), @@ -433,13 +433,13 @@ static const struct qmp_phy_cfg qcm2290_usb3phy_cfg = =3D { .rx_tbl_num =3D ARRAY_SIZE(qcm2290_usb3_rx_tbl), .pcs_tbl =3D qcm2290_usb3_pcs_tbl, .pcs_tbl_num =3D ARRAY_SIZE(qcm2290_usb3_pcs_tbl), - .vreg_list =3D qmp_phy_vreg_l, - .num_vregs =3D ARRAY_SIZE(qmp_phy_vreg_l), + .vreg_list =3D qmp_phy_usb_vreg_l, + .num_vregs =3D ARRAY_SIZE(qmp_phy_usb_vreg_l), .regs =3D qmp_v3_usb3phy_regs_layout_qcm2290, }; =20 -static const struct qmp_phy_cfg sdm660_usb3phy_cfg =3D { - .offsets =3D &qmp_usbc_offsets_v3_qcm2290, +static const struct qmp_phy_usb_cfg sdm660_usb3phy_cfg =3D { + .offsets =3D &qmp_usbc_usb_offsets_v3_qcm2290, =20 .serdes_tbl =3D qcm2290_usb3_serdes_tbl, .serdes_tbl_num =3D ARRAY_SIZE(qcm2290_usb3_serdes_tbl), @@ -449,19 +449,27 @@ static const struct qmp_phy_cfg sdm660_usb3phy_cfg = =3D { .rx_tbl_num =3D ARRAY_SIZE(sdm660_usb3_rx_tbl), .pcs_tbl =3D qcm2290_usb3_pcs_tbl, .pcs_tbl_num =3D ARRAY_SIZE(qcm2290_usb3_pcs_tbl), - .vreg_list =3D qmp_phy_vreg_l, - .num_vregs =3D ARRAY_SIZE(qmp_phy_vreg_l), + .vreg_list =3D qmp_phy_usb_vreg_l, + .num_vregs =3D ARRAY_SIZE(qmp_phy_usb_vreg_l), .regs =3D qmp_v3_usb3phy_regs_layout_qcm2290, }; =20 -static int qmp_usbc_init(struct phy *phy) +#define to_usb_cfg(x) ((struct qmp_phy_usb_cfg *)((x)->cfg)) +#define to_usb_layout(x) ((struct qmp_phy_usb_layout *)((x)->layout)) + +static int qmp_usbc_generic_init(struct phy *phy) { struct qmp_usbc *qmp =3D phy_get_drvdata(phy); - const struct qmp_phy_cfg *cfg =3D qmp->cfg; - void __iomem *pcs =3D qmp->pcs; - u32 val =3D 0; + struct qmp_phy_usb_cfg *cfg =3D to_usb_cfg(qmp); + struct qmp_phy_usb_layout *layout =3D to_usb_layout(qmp); + int num_vregs; + unsigned int reg_pwr_dn; + u32 val; int ret; =20 + num_vregs =3D cfg->num_vregs; + reg_pwr_dn =3D cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]; + ret =3D regulator_bulk_enable(cfg->num_vregs, qmp->vregs); if (ret) { dev_err(qmp->dev, "failed to enable regulators, err=3D%d\n", ret); @@ -484,30 +492,28 @@ static int qmp_usbc_init(struct phy *phy) if (ret) goto err_assert_reset; =20 - qphy_setbits(pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], SW_PWRDN); - -#define SW_PORTSELECT_VAL BIT(0) -#define SW_PORTSELECT_MUX BIT(1) /* Use software based port select and switch on typec orientation */ val =3D SW_PORTSELECT_MUX; if (qmp->orientation =3D=3D TYPEC_ORIENTATION_REVERSE) val |=3D SW_PORTSELECT_VAL; - writel(val, qmp->pcs_misc); + + qphy_setbits(layout->pcs, reg_pwr_dn, SW_PWRDN); + writel(val, layout->pcs_misc); =20 return 0; =20 err_assert_reset: reset_control_bulk_assert(qmp->num_resets, qmp->resets); err_disable_regulators: - regulator_bulk_disable(cfg->num_vregs, qmp->vregs); + regulator_bulk_disable(num_vregs, qmp->vregs); =20 return ret; } =20 -static int qmp_usbc_exit(struct phy *phy) +static int qmp_usbc_generic_exit(struct phy *phy) { struct qmp_usbc *qmp =3D phy_get_drvdata(phy); - const struct qmp_phy_cfg *cfg =3D qmp->cfg; + struct qmp_phy_usb_cfg *cfg =3D to_usb_cfg(qmp); =20 reset_control_bulk_assert(qmp->num_resets, qmp->resets); =20 @@ -518,39 +524,40 @@ static int qmp_usbc_exit(struct phy *phy) return 0; } =20 -static int qmp_usbc_power_on(struct phy *phy) +static int qmp_usbc_usb_power_on(struct phy *phy) { struct qmp_usbc *qmp =3D phy_get_drvdata(phy); - const struct qmp_phy_cfg *cfg =3D qmp->cfg; + const struct qmp_phy_usb_cfg *cfg =3D to_usb_cfg(qmp); + struct qmp_phy_usb_layout *layout =3D to_usb_layout(qmp); void __iomem *status; unsigned int val; int ret; =20 - qmp_configure(qmp->dev, qmp->serdes, cfg->serdes_tbl, + qmp_configure(qmp->dev, layout->serdes, cfg->serdes_tbl, cfg->serdes_tbl_num); =20 - ret =3D clk_prepare_enable(qmp->pipe_clk); + ret =3D clk_prepare_enable(layout->pipe_clk); if (ret) { dev_err(qmp->dev, "pipe_clk enable failed err=3D%d\n", ret); return ret; } =20 /* Tx, Rx, and PCS configurations */ - qmp_configure_lane(qmp->dev, qmp->tx, cfg->tx_tbl, cfg->tx_tbl_num, 1); - qmp_configure_lane(qmp->dev, qmp->rx, cfg->rx_tbl, cfg->rx_tbl_num, 1); + qmp_configure_lane(qmp->dev, layout->tx, cfg->tx_tbl, cfg->tx_tbl_num, 1); + qmp_configure_lane(qmp->dev, layout->rx, cfg->rx_tbl, cfg->rx_tbl_num, 1); =20 - qmp_configure_lane(qmp->dev, qmp->tx2, cfg->tx_tbl, cfg->tx_tbl_num, 2); - qmp_configure_lane(qmp->dev, qmp->rx2, cfg->rx_tbl, cfg->rx_tbl_num, 2); + qmp_configure_lane(qmp->dev, layout->tx2, cfg->tx_tbl, cfg->tx_tbl_num, 2= ); + qmp_configure_lane(qmp->dev, layout->rx2, cfg->rx_tbl, cfg->rx_tbl_num, 2= ); =20 - qmp_configure(qmp->dev, qmp->pcs, cfg->pcs_tbl, cfg->pcs_tbl_num); + qmp_configure(qmp->dev, layout->pcs, cfg->pcs_tbl, cfg->pcs_tbl_num); =20 /* Pull PHY out of reset state */ - qphy_clrbits(qmp->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); + qphy_clrbits(layout->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); =20 /* start SerDes and Phy-Coding-Sublayer */ - qphy_setbits(qmp->pcs, cfg->regs[QPHY_START_CTRL], SERDES_START | PCS_STA= RT); + qphy_setbits(layout->pcs, cfg->regs[QPHY_START_CTRL], SERDES_START | PCS_= START); =20 - status =3D qmp->pcs + cfg->regs[QPHY_PCS_STATUS]; + status =3D layout->pcs + cfg->regs[QPHY_PCS_STATUS]; ret =3D readl_poll_timeout(status, val, !(val & PHYSTATUS), 200, PHY_INIT_COMPLETE_TIMEOUT); if (ret) { @@ -561,92 +568,95 @@ static int qmp_usbc_power_on(struct phy *phy) return 0; =20 err_disable_pipe_clk: - clk_disable_unprepare(qmp->pipe_clk); + clk_disable_unprepare(layout->pipe_clk); =20 return ret; } =20 -static int qmp_usbc_power_off(struct phy *phy) +static int qmp_usbc_usb_power_off(struct phy *phy) { struct qmp_usbc *qmp =3D phy_get_drvdata(phy); - const struct qmp_phy_cfg *cfg =3D qmp->cfg; + const struct qmp_phy_usb_cfg *cfg =3D to_usb_cfg(qmp); + struct qmp_phy_usb_layout *layout =3D to_usb_layout(qmp); =20 - clk_disable_unprepare(qmp->pipe_clk); + clk_disable_unprepare(layout->pipe_clk); =20 /* PHY reset */ - qphy_setbits(qmp->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); + qphy_setbits(layout->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); =20 /* stop SerDes and Phy-Coding-Sublayer */ - qphy_clrbits(qmp->pcs, cfg->regs[QPHY_START_CTRL], - SERDES_START | PCS_START); + qphy_clrbits(layout->pcs, cfg->regs[QPHY_START_CTRL], + SERDES_START | PCS_START); =20 /* Put PHY into POWER DOWN state: active low */ - qphy_clrbits(qmp->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], - SW_PWRDN); + qphy_clrbits(layout->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], + SW_PWRDN); =20 return 0; } =20 -static int qmp_usbc_enable(struct phy *phy) +static int qmp_usbc_usb_enable(struct phy *phy) { struct qmp_usbc *qmp =3D phy_get_drvdata(phy); int ret; =20 mutex_lock(&qmp->phy_mutex); =20 - ret =3D qmp_usbc_init(phy); + ret =3D qmp_usbc_generic_init(phy); if (ret) goto out_unlock; =20 - ret =3D qmp_usbc_power_on(phy); + ret =3D qmp_usbc_usb_power_on(phy); if (ret) { - qmp_usbc_exit(phy); + qmp_usbc_generic_exit(phy); goto out_unlock; } =20 - qmp->usb_init_count++; + qmp->init_count++; out_unlock: mutex_unlock(&qmp->phy_mutex); =20 return ret; } =20 -static int qmp_usbc_disable(struct phy *phy) +static int qmp_usbc_usb_disable(struct phy *phy) { struct qmp_usbc *qmp =3D phy_get_drvdata(phy); int ret; =20 - qmp->usb_init_count--; - ret =3D qmp_usbc_power_off(phy); + qmp->init_count--; + ret =3D qmp_usbc_usb_power_off(phy); if (ret) return ret; - return qmp_usbc_exit(phy); + return qmp_usbc_generic_exit(phy); } =20 -static int qmp_usbc_set_mode(struct phy *phy, enum phy_mode mode, int subm= ode) +static int qmp_usbc_usb_set_mode(struct phy *phy, enum phy_mode mode, int = submode) { struct qmp_usbc *qmp =3D phy_get_drvdata(phy); + struct qmp_phy_usb_layout *layout =3D to_usb_layout(qmp); =20 - qmp->mode =3D mode; + layout->mode =3D mode; =20 return 0; } =20 -static const struct phy_ops qmp_usbc_phy_ops =3D { - .init =3D qmp_usbc_enable, - .exit =3D qmp_usbc_disable, - .set_mode =3D qmp_usbc_set_mode, +static const struct phy_ops qmp_usbc_usb_phy_ops =3D { + .init =3D qmp_usbc_usb_enable, + .exit =3D qmp_usbc_usb_disable, + .set_mode =3D qmp_usbc_usb_set_mode, .owner =3D THIS_MODULE, }; =20 static void qmp_usbc_enable_autonomous_mode(struct qmp_usbc *qmp) { - const struct qmp_phy_cfg *cfg =3D qmp->cfg; - void __iomem *pcs =3D qmp->pcs; + const struct qmp_phy_usb_cfg *cfg =3D qmp->cfg; + struct qmp_phy_usb_layout *layout =3D to_usb_layout(qmp); + void __iomem *pcs =3D layout->pcs; u32 intr_mask; =20 - if (qmp->mode =3D=3D PHY_MODE_USB_HOST_SS || - qmp->mode =3D=3D PHY_MODE_USB_DEVICE_SS) + if (layout->mode =3D=3D PHY_MODE_USB_HOST_SS || + layout->mode =3D=3D PHY_MODE_USB_DEVICE_SS) intr_mask =3D ARCVR_DTCT_EN | ALFPS_DTCT_EN; else intr_mask =3D ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL; @@ -669,8 +679,9 @@ static void qmp_usbc_enable_autonomous_mode(struct qmp_= usbc *qmp) =20 static void qmp_usbc_disable_autonomous_mode(struct qmp_usbc *qmp) { - const struct qmp_phy_cfg *cfg =3D qmp->cfg; - void __iomem *pcs =3D qmp->pcs; + const struct qmp_phy_usb_cfg *cfg =3D to_usb_cfg(qmp); + struct qmp_phy_usb_layout *layout =3D to_usb_layout(qmp); + void __iomem *pcs =3D layout->pcs; =20 /* Disable i/o clamp_n on resume for normal mode */ if (qmp->tcsr_map && qmp->vls_clamp_reg) @@ -687,8 +698,9 @@ static void qmp_usbc_disable_autonomous_mode(struct qmp= _usbc *qmp) static int __maybe_unused qmp_usbc_runtime_suspend(struct device *dev) { struct qmp_usbc *qmp =3D dev_get_drvdata(dev); + struct qmp_phy_usb_layout *layout =3D to_usb_layout(qmp); =20 - dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qmp->mode); + dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", layout->mode); =20 if (!qmp->phy->init_count) { dev_vdbg(dev, "PHY not initialized, bailing out\n"); @@ -697,7 +709,7 @@ static int __maybe_unused qmp_usbc_runtime_suspend(stru= ct device *dev) =20 qmp_usbc_enable_autonomous_mode(qmp); =20 - clk_disable_unprepare(qmp->pipe_clk); + clk_disable_unprepare(layout->pipe_clk); clk_bulk_disable_unprepare(qmp->num_clks, qmp->clks); =20 return 0; @@ -706,9 +718,10 @@ static int __maybe_unused qmp_usbc_runtime_suspend(str= uct device *dev) static int __maybe_unused qmp_usbc_runtime_resume(struct device *dev) { struct qmp_usbc *qmp =3D dev_get_drvdata(dev); + struct qmp_phy_usb_layout *layout =3D to_usb_layout(qmp); int ret =3D 0; =20 - dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", qmp->mode); + dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", layout->mode); =20 if (!qmp->phy->init_count) { dev_vdbg(dev, "PHY not initialized, bailing out\n"); @@ -719,7 +732,7 @@ static int __maybe_unused qmp_usbc_runtime_resume(struc= t device *dev) if (ret) return ret; =20 - ret =3D clk_prepare_enable(qmp->pipe_clk); + ret =3D clk_prepare_enable(layout->pipe_clk); if (ret) { dev_err(dev, "pipe_clk enable failed, err=3D%d\n", ret); clk_bulk_disable_unprepare(qmp->num_clks, qmp->clks); @@ -738,11 +751,12 @@ static const struct dev_pm_ops qmp_usbc_pm_ops =3D { =20 static int qmp_usbc_vreg_init(struct qmp_usbc *qmp) { - const struct qmp_phy_cfg *cfg =3D qmp->cfg; + struct qmp_phy_usb_cfg *cfg =3D to_usb_cfg(qmp); struct device *dev =3D qmp->dev; - int num =3D cfg->num_vregs; int i; =20 + int num =3D cfg->num_vregs; + qmp->vregs =3D devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL); if (!qmp->vregs) return -ENOMEM; @@ -821,7 +835,9 @@ static void phy_clk_release_provider(void *res) */ static int phy_pipe_clk_register(struct qmp_usbc *qmp, struct device_node = *np) { - struct clk_fixed_rate *fixed =3D &qmp->pipe_clk_fixed; + struct qmp_phy_usb_layout *layout =3D to_usb_layout(qmp); + + struct clk_fixed_rate *fixed =3D &layout->pipe_clk_fixed; struct clk_init_data init =3D { }; int ret; =20 @@ -864,12 +880,12 @@ static int qmp_usbc_typec_switch_set(struct typec_swi= tch_dev *sw, mutex_lock(&qmp->phy_mutex); qmp->orientation =3D orientation; =20 - if (qmp->usb_init_count) { - qmp_usbc_power_off(qmp->phy); - qmp_usbc_exit(qmp->phy); + if (qmp->init_count) { + qmp_usbc_usb_power_off(qmp->phy); + qmp_usbc_generic_exit(qmp->phy); =20 - qmp_usbc_init(qmp->phy); - qmp_usbc_power_on(qmp->phy); + qmp_usbc_generic_init(qmp->phy); + qmp_usbc_usb_power_on(qmp->phy); } =20 mutex_unlock(&qmp->phy_mutex); @@ -907,15 +923,16 @@ static int qmp_usbc_typec_switch_register(struct qmp_= usbc *qmp) } #endif =20 -static int qmp_usbc_parse_dt_legacy(struct qmp_usbc *qmp, struct device_no= de *np) +static int qmp_usbc_parse_usb_dt_legacy(struct qmp_usbc *qmp, struct devic= e_node *np) { struct platform_device *pdev =3D to_platform_device(qmp->dev); struct device *dev =3D qmp->dev; + struct qmp_phy_usb_layout *layout =3D to_usb_layout(qmp); int ret; =20 - qmp->serdes =3D devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(qmp->serdes)) - return PTR_ERR(qmp->serdes); + layout->serdes =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(layout->serdes)) + return PTR_ERR(layout->serdes); =20 /* * Get memory resources for the PHY: @@ -923,35 +940,35 @@ static int qmp_usbc_parse_dt_legacy(struct qmp_usbc *= qmp, struct device_node *np * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5 * For single lane PHYs: pcs_misc (optional) -> 3. */ - qmp->tx =3D devm_of_iomap(dev, np, 0, NULL); - if (IS_ERR(qmp->tx)) - return PTR_ERR(qmp->tx); + layout->tx =3D devm_of_iomap(dev, np, 0, NULL); + if (IS_ERR(layout->tx)) + return PTR_ERR(layout->tx); =20 - qmp->rx =3D devm_of_iomap(dev, np, 1, NULL); - if (IS_ERR(qmp->rx)) - return PTR_ERR(qmp->rx); + layout->rx =3D devm_of_iomap(dev, np, 1, NULL); + if (IS_ERR(layout->rx)) + return PTR_ERR(layout->rx); =20 - qmp->pcs =3D devm_of_iomap(dev, np, 2, NULL); - if (IS_ERR(qmp->pcs)) - return PTR_ERR(qmp->pcs); + layout->pcs =3D devm_of_iomap(dev, np, 2, NULL); + if (IS_ERR(layout->pcs)) + return PTR_ERR(layout->pcs); =20 - qmp->tx2 =3D devm_of_iomap(dev, np, 3, NULL); - if (IS_ERR(qmp->tx2)) - return PTR_ERR(qmp->tx2); + layout->tx2 =3D devm_of_iomap(dev, np, 3, NULL); + if (IS_ERR(layout->tx2)) + return PTR_ERR(layout->tx2); =20 - qmp->rx2 =3D devm_of_iomap(dev, np, 4, NULL); - if (IS_ERR(qmp->rx2)) - return PTR_ERR(qmp->rx2); + layout->rx2 =3D devm_of_iomap(dev, np, 4, NULL); + if (IS_ERR(layout->rx2)) + return PTR_ERR(layout->rx2); =20 - qmp->pcs_misc =3D devm_of_iomap(dev, np, 5, NULL); - if (IS_ERR(qmp->pcs_misc)) { + layout->pcs_misc =3D devm_of_iomap(dev, np, 5, NULL); + if (IS_ERR(layout->pcs_misc)) { dev_vdbg(dev, "PHY pcs_misc-reg not used\n"); - qmp->pcs_misc =3D NULL; + layout->pcs_misc =3D NULL; } =20 - qmp->pipe_clk =3D devm_get_clk_from_child(dev, np, NULL); - if (IS_ERR(qmp->pipe_clk)) { - return dev_err_probe(dev, PTR_ERR(qmp->pipe_clk), + layout->pipe_clk =3D devm_get_clk_from_child(dev, np, NULL); + if (IS_ERR(layout->pipe_clk)) { + return dev_err_probe(dev, PTR_ERR(layout->pipe_clk), "failed to get pipe clock\n"); } =20 @@ -969,11 +986,12 @@ static int qmp_usbc_parse_dt_legacy(struct qmp_usbc *= qmp, struct device_node *np return 0; } =20 -static int qmp_usbc_parse_dt(struct qmp_usbc *qmp) +static int qmp_usbc_parse_usb_dt(struct qmp_usbc *qmp) { struct platform_device *pdev =3D to_platform_device(qmp->dev); - const struct qmp_phy_cfg *cfg =3D qmp->cfg; - const struct qmp_usbc_offsets *offs =3D cfg->offsets; + const struct qmp_phy_usb_cfg *cfg =3D to_usb_cfg(qmp); + const struct qmp_usbc_usb_offsets *offs =3D cfg->offsets; + struct qmp_phy_usb_layout *layout =3D to_usb_layout(qmp); struct device *dev =3D qmp->dev; void __iomem *base; int ret; @@ -985,28 +1003,28 @@ static int qmp_usbc_parse_dt(struct qmp_usbc *qmp) if (IS_ERR(base)) return PTR_ERR(base); =20 - qmp->serdes =3D base + offs->serdes; - qmp->pcs =3D base + offs->pcs; + layout->serdes =3D base + offs->serdes; + layout->pcs =3D base + offs->pcs; if (offs->pcs_misc) - qmp->pcs_misc =3D base + offs->pcs_misc; - qmp->tx =3D base + offs->tx; - qmp->rx =3D base + offs->rx; + layout->pcs_misc =3D base + offs->pcs_misc; + layout->tx =3D base + offs->tx; + layout->rx =3D base + offs->rx; =20 - qmp->tx2 =3D base + offs->tx2; - qmp->rx2 =3D base + offs->rx2; + layout->tx2 =3D base + offs->tx2; + layout->rx2 =3D base + offs->rx2; =20 ret =3D qmp_usbc_clk_init(qmp); if (ret) return ret; =20 - qmp->pipe_clk =3D devm_clk_get(dev, "pipe"); - if (IS_ERR(qmp->pipe_clk)) { - return dev_err_probe(dev, PTR_ERR(qmp->pipe_clk), + layout->pipe_clk =3D devm_clk_get(dev, "pipe"); + if (IS_ERR(layout->pipe_clk)) { + return dev_err_probe(dev, PTR_ERR(layout->pipe_clk), "failed to get pipe clock\n"); } =20 ret =3D qmp_usbc_reset_init(qmp, usb3phy_reset_l, - ARRAY_SIZE(usb3phy_reset_l)); + ARRAY_SIZE(usb3phy_reset_l)); if (ret) return ret; =20 @@ -1064,6 +1082,10 @@ static int qmp_usbc_probe(struct platform_device *pd= ev) if (ret) return ret; =20 + qmp->layout =3D devm_kzalloc(dev, sizeof(struct qmp_phy_usb_layout), GFP_= KERNEL); + if (!qmp->layout) + return -ENOMEM; + ret =3D qmp_usbc_typec_switch_register(qmp); if (ret) return ret; @@ -1075,10 +1097,10 @@ static int qmp_usbc_probe(struct platform_device *p= dev) /* Check for legacy binding with child node. */ np =3D of_get_child_by_name(dev->of_node, "phy"); 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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-31cc3e45e6csm7490753a91.3.2025.07.22.00.22.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Jul 2025 00:22:57 -0700 (PDT) From: Xiangxu Yin Date: Tue, 22 Jul 2025 15:22:06 +0800 Subject: [PATCH v2 05/13] phy: qcom: qmp-usbc: Introduce PHY type enum for USB/DP support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250722-add-displayport-support-for-qcs615-platform-v2-5-42b4037171f8@oss.qualcomm.com> References: <20250722-add-displayport-support-for-qcs615-platform-v2-0-42b4037171f8@oss.qualcomm.com> In-Reply-To: <20250722-add-displayport-support-for-qcs615-platform-v2-0-42b4037171f8@oss.qualcomm.com> To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Kuogee Hsieh , Vinod Koul , Kishon Vijay Abraham I Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, dmitry.baryshkov@oss.qualcomm.com, konrad.dybcio@oss.qualcomm.com, fange.zhang@oss.qualcomm.com, quic_lliu6@quicinc.com, quic_yongmou@quicinc.com, Xiangxu Yin X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1753168937; l=10901; i=xiangxu.yin@oss.qualcomm.com; s=20241125; h=from:subject:message-id; bh=A/33KDRt3oDK4NDO2X2o64L+cjx2DofT19gj6OCqf7g=; b=YDREKYRUTca7/pvK1h3Q1whlAfi6sY4u2iLzec2J+rRH4GEmAsQfi5xA6MykrceM7premjvzW 8+2lZrRHeNLCOStdaoVpXGAY81dSnFd33BOhziX5Gq3z9TGWcw3TP/u X-Developer-Key: i=xiangxu.yin@oss.qualcomm.com; a=ed25519; pk=F1TwipJzpywfbt3n/RPi4l/A4AVF+QC89XzCHgZYaOc= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzIyMDA1OSBTYWx0ZWRfX2CNdqrHWqWB9 quSX7sC8zMeHHB9k/cH0Ev+e5NanAZeZCwzO2LfhW4LNkCOi5WLhWtLCLTGCPE7OLfrNUMmav4m w0Gjc2sV6UQOQbon5eRtkmj0UN3bW7K9K0/miG3cm11JcPMdj0dt0Wbb/DYeSZpki/sdj0+aTHU 03MfGpsb6oUZpRjhBkmaDvG+uf88pFC9H9iN8A2Zo/4ghY8r6w2/ofsVIpfsySEwLODx+0DHzDU 3CVCB1RqgeqcjOIM/5U2g+U1I0g95dCtlfXz08krZj7LyR+AzSuBzt1FwZdBlS3XYeEBSw72f9r hBJh1wRsz3m+HJ4VQdisnR6pWWU0d+1Pa0b0sA23qs2uKHAaJ9EthvRi66zqQHzu4Niad0Da4Zj 7x/u3DAtCN+Tz0yuoX0mxPzpTAJztRUXMCmRe4MQg3OwI+j1L6a5nfLe6srUCinkwKrWOwMz X-Authority-Analysis: v=2.4 cv=Jb68rVKV c=1 sm=1 tr=0 ts=687f3c54 cx=c_pps a=RP+M6JBNLl+fLTcSJhASfg==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=Wb1JkmetP80A:10 a=EUspDBNiAAAA:8 a=lpKKpq6P2_pQO93rLgIA:9 a=QEXdDO2ut3YA:10 a=iS9zxrgQBfv6-_F4QbHw:22 X-Proofpoint-GUID: ah7ywia_crxNh9ibP79LCpPQKTZrcLeR X-Proofpoint-ORIG-GUID: ah7ywia_crxNh9ibP79LCpPQKTZrcLeR X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-22_01,2025-07-21_02,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 adultscore=0 priorityscore=1501 clxscore=1015 phishscore=0 lowpriorityscore=0 suspectscore=0 bulkscore=0 malwarescore=0 mlxscore=0 spamscore=0 impostorscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507220059 Add `qmp_phy_usbc_type` enum and a `type` field in `qmp_usbc` to distinguish between USB and DP PHYs. - Introduce `qmp_phy_usbc_type` enum with USB and DP types. - Update device match table to associate compatible strings with type and config. - Wrap existing USB-specific logic with type checks to prepare for future DP support. No functional changes and serves as a preparatory step for adding DP PHY support. Signed-off-by: Xiangxu Yin --- drivers/phy/qualcomm/phy-qcom-qmp-usbc.c | 195 ++++++++++++++++++++-------= ---- 1 file changed, 126 insertions(+), 69 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c b/drivers/phy/qualcom= m/phy-qcom-qmp-usbc.c index 078752dbc66f9b9844c003e7755fff6466ea1d6c..647e2f54b744bf099ea667e672c= 606dd7aef3bcf 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c @@ -286,6 +286,16 @@ static const struct qmp_phy_init_tbl qcm2290_usb3_pcs_= tbl[] =3D { QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88), }; =20 +enum qmp_phy_usbc_type { + QMP_PHY_USBC_USB, + QMP_PHY_USBC_DP, +}; + +struct qmp_phy_cfg { + int type; + const void *cfg; +}; + struct qmp_usbc_usb_offsets { u16 serdes; u16 pcs; @@ -454,23 +464,40 @@ static const struct qmp_phy_usb_cfg sdm660_usb3phy_cf= g =3D { .regs =3D qmp_v3_usb3phy_regs_layout_qcm2290, }; =20 +static const struct qmp_phy_cfg msm8998_phy_usb3_cfg =3D { + .type =3D QMP_PHY_USBC_USB, + .cfg =3D &msm8998_usb3phy_cfg, +}; + +static const struct qmp_phy_cfg qcm2290_phy_usb3_cfg =3D { + .type =3D QMP_PHY_USBC_USB, + .cfg =3D &qcm2290_usb3phy_cfg, +}; + +static const struct qmp_phy_cfg sdm660_phy_usb3_cfg =3D { + .type =3D QMP_PHY_USBC_USB, + .cfg =3D &sdm660_usb3phy_cfg, +}; + #define to_usb_cfg(x) ((struct qmp_phy_usb_cfg *)((x)->cfg)) #define to_usb_layout(x) ((struct qmp_phy_usb_layout *)((x)->layout)) =20 static int qmp_usbc_generic_init(struct phy *phy) { struct qmp_usbc *qmp =3D phy_get_drvdata(phy); - struct qmp_phy_usb_cfg *cfg =3D to_usb_cfg(qmp); - struct qmp_phy_usb_layout *layout =3D to_usb_layout(qmp); int num_vregs; - unsigned int reg_pwr_dn; u32 val; int ret; + unsigned int reg_pwr_dn; =20 - num_vregs =3D cfg->num_vregs; - reg_pwr_dn =3D cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]; + if (qmp->type =3D=3D QMP_PHY_USBC_USB) { + struct qmp_phy_usb_cfg *cfg =3D to_usb_cfg(qmp); =20 - ret =3D regulator_bulk_enable(cfg->num_vregs, qmp->vregs); + num_vregs =3D cfg->num_vregs; + reg_pwr_dn =3D cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]; + } + + ret =3D regulator_bulk_enable(num_vregs, qmp->vregs); if (ret) { dev_err(qmp->dev, "failed to enable regulators, err=3D%d\n", ret); return ret; @@ -497,8 +524,12 @@ static int qmp_usbc_generic_init(struct phy *phy) if (qmp->orientation =3D=3D TYPEC_ORIENTATION_REVERSE) val |=3D SW_PORTSELECT_VAL; =20 - qphy_setbits(layout->pcs, reg_pwr_dn, SW_PWRDN); - writel(val, layout->pcs_misc); + if (qmp->type =3D=3D QMP_PHY_USBC_USB) { + struct qmp_phy_usb_layout *layout =3D to_usb_layout(qmp); + + qphy_setbits(layout->pcs, reg_pwr_dn, SW_PWRDN); + writel(val, layout->pcs_misc); + } =20 return 0; =20 @@ -513,13 +544,18 @@ static int qmp_usbc_generic_init(struct phy *phy) static int qmp_usbc_generic_exit(struct phy *phy) { struct qmp_usbc *qmp =3D phy_get_drvdata(phy); - struct qmp_phy_usb_cfg *cfg =3D to_usb_cfg(qmp); + int num_vregs; =20 reset_control_bulk_assert(qmp->num_resets, qmp->resets); =20 clk_bulk_disable_unprepare(qmp->num_clks, qmp->clks); =20 - regulator_bulk_disable(cfg->num_vregs, qmp->vregs); + if (qmp->type =3D=3D QMP_PHY_USBC_USB) { + struct qmp_phy_usb_cfg *cfg =3D to_usb_cfg(qmp); + + num_vregs =3D cfg->num_vregs; + } + regulator_bulk_disable(num_vregs, qmp->vregs); =20 return 0; } @@ -650,7 +686,7 @@ static const struct phy_ops qmp_usbc_usb_phy_ops =3D { =20 static void qmp_usbc_enable_autonomous_mode(struct qmp_usbc *qmp) { - const struct qmp_phy_usb_cfg *cfg =3D qmp->cfg; + const struct qmp_phy_usb_cfg *cfg =3D to_usb_cfg(qmp); struct qmp_phy_usb_layout *layout =3D to_usb_layout(qmp); void __iomem *pcs =3D layout->pcs; u32 intr_mask; @@ -698,18 +734,20 @@ static void qmp_usbc_disable_autonomous_mode(struct q= mp_usbc *qmp) static int __maybe_unused qmp_usbc_runtime_suspend(struct device *dev) { struct qmp_usbc *qmp =3D dev_get_drvdata(dev); - struct qmp_phy_usb_layout *layout =3D to_usb_layout(qmp); - - dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", layout->mode); =20 if (!qmp->phy->init_count) { dev_vdbg(dev, "PHY not initialized, bailing out\n"); return 0; } =20 - qmp_usbc_enable_autonomous_mode(qmp); + if (qmp->type =3D=3D QMP_PHY_USBC_USB) { + struct qmp_phy_usb_layout *layout =3D to_usb_layout(qmp); + + dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", layout->mode); + qmp_usbc_enable_autonomous_mode(qmp); + clk_disable_unprepare(layout->pipe_clk); + } =20 - clk_disable_unprepare(layout->pipe_clk); clk_bulk_disable_unprepare(qmp->num_clks, qmp->clks); =20 return 0; @@ -718,11 +756,8 @@ static int __maybe_unused qmp_usbc_runtime_suspend(str= uct device *dev) static int __maybe_unused qmp_usbc_runtime_resume(struct device *dev) { struct qmp_usbc *qmp =3D dev_get_drvdata(dev); - struct qmp_phy_usb_layout *layout =3D to_usb_layout(qmp); int ret =3D 0; =20 - dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", layout->mode); - if (!qmp->phy->init_count) { dev_vdbg(dev, "PHY not initialized, bailing out\n"); return 0; @@ -732,14 +767,19 @@ static int __maybe_unused qmp_usbc_runtime_resume(str= uct device *dev) if (ret) return ret; =20 - ret =3D clk_prepare_enable(layout->pipe_clk); - if (ret) { - dev_err(dev, "pipe_clk enable failed, err=3D%d\n", ret); - clk_bulk_disable_unprepare(qmp->num_clks, qmp->clks); - return ret; - } + if (qmp->type =3D=3D QMP_PHY_USBC_USB) { + struct qmp_phy_usb_layout *layout =3D to_usb_layout(qmp); + + dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", layout->mode); + ret =3D clk_prepare_enable(layout->pipe_clk); + if (ret) { + dev_err(dev, "pipe_clk enable failed, err=3D%d\n", ret); + clk_bulk_disable_unprepare(qmp->num_clks, qmp->clks); + return ret; + } =20 - qmp_usbc_disable_autonomous_mode(qmp); + qmp_usbc_disable_autonomous_mode(qmp); + } =20 return 0; } @@ -751,20 +791,28 @@ static const struct dev_pm_ops qmp_usbc_pm_ops =3D { =20 static int qmp_usbc_vreg_init(struct qmp_usbc *qmp) { - struct qmp_phy_usb_cfg *cfg =3D to_usb_cfg(qmp); struct device *dev =3D qmp->dev; - int i; + int ret, i; =20 - int num =3D cfg->num_vregs; + if (qmp->type =3D=3D QMP_PHY_USBC_USB) { + struct qmp_phy_usb_cfg *cfg =3D to_usb_cfg(qmp); + int num =3D cfg->num_vregs; =20 - qmp->vregs =3D devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL); - if (!qmp->vregs) - return -ENOMEM; + qmp->vregs =3D devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL); + if (!qmp->vregs) + return -ENOMEM; =20 - for (i =3D 0; i < num; i++) - qmp->vregs[i].supply =3D cfg->vreg_list[i]; + for (i =3D 0; i < num; i++) + qmp->vregs[i].supply =3D cfg->vreg_list[i]; =20 - return devm_regulator_bulk_get(dev, num, qmp->vregs); + ret =3D devm_regulator_bulk_get(dev, num, qmp->vregs); + if (ret) { + dev_err(dev, "failed at devm_regulator_bulk_get\n"); + return ret; + } + } + + return 0; } =20 static int qmp_usbc_reset_init(struct qmp_usbc *qmp, @@ -1061,6 +1109,7 @@ static int qmp_usbc_probe(struct platform_device *pde= v) struct phy_provider *phy_provider; struct device_node *np; struct qmp_usbc *qmp; + const struct qmp_phy_cfg *data_cfg; int ret; =20 qmp =3D devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL); @@ -1072,39 +1121,45 @@ static int qmp_usbc_probe(struct platform_device *p= dev) =20 qmp->orientation =3D TYPEC_ORIENTATION_NORMAL; =20 - qmp->cfg =3D of_device_get_match_data(dev); - if (!qmp->cfg) + data_cfg =3D of_device_get_match_data(dev); + if (!data_cfg) return -EINVAL; =20 mutex_init(&qmp->phy_mutex); =20 + qmp->type =3D data_cfg->type; + qmp->cfg =3D data_cfg->cfg; + ret =3D qmp_usbc_vreg_init(qmp); if (ret) return ret; =20 - qmp->layout =3D devm_kzalloc(dev, sizeof(struct qmp_phy_usb_layout), GFP_= KERNEL); - if (!qmp->layout) - return -ENOMEM; + if (qmp->type =3D=3D QMP_PHY_USBC_USB) { + qmp->layout =3D devm_kzalloc(dev, sizeof(struct qmp_phy_usb_layout), GFP= _KERNEL); + if (!qmp->layout) + return -ENOMEM; + + ret =3D qmp_usbc_parse_vls_clamp(qmp); + if (ret) + return ret; + + /* Check for legacy binding with child node. */ + np =3D of_get_child_by_name(dev->of_node, "phy"); + if (np) { + ret =3D qmp_usbc_parse_usb_dt_legacy(qmp, np); + } else { + np =3D of_node_get(dev->of_node); + ret =3D qmp_usbc_parse_usb_dt(qmp); + } + + if (ret) + goto err_node_put; + } =20 ret =3D qmp_usbc_typec_switch_register(qmp); if (ret) return ret; =20 - ret =3D qmp_usbc_parse_vls_clamp(qmp); - if (ret) - return ret; - - /* Check for legacy binding with child node. */ - np =3D of_get_child_by_name(dev->of_node, "phy"); - if (np) { - ret =3D qmp_usbc_parse_usb_dt_legacy(qmp, np); - } else { - np =3D of_node_get(dev->of_node); - ret =3D qmp_usbc_parse_usb_dt(qmp); - } - if (ret) - goto err_node_put; - pm_runtime_set_active(dev); ret =3D devm_pm_runtime_enable(dev); if (ret) @@ -1115,15 +1170,17 @@ static int qmp_usbc_probe(struct platform_device *p= dev) */ pm_runtime_forbid(dev); =20 - ret =3D phy_pipe_clk_register(qmp, np); - if (ret) - goto err_node_put; - - qmp->phy =3D devm_phy_create(dev, np, &qmp_usbc_usb_phy_ops); - if (IS_ERR(qmp->phy)) { - ret =3D PTR_ERR(qmp->phy); - dev_err(dev, "failed to create PHY: %d\n", ret); - goto err_node_put; + if (qmp->type =3D=3D QMP_PHY_USBC_USB) { + ret =3D phy_pipe_clk_register(qmp, np); + if (ret) + goto err_node_put; + + qmp->phy =3D devm_phy_create(dev, np, &qmp_usbc_usb_phy_ops); + if (IS_ERR(qmp->phy)) { + ret =3D PTR_ERR(qmp->phy); + dev_err(dev, "failed to create PHY: %d\n", ret); + goto err_node_put; + } } =20 phy_set_drvdata(qmp->phy, qmp); @@ -1142,19 +1199,19 @@ static int qmp_usbc_probe(struct platform_device *p= dev) static const struct of_device_id qmp_usbc_of_match_table[] =3D { { .compatible =3D "qcom,msm8998-qmp-usb3-phy", - .data =3D &msm8998_usb3phy_cfg, + .data =3D &msm8998_phy_usb3_cfg, }, { .compatible =3D "qcom,qcm2290-qmp-usb3-phy", - .data =3D &qcm2290_usb3phy_cfg, + .data =3D &qcm2290_phy_usb3_cfg, }, { .compatible =3D "qcom,qcs615-qmp-usb3-phy", - .data =3D &qcm2290_usb3phy_cfg, + .data =3D &qcm2290_phy_usb3_cfg, }, { .compatible =3D "qcom,sdm660-qmp-usb3-phy", - .data =3D &sdm660_usb3phy_cfg, + .data =3D &sdm660_phy_usb3_cfg, }, { .compatible =3D "qcom,sm6115-qmp-usb3-phy", - .data =3D &qcm2290_usb3phy_cfg, + .data =3D &qcm2290_phy_usb3_cfg, }, { }, }; --=20 2.34.1 From nobody Mon Oct 6 11:57:30 2025 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D40CA2D3EF6 for ; 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These structures mirror the USB counterparts and enable clean separation of DP logic. Signed-off-by: Xiangxu Yin --- drivers/phy/qualcomm/phy-qcom-qmp-usbc.c | 70 ++++++++++++++++++++++++++++= ++++ 1 file changed, 70 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c b/drivers/phy/qualcom= m/phy-qcom-qmp-usbc.c index 647e2f54b744bf099ea667e672c606dd7aef3bcf..bc0eaa7dba9cb84b54c7c5a264a= ac613f888cb99 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c @@ -291,6 +291,12 @@ enum qmp_phy_usbc_type { QMP_PHY_USBC_DP, }; =20 +/* list of regulators */ +struct qmp_regulator_data { + const char *name; + unsigned int enable_load; +}; + struct qmp_phy_cfg { int type; const void *cfg; @@ -341,6 +347,67 @@ struct qmp_phy_usb_layout { struct clk_fixed_rate pipe_clk_fixed; }; =20 +struct qmp_usbc_dp_offsets { + u16 dp_serdes; + u16 dp_txa; + u16 dp_txb; + u16 dp_phy; +}; + +struct qmp_usbc; + +struct qmp_phy_dp_cfg { + const struct qmp_usbc_dp_offsets *offsets; + + const struct qmp_phy_init_tbl *serdes_tbl; + int serdes_tbl_num; + const struct qmp_phy_init_tbl *tx_tbl; + int tx_tbl_num; + const struct qmp_phy_init_tbl *rx_tbl; + int rx_tbl_num; + const struct qmp_phy_init_tbl *pcs_tbl; + int pcs_tbl_num; + const struct qmp_phy_init_tbl *pcs_usb_tbl; + int pcs_usb_tbl_num; + const struct qmp_phy_init_tbl *dp_serdes_tbl; + int dp_serdes_tbl_num; + const struct qmp_phy_init_tbl *dp_tx_tbl; + int dp_tx_tbl_num; + + /* Init sequence for DP PHY block link rates */ + const struct qmp_phy_init_tbl *serdes_tbl_rbr; + int serdes_tbl_rbr_num; + const struct qmp_phy_init_tbl *serdes_tbl_hbr; + int serdes_tbl_hbr_num; + const struct qmp_phy_init_tbl *serdes_tbl_hbr2; + int serdes_tbl_hbr2_num; + + /* DP PHY swing and pre_emphasis tables */ + const u8 (*swing_tbl)[4][4]; + const u8 (*pre_emphasis_tbl)[4][4]; + + /* DP PHY callbacks */ + void (*dp_aux_init)(struct qmp_usbc *qmp); + void (*configure_dp_tx)(struct qmp_usbc *qmp); + int (*configure_dp_phy)(struct qmp_usbc *qmp); + int (*calibrate_dp_phy)(struct qmp_usbc *qmp); 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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-31cc3e45e6csm7490753a91.3.2025.07.22.00.23.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Jul 2025 00:23:11 -0700 (PDT) From: Xiangxu Yin Date: Tue, 22 Jul 2025 15:22:08 +0800 Subject: [PATCH v2 07/13] phy: qcom: qmp-usbc: Add QCS615 DP PHY configuration and init data Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250722-add-displayport-support-for-qcs615-platform-v2-7-42b4037171f8@oss.qualcomm.com> References: <20250722-add-displayport-support-for-qcs615-platform-v2-0-42b4037171f8@oss.qualcomm.com> In-Reply-To: <20250722-add-displayport-support-for-qcs615-platform-v2-0-42b4037171f8@oss.qualcomm.com> To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Kuogee Hsieh , Vinod Koul , Kishon Vijay Abraham I Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, dmitry.baryshkov@oss.qualcomm.com, konrad.dybcio@oss.qualcomm.com, fange.zhang@oss.qualcomm.com, quic_lliu6@quicinc.com, quic_yongmou@quicinc.com, Xiangxu Yin X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1753168937; l=8758; i=xiangxu.yin@oss.qualcomm.com; s=20241125; h=from:subject:message-id; bh=qNbe8OPGDdUMep/3XWLUqrKYp08jEHqdWv1AWzkSpPk=; b=mAlLNDIHo3v5PwuFwQE2/GRlhiiojVXyQZfsqkeI6HBKPdhdxnMxMIzZ3+JUuNGv3PXoDhjGY VF+cFQcDTtGCEBmuYvuqsYjDSCI83TjF/Hc8HP27QQGsVMlbY4lAF+A X-Developer-Key: i=xiangxu.yin@oss.qualcomm.com; a=ed25519; pk=F1TwipJzpywfbt3n/RPi4l/A4AVF+QC89XzCHgZYaOc= X-Authority-Analysis: v=2.4 cv=EIMG00ZC c=1 sm=1 tr=0 ts=687f3c61 cx=c_pps a=0uOsjrqzRL749jD1oC5vDA==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=Wb1JkmetP80A:10 a=EUspDBNiAAAA:8 a=LsK-adbuWOzvq-IKUcoA:9 a=QEXdDO2ut3YA:10 a=mQ_c8vxmzFEMiUWkPHU9:22 X-Proofpoint-ORIG-GUID: htAzQ2UQTj3CfH7zXA9DNyp5Vv3hVyhe X-Proofpoint-GUID: htAzQ2UQTj3CfH7zXA9DNyp5Vv3hVyhe X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzIyMDA1OSBTYWx0ZWRfXwJ4CW7GPc63q oGW1XpKWyTFFehzna8LOQQs17snBv3IU82kb4UWe4uakhpi2BU4mFe5Crvbgo8uVloIprbFk14n QLGQRaaSiVqAIgF3X8lavl71TCnd4LpXNvQYqGvfDWlnavlHoMdYBKd1JFwpAi33fnzCzgtsk0d vDAF7qJKoUqLAn2t0MmjNoOxITIiSTuxwb4h/W1GCBv5kutU3ckt/eCDQ1QcreXircFu6Lmg33m 08sH81nFopHJGmy0WOeUUvwbJfeuI07mFj6fwsJWKNtsn8O1aVXySyL71G/xdiR7oJSbIAwxd3s alPmI1M+pjnJ8Sgv6/qUM+2Fsp4Zx5O/OBDo/3UIwgvwc49VWXolugi73mN3Gu+CSNG7Z0LWbQp e2qowj4joxzD/n8lsuKMy/tEGwcr/62bs2vOimmiMmP8E6Kz1GFbry1OJTxVzvQIkJW1xO1P X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-22_01,2025-07-21_02,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 impostorscore=0 lowpriorityscore=0 bulkscore=0 adultscore=0 priorityscore=1501 mlxlogscore=999 phishscore=0 mlxscore=0 clxscore=1015 suspectscore=0 malwarescore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507220059 Introduce QCS615 hardware-specific configuration for DP PHY mode, including register offsets, initialization tables, voltage swing and pre-emphasis settings, and regulator definitions. Signed-off-by: Xiangxu Yin --- drivers/phy/qualcomm/phy-qcom-qmp-usbc.c | 148 +++++++++++++++++++++++++++= ++++ 1 file changed, 148 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c b/drivers/phy/qualcom= m/phy-qcom-qmp-usbc.c index bc0eaa7dba9cb84b54c7c5a264aac613f888cb99..aefcc520ee0bb3dd116e58222e5= e035d1d750714 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c @@ -28,6 +28,9 @@ #include "phy-qcom-qmp.h" #include "phy-qcom-qmp-pcs-misc-v3.h" =20 +#include "phy-qcom-qmp-dp-phy.h" +#include "phy-qcom-qmp-dp-phy-v3.h" + #define PHY_INIT_COMPLETE_TIMEOUT 10000 #define SW_PORTSELECT_VAL BIT(0) #define SW_PORTSELECT_MUX BIT(1) @@ -286,6 +289,86 @@ static const struct qmp_phy_init_tbl qcm2290_usb3_pcs_= tbl[] =3D { QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88), }; =20 +static const struct qmp_phy_init_tbl qcs615_qmp_dp_serdes_tbl[] =3D { + QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01), + QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x37), + QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06), + QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x3f), + QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x0e), + QMP_PHY_INIT_CFG(QSERDES_COM_BG_CTRL, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x06), + QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30), + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), + QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b), + QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x40), + QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x08), + QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x05), + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x02), +}; + +static const struct qmp_phy_init_tbl qcs615_qmp_dp_serdes_tbl_rbr[] =3D { + QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x2c), + QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x69), + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x80), + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x07), + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xbf), + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x21), + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6), +}; + +static const struct qmp_phy_init_tbl qcs615_qmp_dp_serdes_tbl_hbr[] =3D { + QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x24), + QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x69), + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x80), + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x07), + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x3f), + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x38), + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc4), +}; + +static const struct qmp_phy_init_tbl qcs615_qmp_dp_serdes_tbl_hbr2[] =3D { + QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x20), + QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x8c), + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x7f), + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x70), + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc4), +}; + +static const struct qmp_phy_init_tbl qcs615_qmp_dp_tx_tbl[] =3D { + QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRANSCEIVER_BIAS_EN, 0x1a), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_VMODE_CTRL1, 0x40), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_PRE_STALL_LDO_BOOST_EN, 0x30), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_INTERFACE_SELECT, 0x3d), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_CLKBUF_ENABLE, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RESET_TSYNC_EN, 0x03), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRAN_DRVR_EMP_EN, 0x03), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_INTERFACE_MODE, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_EMP_POST1_LVL, 0x2b), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_DRV_LVL, 0x2f), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_BAND, 0x4), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x12), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x12), +}; + enum qmp_phy_usbc_type { QMP_PHY_USBC_USB, QMP_PHY_USBC_DP, @@ -469,11 +552,20 @@ static const char * const usb3phy_reset_l[] =3D { "phy_phy", "phy", }; =20 +static const char * const dpphy_reset_l[] =3D { + "phy", +}; + /* list of regulators */ static const char * const qmp_phy_usb_vreg_l[] =3D { "vdda-phy", "vdda-pll", }; =20 +static struct qmp_regulator_data qmp_phy_dp_vreg_l[] =3D { + { .name =3D "vdda-phy", .enable_load =3D 21800 }, + { .name =3D "vdda-pll", .enable_load =3D 36000 }, +}; + static const struct qmp_usbc_usb_offsets qmp_usbc_usb_offsets_v3_qcm2290 = =3D { .serdes =3D 0x0, .pcs =3D 0xc00, @@ -484,6 +576,27 @@ static const struct qmp_usbc_usb_offsets qmp_usbc_usb_= offsets_v3_qcm2290 =3D { .rx2 =3D 0x800, }; =20 +static const struct qmp_usbc_dp_offsets qmp_usbc_dp_offsets_qcs615 =3D { + .dp_serdes =3D 0x0c00, + .dp_txa =3D 0x0400, + .dp_txb =3D 0x0800, + .dp_phy =3D 0x0000, +}; + +static const u8 qmp_dp_pre_emphasis_hbr2_rbr[4][4] =3D { + {0x00, 0x0b, 0x12, 0xff}, + {0x00, 0x0a, 0x12, 0xff}, + {0x00, 0x0c, 0xff, 0xff}, + {0xff, 0xff, 0xff, 0xff} +}; + +static const u8 qmp_dp_voltage_swing_hbr2_rbr[4][4] =3D { + {0x07, 0x0f, 0x14, 0xff}, + {0x11, 0x1d, 0x1f, 0xff}, + {0x18, 0x1f, 0xff, 0xff}, + {0xff, 0xff, 0xff, 0xff} +}; + static const struct qmp_phy_usb_cfg msm8998_usb3phy_cfg =3D { .offsets =3D &qmp_usbc_usb_offsets_v3_qcm2290, =20 @@ -532,6 +645,28 @@ static const struct qmp_phy_usb_cfg sdm660_usb3phy_cfg= =3D { .regs =3D qmp_v3_usb3phy_regs_layout_qcm2290, }; =20 +static const struct qmp_phy_dp_cfg qcs615_dpphy_cfg =3D { + .offsets =3D &qmp_usbc_dp_offsets_qcs615, + + .dp_serdes_tbl =3D qcs615_qmp_dp_serdes_tbl, + .dp_serdes_tbl_num =3D ARRAY_SIZE(qcs615_qmp_dp_serdes_tbl), + .dp_tx_tbl =3D qcs615_qmp_dp_tx_tbl, + .dp_tx_tbl_num =3D ARRAY_SIZE(qcs615_qmp_dp_tx_tbl), + + .serdes_tbl_rbr =3D qcs615_qmp_dp_serdes_tbl_rbr, + .serdes_tbl_rbr_num =3D ARRAY_SIZE(qcs615_qmp_dp_serdes_tbl_rbr), + .serdes_tbl_hbr =3D qcs615_qmp_dp_serdes_tbl_hbr, + .serdes_tbl_hbr_num =3D ARRAY_SIZE(qcs615_qmp_dp_serdes_tbl_hbr), + .serdes_tbl_hbr2 =3D qcs615_qmp_dp_serdes_tbl_hbr2, + .serdes_tbl_hbr2_num =3D ARRAY_SIZE(qcs615_qmp_dp_serdes_tbl_hbr2), + + .swing_tbl =3D &qmp_dp_voltage_swing_hbr2_rbr, + .pre_emphasis_tbl =3D &qmp_dp_pre_emphasis_hbr2_rbr, + + .vreg_list =3D qmp_phy_dp_vreg_l, + .num_vregs =3D ARRAY_SIZE(qmp_phy_dp_vreg_l), +}; + static const struct qmp_phy_cfg msm8998_phy_usb3_cfg =3D { .type =3D QMP_PHY_USBC_USB, .cfg =3D &msm8998_usb3phy_cfg, @@ -565,6 +700,10 @@ static int qmp_usbc_generic_init(struct phy *phy) =20 num_vregs =3D cfg->num_vregs; reg_pwr_dn =3D cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]; + } else { + struct qmp_phy_dp_cfg *cfg =3D to_dp_cfg(qmp); + + num_vregs =3D cfg->num_vregs; } =20 ret =3D regulator_bulk_enable(num_vregs, qmp->vregs); @@ -599,6 +738,9 @@ static int qmp_usbc_generic_init(struct phy *phy) =20 qphy_setbits(layout->pcs, reg_pwr_dn, SW_PWRDN); writel(val, layout->pcs_misc); + } else { + if (qmp->tcsr_map && qmp->dp_phy_mode_reg) + regmap_write(qmp->tcsr_map, qmp->dp_phy_mode_reg, 1); } =20 return 0; @@ -624,6 +766,12 @@ static int qmp_usbc_generic_exit(struct phy *phy) struct qmp_phy_usb_cfg *cfg =3D to_usb_cfg(qmp); =20 num_vregs =3D cfg->num_vregs; + } else { + struct qmp_phy_dp_cfg *cfg =3D to_dp_cfg(qmp); + + num_vregs =3D cfg->num_vregs; + if (qmp->tcsr_map && qmp->dp_phy_mode_reg) + regmap_write(qmp->tcsr_map, qmp->dp_phy_mode_reg, 0); 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These functions follow the QMP combo PHY flow and are integrated into the `qmp_phy_dp_cfg` structure to support full DP PHY mode enablement. Signed-off-by: Xiangxu Yin --- drivers/phy/qualcomm/phy-qcom-qmp-dp-phy.h | 1 + drivers/phy/qualcomm/phy-qcom-qmp-usbc.c | 256 +++++++++++++++++++++++++= ++++ 2 files changed, 257 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-dp-phy.h b/drivers/phy/qualc= omm/phy-qcom-qmp-dp-phy.h index 0ebd405bcaf0cac8215550bfc9b226f30cc43a59..59885616405f878885d0837838a= 0bac1899fb69f 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-dp-phy.h +++ b/drivers/phy/qualcomm/phy-qcom-qmp-dp-phy.h @@ -25,6 +25,7 @@ #define QSERDES_DP_PHY_AUX_CFG7 0x03c #define QSERDES_DP_PHY_AUX_CFG8 0x040 #define QSERDES_DP_PHY_AUX_CFG9 0x044 +#define QSERDES_DP_PHY_VCO_DIV 0x068 =20 /* QSERDES COM_BIAS_EN_CLKBUFLR_EN bits */ # define QSERDES_V3_COM_BIAS_EN 0x0001 diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c b/drivers/phy/qualcom= m/phy-qcom-qmp-usbc.c index aefcc520ee0bb3dd116e58222e5e035d1d750714..13228a21644271567d4281169ff= 1c1f316465d81 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c @@ -645,6 +645,11 @@ static const struct qmp_phy_usb_cfg sdm660_usb3phy_cfg= =3D { .regs =3D qmp_v3_usb3phy_regs_layout_qcm2290, }; =20 +static void qcs615_qmp_dp_aux_init(struct qmp_usbc *qmp); +static void qcs615_qmp_configure_dp_tx(struct qmp_usbc *qmp); +static int qcs615_qmp_configure_dp_phy(struct qmp_usbc *qmp); +static int qcs615_qmp_calibrate_dp_phy(struct qmp_usbc *qmp); + static const struct qmp_phy_dp_cfg qcs615_dpphy_cfg =3D { .offsets =3D &qmp_usbc_dp_offsets_qcs615, =20 @@ -663,6 +668,11 @@ static const struct qmp_phy_dp_cfg qcs615_dpphy_cfg = =3D { .swing_tbl =3D &qmp_dp_voltage_swing_hbr2_rbr, .pre_emphasis_tbl =3D &qmp_dp_pre_emphasis_hbr2_rbr, =20 + .dp_aux_init =3D qcs615_qmp_dp_aux_init, + .configure_dp_tx =3D qcs615_qmp_configure_dp_tx, + .configure_dp_phy =3D qcs615_qmp_configure_dp_phy, + .calibrate_dp_phy =3D qcs615_qmp_calibrate_dp_phy, + .vreg_list =3D qmp_phy_dp_vreg_l, .num_vregs =3D ARRAY_SIZE(qmp_phy_dp_vreg_l), }; @@ -778,6 +788,252 @@ static int qmp_usbc_generic_exit(struct phy *phy) return 0; } =20 +static void qcs615_qmp_dp_aux_init(struct qmp_usbc *qmp) +{ + struct qmp_phy_dp_layout *layout =3D to_dp_layout(qmp); + + writel(DP_PHY_PD_CTL_AUX_PWRDN | + DP_PHY_PD_CTL_LANE_0_1_PWRDN | DP_PHY_PD_CTL_LANE_2_3_PWRDN | + DP_PHY_PD_CTL_PLL_PWRDN, + layout->dp_phy + QSERDES_DP_PHY_PD_CTL); + + writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | + DP_PHY_PD_CTL_LANE_0_1_PWRDN | DP_PHY_PD_CTL_LANE_2_3_PWRDN | + DP_PHY_PD_CTL_PLL_PWRDN, + layout->dp_phy + QSERDES_DP_PHY_PD_CTL); + + writel(0x00, layout->dp_phy + QSERDES_DP_PHY_AUX_CFG0); + writel(0x13, layout->dp_phy + QSERDES_DP_PHY_AUX_CFG1); + writel(0x00, layout->dp_phy + QSERDES_DP_PHY_AUX_CFG2); + writel(0x00, layout->dp_phy + QSERDES_DP_PHY_AUX_CFG3); + writel(0x0a, layout->dp_phy + QSERDES_DP_PHY_AUX_CFG4); + writel(0x26, layout->dp_phy + QSERDES_DP_PHY_AUX_CFG5); + writel(0x0a, layout->dp_phy + QSERDES_DP_PHY_AUX_CFG6); + writel(0x03, layout->dp_phy + QSERDES_DP_PHY_AUX_CFG7); + writel(0xbb, layout->dp_phy + QSERDES_DP_PHY_AUX_CFG8); + writel(0x03, layout->dp_phy + QSERDES_DP_PHY_AUX_CFG9); + layout->dp_aux_cfg =3D 0; + + writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK | + PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK | + PHY_AUX_REQ_ERR_MASK, + layout->dp_phy + QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK); +} + +static int qcs615_qmp_configure_dp_swing(struct qmp_usbc *qmp) +{ + struct qmp_phy_dp_layout *layout =3D to_dp_layout(qmp); + struct qmp_phy_dp_cfg *cfg =3D to_dp_cfg(qmp); + const struct phy_configure_opts_dp *dp_opts =3D &layout->dp_opts; + void __iomem *tx =3D layout->dp_tx; + void __iomem *tx2 =3D layout->dp_tx2; + unsigned int v_level =3D 0, p_level =3D 0; + u8 voltage_swing_cfg, pre_emphasis_cfg; + int i; + + if (dp_opts->lanes > 4) { + dev_err(qmp->dev, "Invalid lane_num(%d)\n", dp_opts->lanes); + return -EINVAL; + } + + for (i =3D 0; i < dp_opts->lanes; i++) { + v_level =3D max(v_level, dp_opts->voltage[i]); + p_level =3D max(p_level, dp_opts->pre[i]); + } + + if (v_level > 4 || p_level > 4) { + dev_err(qmp->dev, "Invalid v(%d) | p(%d) level)\n", + v_level, p_level); + return -EINVAL; + } + + voltage_swing_cfg =3D (*cfg->swing_tbl)[v_level][p_level]; + pre_emphasis_cfg =3D (*cfg->pre_emphasis_tbl)[v_level][p_level]; + + voltage_swing_cfg |=3D DP_PHY_TXn_TX_DRV_LVL_MUX_EN; + pre_emphasis_cfg |=3D DP_PHY_TXn_TX_EMP_POST1_LVL_MUX_EN; + + if (voltage_swing_cfg =3D=3D 0xff && pre_emphasis_cfg =3D=3D 0xff) + return -EINVAL; + + writel(voltage_swing_cfg, tx + QSERDES_V3_TX_TX_DRV_LVL); + writel(pre_emphasis_cfg, tx + QSERDES_V3_TX_TX_EMP_POST1_LVL); + writel(voltage_swing_cfg, tx2 + QSERDES_V3_TX_TX_DRV_LVL); + writel(pre_emphasis_cfg, tx2 + QSERDES_V3_TX_TX_EMP_POST1_LVL); + + return 0; +} + +static void qmp_usbc_configure_dp_mode(struct qmp_usbc *qmp) +{ + struct qmp_phy_dp_layout *layout =3D to_dp_layout(qmp); + bool reverse =3D (qmp->orientation =3D=3D TYPEC_ORIENTATION_REVERSE); + u32 val; + + val =3D DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | + DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_LANE_0_1_PWRDN | DP_PHY_PD_= CTL_LANE_2_3_PWRDN; + + writel(val, layout->dp_phy + QSERDES_DP_PHY_PD_CTL); + + if (reverse) + writel(0xc9, layout->dp_phy + QSERDES_DP_PHY_MODE); + else + writel(0xd9, layout->dp_phy + QSERDES_DP_PHY_MODE); +} + +static int qmp_usbc_configure_dp_clocks(struct qmp_usbc *qmp) +{ + struct qmp_phy_dp_layout *layout =3D to_dp_layout(qmp); + const struct phy_configure_opts_dp *dp_opts =3D &layout->dp_opts; + u32 phy_vco_div; + unsigned long pixel_freq; + + switch (dp_opts->link_rate) { + case 1620: + phy_vco_div =3D 0x1; + pixel_freq =3D 1620000000UL / 2; + break; + case 2700: + phy_vco_div =3D 0x1; + pixel_freq =3D 2700000000UL / 2; + break; + case 5400: + phy_vco_div =3D 0x2; + pixel_freq =3D 5400000000UL / 4; + break; + default: + dev_err(qmp->dev, "link rate:%d not supported\n", dp_opts->link_rate); + return -EINVAL; + } + writel(phy_vco_div, layout->dp_phy + QSERDES_DP_PHY_VCO_DIV); + + clk_set_rate(layout->dp_link_hw.clk, dp_opts->link_rate * 100000); + clk_set_rate(layout->dp_pixel_hw.clk, pixel_freq); + + return 0; +} + +static void qcs615_qmp_configure_dp_tx(struct qmp_usbc *qmp) +{ + struct qmp_phy_dp_layout *layout =3D to_dp_layout(qmp); + void __iomem *tx =3D layout->dp_tx; + void __iomem *tx2 =3D layout->dp_tx2; + + /* program default setting first */ + writel(0x2a, tx + QSERDES_V3_TX_TX_DRV_LVL); + writel(0x20, tx + QSERDES_V3_TX_TX_EMP_POST1_LVL); + writel(0x2a, tx2 + QSERDES_V3_TX_TX_DRV_LVL); + writel(0x20, tx2 + QSERDES_V3_TX_TX_EMP_POST1_LVL); + + qcs615_qmp_configure_dp_swing(qmp); +} + +static int qcs615_qmp_configure_dp_phy(struct qmp_usbc *qmp) +{ + struct qmp_phy_dp_layout *layout =3D to_dp_layout(qmp); + u32 status; + int ret; + + qmp_usbc_configure_dp_mode(qmp); + + writel(0x05, layout->dp_phy + QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL); + writel(0x05, layout->dp_phy + QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL); + + ret =3D qmp_usbc_configure_dp_clocks(qmp); + if (ret) + return ret; + + writel(0x01, layout->dp_phy + QSERDES_DP_PHY_CFG); + writel(0x05, layout->dp_phy + QSERDES_DP_PHY_CFG); + writel(0x01, layout->dp_phy + QSERDES_DP_PHY_CFG); + writel(0x09, layout->dp_phy + QSERDES_DP_PHY_CFG); + + writel(0x20, layout->dp_serdes + QSERDES_COM_RESETSM_CNTRL); + + if (readl_poll_timeout(layout->dp_serdes + QSERDES_COM_C_READY_STATUS, + status, + ((status & BIT(0)) > 0), + 500, + 10000)) { + dev_err(qmp->dev, "C_READY not ready\n"); + return -ETIMEDOUT; + } + + if (readl_poll_timeout(layout->dp_serdes + QSERDES_COM_CMN_STATUS, + status, + ((status & BIT(0)) > 0), + 500, + 10000)){ + dev_err(qmp->dev, "FREQ_DONE not ready\n"); + return -ETIMEDOUT; + } + + if (readl_poll_timeout(layout->dp_serdes + QSERDES_COM_CMN_STATUS, + status, + ((status & BIT(1)) > 0), + 500, + 10000)){ + dev_err(qmp->dev, "PLL_LOCKED not ready\n"); + return -ETIMEDOUT; + } + + writel(0x19, layout->dp_phy + QSERDES_DP_PHY_CFG); + + if (readl_poll_timeout(layout->dp_phy + QSERDES_V3_DP_PHY_STATUS, + status, + ((status & BIT(0)) > 0), + 500, + 10000)){ + dev_err(qmp->dev, "TSYNC_DONE not ready\n"); + return -ETIMEDOUT; + } + + if (readl_poll_timeout(layout->dp_phy + QSERDES_V3_DP_PHY_STATUS, + status, + ((status & BIT(1)) > 0), + 500, + 10000)){ + dev_err(qmp->dev, "PHY_READY not ready\n"); + return -ETIMEDOUT; + } + + writel(0x3f, layout->dp_tx + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN); + writel(0x10, layout->dp_tx + QSERDES_V3_TX_HIGHZ_DRVR_EN); + writel(0x0a, layout->dp_tx + QSERDES_V3_TX_TX_POL_INV); + writel(0x3f, layout->dp_tx2 + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN); + writel(0x10, layout->dp_tx2 + QSERDES_V3_TX_HIGHZ_DRVR_EN); + writel(0x0a, layout->dp_tx2 + QSERDES_V3_TX_TX_POL_INV); + + writel(0x18, layout->dp_phy + QSERDES_DP_PHY_CFG); + writel(0x19, layout->dp_phy + QSERDES_DP_PHY_CFG); + + if (readl_poll_timeout(layout->dp_phy + QSERDES_V3_DP_PHY_STATUS, + status, + ((status & BIT(1)) > 0), + 500, + 10000)){ + dev_err(qmp->dev, "PHY_READY not ready\n"); + return -ETIMEDOUT; + } + + return 0; +} + +static int qcs615_qmp_calibrate_dp_phy(struct qmp_usbc *qmp) +{ + static const u8 cfg1_settings[] =3D {0x13, 0x23, 0x1d}; + struct qmp_phy_dp_layout *layout =3D to_dp_layout(qmp); + u8 val; + + layout->dp_aux_cfg++; + layout->dp_aux_cfg %=3D ARRAY_SIZE(cfg1_settings); + val =3D cfg1_settings[layout->dp_aux_cfg]; + + writel(val, layout->dp_phy + QSERDES_DP_PHY_AUX_CFG1); + + return 0; +} + static int qmp_usbc_usb_power_on(struct phy *phy) { struct qmp_usbc *qmp =3D phy_get_drvdata(phy); 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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-31cc3e45e6csm7490753a91.3.2025.07.22.00.23.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Jul 2025 00:23:24 -0700 (PDT) From: Xiangxu Yin Date: Tue, 22 Jul 2025 15:22:10 +0800 Subject: [PATCH v2 09/13] phy: qcom: qmp-usbc: Wire up DP PHY ops and flow for QCS615 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250722-add-displayport-support-for-qcs615-platform-v2-9-42b4037171f8@oss.qualcomm.com> References: <20250722-add-displayport-support-for-qcs615-platform-v2-0-42b4037171f8@oss.qualcomm.com> In-Reply-To: <20250722-add-displayport-support-for-qcs615-platform-v2-0-42b4037171f8@oss.qualcomm.com> To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Kuogee Hsieh , Vinod Koul , Kishon Vijay Abraham I Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, dmitry.baryshkov@oss.qualcomm.com, konrad.dybcio@oss.qualcomm.com, fange.zhang@oss.qualcomm.com, quic_lliu6@quicinc.com, quic_yongmou@quicinc.com, Xiangxu Yin X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1753168938; l=16498; i=xiangxu.yin@oss.qualcomm.com; s=20241125; h=from:subject:message-id; bh=lPQiwwQXsnw1J7JUgfbArsi1t8dQOJ18Rw4y+r8Vi3U=; b=cnSZMRx3fl39Sxqqg/gVwaRo9hi+a8KSipuUd94bsxZOJtMvGXvhNbZ+PO0oDkbQTqqDwXwtT CiHkglxHprVAObHZyonenccHKREiKaC3NMx3bVBEPTyyJl71WLj6Sbd X-Developer-Key: i=xiangxu.yin@oss.qualcomm.com; a=ed25519; pk=F1TwipJzpywfbt3n/RPi4l/A4AVF+QC89XzCHgZYaOc= X-Authority-Analysis: v=2.4 cv=CZ4I5Krl c=1 sm=1 tr=0 ts=687f3c6f cx=c_pps a=0uOsjrqzRL749jD1oC5vDA==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=Wb1JkmetP80A:10 a=EUspDBNiAAAA:8 a=FmUrSGrLgLJVcwyJgzEA:9 a=QEXdDO2ut3YA:10 a=mQ_c8vxmzFEMiUWkPHU9:22 X-Proofpoint-ORIG-GUID: XYvtwnDa_iULR16uLwLs6hohmDJJ2xZE X-Proofpoint-GUID: XYvtwnDa_iULR16uLwLs6hohmDJJ2xZE X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzIyMDA1OSBTYWx0ZWRfX/m9JC0+ax55t f8uZ3+IrCX4hKoA9jY3+K3r1396w9WDToFnkTZuzDNJC+LNHdJs01AviTfjO1q6u01iTspGegcr 9ceGScteHOhyu1PH0RxaRB3QzDuXRIabSmz83eDmHo2Np+87XN5Pcurxgc0BTSyoDizShm1NxgK rBd4bBWFpNSvd8p3WE4WLlq8lKTJwtoeJqX6aDpzyI+Vr8XnYs+WDwpC3OnVGNgAROAb/6/IwPj PRFsHyl9oSaRDUXF+fZUMqs6vMMBqr3/bgUGhbuiEGWd49nm/vcsyXOTpgMaYsSVcbEmbsdClyc DeI91EAr7DjHQI1Yg5KsVkqTregQh/C5XQhWRcFDOLPylQkJCHSyvGDwbB0q1JRlCnFDRFBmCVO jx2i7CsIsQKW5vE6qHgXWV3YRbCOwLDT2YSN8Js0N53QSUEGbGX/+zkgsG1Q0Igz/Ogegd0L X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-22_01,2025-07-21_02,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 suspectscore=0 mlxlogscore=999 impostorscore=0 clxscore=1015 mlxscore=0 lowpriorityscore=0 phishscore=0 adultscore=0 bulkscore=0 spamscore=0 malwarescore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507220059 Connect all DP PHY operation callbacks for QCS615, including init, power_on/off, configure, and calibrate. This patch also adds support for DP-specific clock registration, TCSR parsing, and AUX bridge integration. With this change, the DP PHY functional flow is fully implemented and aligned with the QMP combo PHY design. Signed-off-by: Xiangxu Yin --- drivers/phy/qualcomm/phy-qcom-qmp-usbc.c | 486 +++++++++++++++++++++++++++= +++- 1 file changed, 484 insertions(+), 2 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c b/drivers/phy/qualcom= m/phy-qcom-qmp-usbc.c index 13228a21644271567d4281169ff1c1f316465d81..6291298904de9717283e59f1ca2= a845b46146d52 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c @@ -22,6 +22,8 @@ #include #include #include +#include +#include =20 #include "phy-qcom-qmp-common.h" =20 @@ -1151,6 +1153,163 @@ static int qmp_usbc_usb_set_mode(struct phy *phy, e= num phy_mode mode, int submod return 0; } =20 +static int qmp_usbc_dp_enable(struct phy *phy) +{ + struct qmp_usbc *qmp =3D phy_get_drvdata(phy); + const struct qmp_phy_dp_cfg *cfg =3D to_dp_cfg(qmp); + int ret; + + if (qmp->init_count) { + dev_err(qmp->dev, "type(%d) inited(%d)\n", qmp->type, qmp->init_count); + return 0; + } + + mutex_lock(&qmp->phy_mutex); + + ret =3D qmp_usbc_generic_init(phy); + if (ret) { + dev_err(qmp->dev, "type(%d) com_init fail\n", qmp->type); + goto dp_init_unlock; + } + + cfg->dp_aux_init(qmp); + + qmp->init_count++; + +dp_init_unlock: + mutex_unlock(&qmp->phy_mutex); + return ret; +} + +static int qmp_usbc_dp_disable(struct phy *phy) +{ + struct qmp_usbc *qmp =3D phy_get_drvdata(phy); + + mutex_lock(&qmp->phy_mutex); + + qmp_usbc_generic_exit(phy); + + qmp->init_count--; + + mutex_unlock(&qmp->phy_mutex); + + return 0; +} + +static int qmp_usbc_dp_configure(struct phy *phy, union phy_configure_opts= *opts) +{ + const struct phy_configure_opts_dp *dp_opts =3D &opts->dp; + struct qmp_usbc *qmp =3D phy_get_drvdata(phy); + struct qmp_phy_dp_cfg *cfg =3D to_dp_cfg(qmp); + struct qmp_phy_dp_layout *layout =3D to_dp_layout(qmp); + + mutex_lock(&qmp->phy_mutex); + + memcpy(&layout->dp_opts, dp_opts, sizeof(*dp_opts)); + if (layout->dp_opts.set_voltages) { + cfg->configure_dp_tx(qmp); + layout->dp_opts.set_voltages =3D 0; + } + + mutex_unlock(&qmp->phy_mutex); + + return 0; +} + +static int qmp_usbc_dp_calibrate(struct phy *phy) +{ + struct qmp_usbc *qmp =3D phy_get_drvdata(phy); + struct qmp_phy_dp_cfg *cfg =3D to_dp_cfg(qmp); + int ret =3D 0; + + mutex_lock(&qmp->phy_mutex); + + if (cfg->calibrate_dp_phy) { + ret =3D cfg->calibrate_dp_phy(qmp); + if (ret) { + dev_err(qmp->dev, "dp calibrate err(%d)\n", ret); + mutex_unlock(&qmp->phy_mutex); + return ret; + } + } + + mutex_unlock(&qmp->phy_mutex); + return 0; +} + +static int qmp_usbc_dp_serdes_init(struct qmp_usbc *qmp) +{ + struct qmp_phy_dp_layout *layout =3D to_dp_layout(qmp); + struct qmp_phy_dp_cfg *cfg =3D to_dp_cfg(qmp); + void __iomem *serdes =3D layout->dp_serdes; + const struct phy_configure_opts_dp *dp_opts =3D &layout->dp_opts; + + qmp_configure(qmp->dev, serdes, cfg->dp_serdes_tbl, + cfg->dp_serdes_tbl_num); + + switch (dp_opts->link_rate) { + case 1620: + qmp_configure(qmp->dev, serdes, cfg->serdes_tbl_rbr, + cfg->serdes_tbl_rbr_num); + break; + case 2700: + qmp_configure(qmp->dev, serdes, cfg->serdes_tbl_hbr, + cfg->serdes_tbl_hbr_num); + break; + case 5400: + qmp_configure(qmp->dev, serdes, cfg->serdes_tbl_hbr2, + cfg->serdes_tbl_hbr2_num); + break; + default: + /* Other link rates aren't supported */ + return -EINVAL; + } + + return 0; +} + +static int qmp_usbc_dp_power_on(struct phy *phy) +{ + struct qmp_usbc *qmp =3D phy_get_drvdata(phy); + const struct qmp_phy_dp_cfg *cfg =3D to_dp_cfg(qmp); + struct qmp_phy_dp_layout *layout =3D to_dp_layout(qmp); + + void __iomem *tx =3D layout->dp_tx; + void __iomem *tx2 =3D layout->dp_tx2; + + mutex_lock(&qmp->phy_mutex); + + qmp_usbc_dp_serdes_init(qmp); + + qmp_configure_lane(qmp->dev, tx, cfg->dp_tx_tbl, cfg->dp_tx_tbl_num, 1); + qmp_configure_lane(qmp->dev, tx2, cfg->dp_tx_tbl, cfg->dp_tx_tbl_num, 2); + + /* Configure special DP tx tunings */ + cfg->configure_dp_tx(qmp); + + /* Configure link rate, swing, etc. */ + cfg->configure_dp_phy(qmp); + + mutex_unlock(&qmp->phy_mutex); + + return 0; +} + +static int qmp_usbc_dp_power_off(struct phy *phy) +{ + struct qmp_usbc *qmp =3D phy_get_drvdata(phy); + struct qmp_phy_dp_layout *layout =3D to_dp_layout(qmp); + + mutex_lock(&qmp->phy_mutex); + + /* Assert DP PHY power down */ + writel(DP_PHY_PD_CTL_PSR_PWRDN, layout->dp_phy + QSERDES_DP_PHY_PD_CTL); + + mutex_unlock(&qmp->phy_mutex); + + return 0; +} + static const struct phy_ops qmp_usbc_usb_phy_ops =3D { .init =3D qmp_usbc_usb_enable, .exit =3D qmp_usbc_usb_disable, @@ -1158,6 +1317,16 @@ static const struct phy_ops qmp_usbc_usb_phy_ops =3D= { .owner =3D THIS_MODULE, }; =20 +static const struct phy_ops qmp_usbc_dp_phy_ops =3D { + .init =3D qmp_usbc_dp_enable, + .exit =3D qmp_usbc_dp_disable, + .configure =3D qmp_usbc_dp_configure, + .calibrate =3D qmp_usbc_dp_calibrate, + .power_on =3D qmp_usbc_dp_power_on, + .power_off =3D qmp_usbc_dp_power_off, + .owner =3D THIS_MODULE, +}; + static void qmp_usbc_enable_autonomous_mode(struct qmp_usbc *qmp) { const struct qmp_phy_usb_cfg *cfg =3D to_usb_cfg(qmp); @@ -1284,6 +1453,32 @@ static int qmp_usbc_vreg_init(struct qmp_usbc *qmp) dev_err(dev, "failed at devm_regulator_bulk_get\n"); return ret; } + } else { + struct qmp_phy_dp_cfg *cfg =3D to_dp_cfg(qmp); + int num =3D cfg->num_vregs; + + qmp->vregs =3D devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL); + if (!qmp->vregs) + return -ENOMEM; + + for (i =3D 0; i < num; i++) + qmp->vregs[i].supply =3D cfg->vreg_list[i].name; + + ret =3D devm_regulator_bulk_get(dev, num, qmp->vregs); + if (ret) { + dev_err(dev, "failed at devm_regulator_bulk_get\n"); + return ret; + } + + for (i =3D 0; i < num; i++) { + ret =3D regulator_set_load(qmp->vregs[i].consumer, + cfg->vreg_list[i].enable_load); + if (ret) { + dev_err(dev, "failed to set load at %s\n", + qmp->vregs[i].supply); + return ret; + } + } } =20 return 0; @@ -1337,6 +1532,28 @@ static void phy_clk_release_provider(void *res) of_clk_del_provider(res); } =20 +static struct clk_hw *qmp_usbc_clks_hw_get(struct of_phandle_args *clkspec= , void *data) +{ + struct qmp_usbc *qmp =3D data; + + if (qmp->type =3D=3D QMP_PHY_USBC_USB) { + struct qmp_phy_usb_layout *layout =3D to_usb_layout(qmp); + + return &layout->pipe_clk_fixed.hw; + } + + struct qmp_phy_dp_layout *layout =3D to_dp_layout(qmp); + + switch (clkspec->args[0]) { + case QMP_USB43DP_DP_LINK_CLK: + return &layout->dp_link_hw; + case QMP_USB43DP_DP_VCO_DIV_CLK: + return &layout->dp_pixel_hw; + } + + return ERR_PTR(-EINVAL); +} + /* * Register a fixed rate pipe clock. * @@ -1379,9 +1596,11 @@ static int phy_pipe_clk_register(struct qmp_usbc *qm= p, struct device_node *np) if (ret) return ret; =20 - ret =3D of_clk_add_hw_provider(np, of_clk_hw_simple_get, &fixed->hw); - if (ret) + ret =3D of_clk_add_hw_provider(np, qmp_usbc_clks_hw_get, qmp); + if (ret) { + dev_err(qmp->dev, "add provider fail ret:%d\n", ret); return ret; + } =20 /* * Roll a devm action because the clock provider is the child node, but @@ -1577,6 +1796,238 @@ static int qmp_usbc_parse_vls_clamp(struct qmp_usbc= *qmp) return 0; } =20 +static int qmp_usbc_parse_dp_tcsr(struct qmp_usbc *qmp) +{ + struct of_phandle_args tcsr_args; + struct device *dev =3D qmp->dev; + int ret; + + ret =3D of_parse_phandle_with_fixed_args(dev->of_node, "qcom,tcsr-reg", 1= , 0, + &tcsr_args); + if (ret < 0) + return dev_err_probe(dev, ret, "Failed to parse qcom,tcsr-reg\n"); + + qmp->tcsr_map =3D syscon_node_to_regmap(tcsr_args.np); + of_node_put(tcsr_args.np); + if (IS_ERR(qmp->tcsr_map)) + return PTR_ERR(qmp->tcsr_map); + + qmp->dp_phy_mode_reg =3D tcsr_args.args[0]; + + return 0; +} + +static int qmp_usbc_parse_dp_dt(struct qmp_usbc *qmp) +{ + struct platform_device *pdev =3D to_platform_device(qmp->dev); + struct qmp_phy_dp_layout *layout =3D to_dp_layout(qmp); + struct qmp_phy_dp_cfg *cfg =3D to_dp_cfg(qmp); + const struct qmp_usbc_dp_offsets *offs =3D cfg->offsets; + struct device *dev =3D qmp->dev; + void __iomem *base; + int ret; + + base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) + return PTR_ERR(base); + + layout->dp_serdes =3D base + offs->dp_serdes; + layout->dp_tx =3D base + offs->dp_txa; + layout->dp_tx2 =3D base + offs->dp_txb; + layout->dp_phy =3D base + offs->dp_phy; + + ret =3D qmp_usbc_clk_init(qmp); + if (ret) { + dev_err(dev, "clk init fail, ret:%d\n", ret); + return ret; + } + + ret =3D qmp_usbc_reset_init(qmp, dpphy_reset_l, + ARRAY_SIZE(dpphy_reset_l)); + if (ret) + return ret; + + return 0; +} + +/* + * Display Port PLL driver block diagram for branch clocks + * + * +------------------------------+ + * | DP_VCO_CLK | + * | | + * | +-------------------+ | + * | | (DP PLL/VCO) | | + * | +---------+---------+ | + * | v | + * | +----------+-----------+ | + * | | hsclk_divsel_clk_src | | + * | +----------+-----------+ | + * +------------------------------+ + * | + * +---------<---------v------------>----------+ + * | | + * +--------v----------------+ | + * | dp_phy_pll_link_clk | | + * | link_clk | | + * +--------+----------------+ | + * | | + * | | + * v v + * Input to DISPCC block | + * for link clk, crypto clk | + * and interface clock | + * | + * | + * +--------<------------+-----------------+---<---+ + * | | | + * +----v---------+ +--------v-----+ +--------v------+ + * | vco_divided | | vco_divided | | vco_divided | + * | _clk_src | | _clk_src | | _clk_src | + * | | | | | | + * |divsel_six | | divsel_two | | divsel_four | + * +-------+------+ +-----+--------+ +--------+------+ + * | | | + * v---->----------v-------------<------v + * | + * +----------+-----------------+ + * | dp_phy_pll_vco_div_clk | + * +---------+------------------+ + * | + * v + * Input to DISPCC block + * for DP pixel clock + * + */ +static int qmp_dp_pixel_clk_determine_rate(struct clk_hw *hw, struct clk_r= ate_request *req) +{ + switch (req->rate) { + case 1620000000UL / 2: + case 2700000000UL / 2: + /* 5.4 and 8.1 GHz are same link rate as 2.7GHz, i.e. div 4 and div 6 */ + return 0; + default: + return -EINVAL; + } +} + +static unsigned long qmp_dp_pixel_clk_recalc_rate(struct clk_hw *hw, unsig= ned long parent_rate) +{ + struct qmp_phy_dp_layout *layout; + const struct phy_configure_opts_dp *dp_opts; + + layout =3D container_of(hw, struct qmp_phy_dp_layout, dp_pixel_hw); + + dp_opts =3D &layout->dp_opts; + + switch (dp_opts->link_rate) { + case 1620: + return 1620000000UL / 2; + case 2700: + return 2700000000UL / 2; + case 5400: + return 5400000000UL / 4; + default: + return 0; + } +} + +static const struct clk_ops qmp_dp_pixel_clk_ops =3D { + .determine_rate =3D qmp_dp_pixel_clk_determine_rate, + .recalc_rate =3D qmp_dp_pixel_clk_recalc_rate, +}; + +static int qmp_dp_link_clk_determine_rate(struct clk_hw *hw, struct clk_ra= te_request *req) +{ + switch (req->rate) { + case 162000000: + case 270000000: + case 540000000: + return 0; + default: + return -EINVAL; + } +} + +static unsigned long qmp_dp_link_clk_recalc_rate(struct clk_hw *hw, unsign= ed long parent_rate) +{ + struct qmp_phy_dp_layout *layout; + const struct phy_configure_opts_dp *dp_opts; + + layout =3D container_of(hw, struct qmp_phy_dp_layout, dp_link_hw); + dp_opts =3D &layout->dp_opts; + + switch (dp_opts->link_rate) { + case 1620: + case 2700: + case 5400: + return dp_opts->link_rate * 100000; + default: + return 0; + } +} + +static const struct clk_ops qmp_dp_link_clk_ops =3D { + .determine_rate =3D qmp_dp_link_clk_determine_rate, + .recalc_rate =3D qmp_dp_link_clk_recalc_rate, +}; + +static int phy_dp_clks_register(struct qmp_usbc *qmp, struct device_node *= np) +{ + struct clk_init_data init =3D { }; + int ret =3D 0; + struct qmp_phy_dp_layout *layout =3D to_dp_layout(qmp); + + ret =3D of_property_read_string_index(np, "clock-output-names", 0, &init.= name); + if (ret < 0) { + dev_err(qmp->dev, "%pOFn: No link clock-output-names\n", np); + return ret; + } + + init.ops =3D &qmp_dp_link_clk_ops; + layout->dp_link_hw.init =3D &init; + ret =3D devm_clk_hw_register(qmp->dev, &layout->dp_link_hw); + if (ret < 0) { + dev_err(qmp->dev, "link clk reg fail ret=3D%d\n", ret); + return ret; + } + + ret =3D of_property_read_string_index(np, "clock-output-names", 1, &init.= name); + if (ret) { + dev_err(qmp->dev, "%pOFn: No div clock-output-names\n", np); + return ret; + } + + init.ops =3D &qmp_dp_pixel_clk_ops; + layout->dp_pixel_hw.init =3D &init; + ret =3D devm_clk_hw_register(qmp->dev, &layout->dp_pixel_hw); + if (ret) { + dev_err(qmp->dev, "pxl clk reg fail ret=3D%d\n", ret); + return ret; + } + + return 0; +} + +static int qmp_dp_register_clocks(struct qmp_usbc *qmp, struct device_node= *dp_np) +{ + int ret; + + ret =3D phy_dp_clks_register(qmp, dp_np); + if (ret) { + dev_err(qmp->dev, "dp clk reg fail ret:%d\n", ret); + return ret; + } + + ret =3D of_clk_add_hw_provider(dp_np, qmp_usbc_clks_hw_get, qmp); + if (ret) { + dev_err(qmp->dev, "add provider fail ret:%d\n", ret); + return ret; + } + + return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, dp_np= ); +} + static int qmp_usbc_probe(struct platform_device *pdev) { struct device *dev =3D &pdev->dev; @@ -1625,9 +2076,29 @@ static int qmp_usbc_probe(struct platform_device *pd= ev) np =3D of_node_get(dev->of_node); ret =3D qmp_usbc_parse_usb_dt(qmp); } + if (ret) + goto err_node_put; + } else { + qmp->layout =3D devm_kzalloc(dev, sizeof(struct qmp_phy_dp_layout), GFP_= KERNEL); + if (!qmp->layout) + return -ENOMEM; =20 + np =3D of_node_get(dev->of_node); + ret =3D qmp_usbc_parse_dp_tcsr(qmp); if (ret) goto err_node_put; + + ret =3D qmp_usbc_parse_dp_dt(qmp); + if (ret) { + dev_err(qmp->dev, "parse DP dt fail ret=3D%d\n", ret); + goto err_node_put; + } + + ret =3D drm_aux_bridge_register(dev); + if (ret) { + dev_err(qmp->dev, "aux bridge reg fail ret=3D%d\n", ret); + goto err_node_put; + } } =20 ret =3D qmp_usbc_typec_switch_register(qmp); @@ -1655,6 +2126,17 @@ static int qmp_usbc_probe(struct platform_device *pd= ev) dev_err(dev, "failed to create PHY: %d\n", ret); goto err_node_put; } + } else { + ret =3D qmp_dp_register_clocks(qmp, np); + if (ret) + goto err_node_put; + + qmp->phy =3D devm_phy_create(dev, np, &qmp_usbc_dp_phy_ops); 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This allows the driver to detect and manage mutually exclusive PHYs at runtime, preventing configuration conflicts when both PHYs are present on the same platform but operate independently. Signed-off-by: Xiangxu Yin --- drivers/phy/qualcomm/phy-qcom-qmp-usbc.c | 51 ++++++++++++++++++++++++++++= ++-- 1 file changed, 48 insertions(+), 3 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c b/drivers/phy/qualcom= m/phy-qcom-qmp-usbc.c index 6291298904de9717283e59f1ca2a845b46146d52..e97a206a10554b2d157d1fadd66= d66386eec6c40 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c @@ -514,8 +514,13 @@ struct qmp_usbc { u32 dp_phy_mode_reg; =20 struct typec_switch_dev *sw; + + struct list_head list; }; =20 +static LIST_HEAD(phy_list); +static DEFINE_MUTEX(phy_list_mutex); + static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val) { u32 reg; @@ -1107,6 +1112,25 @@ static int qmp_usbc_usb_power_off(struct phy *phy) return 0; } =20 +static int qmp_check_mutex_phy(struct qmp_usbc *qmp) +{ + struct qmp_usbc *mutex_qmp =3D NULL; + + mutex_lock(&phy_list_mutex); + list_for_each_entry(mutex_qmp, &phy_list, list) { + if (qmp->type !=3D mutex_qmp->type && + mutex_qmp->dp_phy_mode_reg =3D=3D qmp->dp_phy_mode_reg && + mutex_qmp->init_count > 0) { + dev_info(qmp->dev, "Mutex phy busy!\n"); + mutex_unlock(&phy_list_mutex); + return -EBUSY; + } + } + mutex_unlock(&phy_list_mutex); + + return 0; +} + static int qmp_usbc_usb_enable(struct phy *phy) { struct qmp_usbc *qmp =3D phy_get_drvdata(phy); @@ -1114,6 +1138,10 @@ static int qmp_usbc_usb_enable(struct phy *phy) =20 mutex_lock(&qmp->phy_mutex); =20 + ret =3D qmp_check_mutex_phy(qmp); + if (ret) + goto out_unlock; + ret =3D qmp_usbc_generic_init(phy); if (ret) goto out_unlock; @@ -1166,6 +1194,10 @@ static int qmp_usbc_dp_enable(struct phy *phy) =20 mutex_lock(&qmp->phy_mutex); =20 + ret =3D qmp_check_mutex_phy(qmp); + if (ret) + goto dp_init_unlock; + ret =3D qmp_usbc_generic_init(phy); if (ret) { dev_err(qmp->dev, "type(%d) com_init fail\n", qmp->type); @@ -1772,15 +1804,16 @@ static int qmp_usbc_parse_usb_dt(struct qmp_usbc *q= mp) return 0; } =20 -static int qmp_usbc_parse_vls_clamp(struct qmp_usbc *qmp) +static int qmp_usbc_parse_usb_tcsr(struct qmp_usbc *qmp) { struct of_phandle_args tcsr_args; struct device *dev =3D qmp->dev; int ret; =20 - /* for backwards compatibility ignore if there is no property */ + /* for backwards compatibility ignore if there is 1 or no property */ ret =3D of_parse_phandle_with_fixed_args(dev->of_node, "qcom,tcsr-reg", 1= , 0, &tcsr_args); + if (ret =3D=3D -ENOENT) return 0; else if (ret < 0) @@ -1793,6 +1826,13 @@ static int qmp_usbc_parse_vls_clamp(struct qmp_usbc = *qmp) =20 qmp->vls_clamp_reg =3D tcsr_args.args[0]; =20 + ret =3D of_parse_phandle_with_fixed_args(dev->of_node, "qcom,tcsr-reg", 1= , 1, + &tcsr_args); + if (ret =3D=3D -ENOENT) + return 0; + + qmp->dp_phy_mode_reg =3D tcsr_args.args[0]; + return 0; } =20 @@ -2051,6 +2091,7 @@ static int qmp_usbc_probe(struct platform_device *pde= v) return -EINVAL; =20 mutex_init(&qmp->phy_mutex); + INIT_LIST_HEAD(&qmp->list); =20 qmp->type =3D data_cfg->type; qmp->cfg =3D data_cfg->cfg; @@ -2064,7 +2105,7 @@ static int qmp_usbc_probe(struct platform_device *pde= v) if (!qmp->layout) return -ENOMEM; =20 - ret =3D qmp_usbc_parse_vls_clamp(qmp); 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With this change, the DP PHY driver for QCS615 is fully integrated: - All required ops and flow are implemented - Platform-specific configuration and init data are in place - Compatible handling is aligned with USB3.0 PHY via type-based dispatch - Supports coexistence with USB3.0 PHY through mutual exclusion based on shared TCSR region This enables end-to-end support for DP PHY mode on QCS615 platforms. Signed-off-by: Xiangxu Yin --- drivers/phy/qualcomm/phy-qcom-qmp-usbc.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c b/drivers/phy/qualcom= m/phy-qcom-qmp-usbc.c index e97a206a10554b2d157d1fadd66d66386eec6c40..35fecf78736f7a6b9c3af6a89c7= 1fd3ad9a87496 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c @@ -699,6 +699,11 @@ static const struct qmp_phy_cfg sdm660_phy_usb3_cfg = =3D { .cfg =3D &sdm660_usb3phy_cfg, }; =20 +static const struct qmp_phy_cfg qcs615_phy_dp_cfg =3D { + .type =3D QMP_PHY_USBC_DP, + .cfg =3D &qcs615_dpphy_cfg, +}; + #define to_usb_cfg(x) ((struct qmp_phy_usb_cfg *)((x)->cfg)) #define to_dp_cfg(x) ((struct qmp_phy_dp_cfg *)((x)->cfg)) #define to_usb_layout(x) ((struct qmp_phy_usb_layout *)((x)->layout)) @@ -2204,6 +2209,9 @@ static const struct of_device_id qmp_usbc_of_match_ta= ble[] =3D { }, { .compatible =3D "qcom,qcm2290-qmp-usb3-phy", .data =3D &qcm2290_phy_usb3_cfg, + }, { + .compatible =3D "qcom,qcs615-qmp-dp-phy", + .data =3D &qcs615_phy_dp_cfg, }, { .compatible =3D "qcom,qcs615-qmp-usb3-phy", .data =3D &qcm2290_phy_usb3_cfg, --=20 2.34.1 From nobody Mon Oct 6 11:57:30 2025 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 17FE92C15A5 for ; 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Reviewed-by: Dmitry Baryshkov Signed-off-by: Xiangxu Yin --- drivers/gpu/drm/msm/dp/dp_display.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/d= p_display.c index d87d47cc7ec3eb757ac192c411000bc50b824c59..ddb22b50490035779904d4cab20= e2fee7e0f9657 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -196,6 +196,7 @@ static const struct of_device_id msm_dp_dt_match[] =3D { { .compatible =3D "qcom,sc8280xp-dp", .data =3D &msm_dp_desc_sc8280xp }, { .compatible =3D "qcom,sc8280xp-edp", .data =3D &msm_dp_desc_sc8280xp }, { .compatible =3D "qcom,sdm845-dp", .data =3D &msm_dp_desc_sdm845 }, + { .compatible =3D "qcom,sm6150-dp", .data =3D &msm_dp_desc_sc7180 }, { .compatible =3D "qcom,sm8350-dp", .data =3D &msm_dp_desc_sc7180 }, { .compatible =3D "qcom,sm8650-dp", .data =3D &msm_dp_desc_sm8650 }, { .compatible =3D "qcom,x1e80100-dp", .data =3D &msm_dp_desc_x1e80100 }, --=20 2.34.1 From nobody Mon Oct 6 11:57:30 2025 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 29B822D3742 for ; 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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-31cc3e45e6csm7490753a91.3.2025.07.22.00.23.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Jul 2025 00:23:51 -0700 (PDT) From: Xiangxu Yin Date: Tue, 22 Jul 2025 15:22:14 +0800 Subject: [PATCH v2 13/13] drm/msm/dp: Add support for lane mapping configuration Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250722-add-displayport-support-for-qcs615-platform-v2-13-42b4037171f8@oss.qualcomm.com> References: <20250722-add-displayport-support-for-qcs615-platform-v2-0-42b4037171f8@oss.qualcomm.com> In-Reply-To: <20250722-add-displayport-support-for-qcs615-platform-v2-0-42b4037171f8@oss.qualcomm.com> To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Kuogee Hsieh , Vinod Koul , Kishon Vijay Abraham I Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, dmitry.baryshkov@oss.qualcomm.com, konrad.dybcio@oss.qualcomm.com, fange.zhang@oss.qualcomm.com, quic_lliu6@quicinc.com, quic_yongmou@quicinc.com, Xiangxu Yin X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1753168938; l=11603; i=xiangxu.yin@oss.qualcomm.com; s=20241125; h=from:subject:message-id; bh=1od1x0khFrwfMLUnR4xw/dFXf07Vmo4IXF/QPtNukLQ=; b=22uwtEHDknol6p+guCL6gTd6/l2boxMJtMRJfEpMolrKz8FrRthhJTl+UL9Si1r9s6y8ujyon 3n8olREt5hfCEJWY7gDOhY7d5cMoGyNH1qXBbZus8RiMNOYEqQMIylx X-Developer-Key: i=xiangxu.yin@oss.qualcomm.com; a=ed25519; pk=F1TwipJzpywfbt3n/RPi4l/A4AVF+QC89XzCHgZYaOc= X-Proofpoint-ORIG-GUID: sD8y9YYgCqzdZG3gxjt6dlaSXlvDo0En X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzIyMDA1OSBTYWx0ZWRfXyfYao3Cb+dkn G5N0CgbQU6y2z6WYxFDfolUy8+xc4oiXO+l1zFXY6Zi6E/mITqMc6O1BCwzsJvgQ/WqnXm0eXV4 lJDn07BePJN/8IZRNO0qhie0+IAqTfbV6Lv+EHQ+A/9VFzhNFUubrKbnVKxNcUhr/VjLjeKgjZn B7jgJBev2wwm1baeiJuULcmIoWAM1sZgDUv3Ie4zZurzTxHxHgDcsFpMg8kO/k8gJRuKr1ZK+Hd n2221GGJPRhnX8cxQFJJJAOgXN33aMxH5aYVdb6KgKlkDyN+aLmItBGbPxwB/D8DMYsXRlXsSNG 3Pm8BkhVXAwk1j3IWUgm0fsovKWZeNl3I/wjAKWMgrQ3FUTS9XRgt83zt5DtyPACXPBh5C2keR5 cdK3gehzk6SHrc3CtxemGcQVxpdtu9v55eUTzPePz28RYiMIGVhzT9hc6aFHtcFJdQWDOABb X-Authority-Analysis: v=2.4 cv=Q+fS452a c=1 sm=1 tr=0 ts=687f3c89 cx=c_pps a=UNFcQwm+pnOIJct1K4W+Mw==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=Wb1JkmetP80A:10 a=EUspDBNiAAAA:8 a=NfoP-xiufhIyd-I1U-kA:9 a=QEXdDO2ut3YA:10 a=uKXjsCUrEbL0IQVhDsJ9:22 X-Proofpoint-GUID: sD8y9YYgCqzdZG3gxjt6dlaSXlvDo0En X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-22_01,2025-07-21_02,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 adultscore=0 phishscore=0 mlxscore=0 lowpriorityscore=0 mlxlogscore=999 suspectscore=0 spamscore=0 priorityscore=1501 malwarescore=0 bulkscore=0 impostorscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507220059 Since max_dp_lanes and max_dp_link_rate are link-specific parameters, move their parsing from dp_panel to dp_link for better separation of concerns. Add lane mapping configuration for the DisplayPort (DP) controller on the QCS615 platform. QCS615 platform requires non-default logical-to-physical lane mapping due to its unique hardware routing. Unlike the standard mapping sequence <0 1 2 3>, QCS615 uses <3 2 0 1>, which necessitates explicit configuration via the data-lanes property in the device tree. This ensures correct signal routing between the DP controller and PHY. The DP PHY supports polarity inversion (PN swap) but does not support lane swapping. Therefore, lane mapping should be handled in the DP controller domain using REG_DP_LOGICAL2PHYSICAL_LANE_MAPPING. Signed-off-by: Xiangxu Yin --- drivers/gpu/drm/msm/dp/dp_ctrl.c | 10 ++--- drivers/gpu/drm/msm/dp/dp_link.c | 71 +++++++++++++++++++++++++++++++++++ drivers/gpu/drm/msm/dp/dp_link.h | 5 +++ drivers/gpu/drm/msm/dp/dp_panel.c | 78 +++++------------------------------= ---- drivers/gpu/drm/msm/dp/dp_panel.h | 3 -- 5 files changed, 90 insertions(+), 77 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_c= trl.c index c42fd2c17a328f6deae211c9cd57cc7416a9365a..cbcc7c2f0ffc4696749b6c43818= d20853ddec069 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c @@ -423,13 +423,13 @@ static void msm_dp_ctrl_config_ctrl(struct msm_dp_ctr= l_private *ctrl) =20 static void msm_dp_ctrl_lane_mapping(struct msm_dp_ctrl_private *ctrl) { - u32 ln_0 =3D 0, ln_1 =3D 1, ln_2 =3D 2, ln_3 =3D 3; /* One-to-One mapping= */ + u32 *lane_map =3D ctrl->link->lane_map; u32 ln_mapping; =20 - ln_mapping =3D ln_0 << LANE0_MAPPING_SHIFT; - ln_mapping |=3D ln_1 << LANE1_MAPPING_SHIFT; - ln_mapping |=3D ln_2 << LANE2_MAPPING_SHIFT; - ln_mapping |=3D ln_3 << LANE3_MAPPING_SHIFT; + ln_mapping =3D lane_map[0] << LANE0_MAPPING_SHIFT; + ln_mapping |=3D lane_map[1] << LANE1_MAPPING_SHIFT; + ln_mapping |=3D lane_map[2] << LANE2_MAPPING_SHIFT; + ln_mapping |=3D lane_map[3] << LANE3_MAPPING_SHIFT; =20 msm_dp_write_link(ctrl, REG_DP_LOGICAL2PHYSICAL_LANE_MAPPING, ln_mapping); diff --git a/drivers/gpu/drm/msm/dp/dp_link.c b/drivers/gpu/drm/msm/dp/dp_l= ink.c index 66e1bbd80db3a28f5f16d083486752007ceaf3f7..7c7a4aa584eb42a0ca7c6ec45de= 585cde8639cb4 100644 --- a/drivers/gpu/drm/msm/dp/dp_link.c +++ b/drivers/gpu/drm/msm/dp/dp_link.c @@ -6,12 +6,14 @@ #define pr_fmt(fmt) "[drm-dp] %s: " fmt, __func__ =20 #include +#include #include =20 #include "dp_reg.h" #include "dp_link.h" #include "dp_panel.h" =20 +#define DP_LINK_RATE_HBR2 540000 /* kbytes */ #define DP_TEST_REQUEST_MASK 0x7F =20 enum audio_sample_rate { @@ -37,6 +39,7 @@ struct msm_dp_link_request { =20 struct msm_dp_link_private { u32 prev_sink_count; + struct device *dev; struct drm_device *drm_dev; struct drm_dp_aux *aux; struct msm_dp_link msm_dp_link; @@ -1210,10 +1213,73 @@ u32 msm_dp_link_get_test_bits_depth(struct msm_dp_l= ink *msm_dp_link, u32 bpp) return tbd; } =20 +static u32 msm_dp_link_link_frequencies(struct device_node *of_node) +{ + struct device_node *endpoint; + u64 frequency =3D 0; + int cnt; + + endpoint =3D of_graph_get_endpoint_by_regs(of_node, 1, 0); /* port@1 */ + if (!endpoint) + return 0; + + cnt =3D of_property_count_u64_elems(endpoint, "link-frequencies"); + + if (cnt > 0) + of_property_read_u64_index(endpoint, "link-frequencies", + cnt - 1, &frequency); + of_node_put(endpoint); + + do_div(frequency, + 10 * /* from symbol rate to link rate */ + 1000); /* kbytes */ + + return frequency; +} + +static int msm_dp_link_parse_dt(struct msm_dp_link *msm_dp_link) +{ + struct msm_dp_link_private *link; + struct device_node *of_node; + int cnt; + u32 lane_map[DP_MAX_NUM_DP_LANES] =3D {0}; + + link =3D container_of(msm_dp_link, struct msm_dp_link_private, msm_dp_lin= k); + of_node =3D link->dev->of_node; + + /* + * data-lanes is the property of msm_dp_out endpoint + */ + cnt =3D drm_of_get_data_lanes_count_ep(of_node, 1, 0, 1, DP_MAX_NUM_DP_LA= NES); + if (cnt < 0) { + /* legacy code, data-lanes is the property of mdss_dp node */ + cnt =3D drm_of_get_data_lanes_count(of_node, 1, DP_MAX_NUM_DP_LANES); + } + + if (cnt > 0) { + struct device_node *endpoint; + + msm_dp_link->max_dp_lanes =3D cnt; + endpoint =3D of_graph_get_endpoint_by_regs(of_node, 1, -1); + of_property_read_u32_array(endpoint, "data-lanes", lane_map, cnt); + } else { + msm_dp_link->max_dp_lanes =3D DP_MAX_NUM_DP_LANES; /* 4 lanes */ + } + + memcpy(msm_dp_link->lane_map, lane_map, msm_dp_link->max_dp_lanes * sizeo= f(u32)); + + msm_dp_link->max_dp_link_rate =3D msm_dp_link_link_frequencies(of_node); + if (!msm_dp_link->max_dp_link_rate) + msm_dp_link->max_dp_link_rate =3D DP_LINK_RATE_HBR2; + + return 0; +} + struct msm_dp_link *msm_dp_link_get(struct device *dev, struct drm_dp_aux = *aux) { struct msm_dp_link_private *link; struct msm_dp_link *msm_dp_link; + int ret; =20 if (!dev || !aux) { DRM_ERROR("invalid input\n"); @@ -1225,9 +1291,14 @@ struct msm_dp_link *msm_dp_link_get(struct device *d= ev, struct drm_dp_aux *aux) return ERR_PTR(-ENOMEM); =20 link->aux =3D aux; + link->dev =3D dev; =20 mutex_init(&link->psm_mutex); msm_dp_link =3D &link->msm_dp_link; =20 + ret =3D msm_dp_link_parse_dt(msm_dp_link); + if (ret) + return ERR_PTR(ret); + return msm_dp_link; } diff --git a/drivers/gpu/drm/msm/dp/dp_link.h b/drivers/gpu/drm/msm/dp/dp_l= ink.h index ba47c6d19fbfacfc58031263e4a2f5a6d9c2c229..b1eb2de6d2a7693f17aa2f25665= 7110af839533d 100644 --- a/drivers/gpu/drm/msm/dp/dp_link.h +++ b/drivers/gpu/drm/msm/dp/dp_link.h @@ -12,6 +12,7 @@ #define DS_PORT_STATUS_CHANGED 0x200 #define DP_TEST_BIT_DEPTH_UNKNOWN 0xFFFFFFFF #define DP_LINK_CAP_ENHANCED_FRAMING (1 << 0) +#define DP_MAX_NUM_DP_LANES 4 =20 struct msm_dp_link_info { unsigned char revision; @@ -72,6 +73,10 @@ struct msm_dp_link { struct msm_dp_link_test_audio test_audio; struct msm_dp_link_phy_params phy_params; struct msm_dp_link_info link_params; + + u32 lane_map[DP_MAX_NUM_DP_LANES]; + u32 max_dp_lanes; + u32 max_dp_link_rate; }; =20 /** diff --git a/drivers/gpu/drm/msm/dp/dp_panel.c b/drivers/gpu/drm/msm/dp/dp_= panel.c index 15b7f6c7146e1176a80b5c9d25896b1c8ede3aed..ad5d55bf009dbe60e61ca4f4c10= 8116333129203 100644 --- a/drivers/gpu/drm/msm/dp/dp_panel.c +++ b/drivers/gpu/drm/msm/dp/dp_panel.c @@ -16,9 +16,6 @@ =20 #define DP_INTF_CONFIG_DATABUS_WIDEN BIT(4) =20 -#define DP_MAX_NUM_DP_LANES 4 -#define DP_LINK_RATE_HBR2 540000 /* kbytes */ - struct msm_dp_panel_private { struct device *dev; struct drm_device *drm_dev; @@ -91,6 +88,7 @@ static int msm_dp_panel_read_dpcd(struct msm_dp_panel *ms= m_dp_panel) int rc, max_lttpr_lanes, max_lttpr_rate; struct msm_dp_panel_private *panel; struct msm_dp_link_info *link_info; + struct msm_dp_link *link; u8 *dpcd, major, minor; =20 panel =3D container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_= panel); @@ -105,16 +103,20 @@ static int msm_dp_panel_read_dpcd(struct msm_dp_panel= *msm_dp_panel) major =3D (link_info->revision >> 4) & 0x0f; minor =3D link_info->revision & 0x0f; =20 + link =3D panel->link; + drm_dbg_dp(panel->drm_dev, "max_lanes=3D%d max_link_rate=3D%d\n", + link->max_dp_lanes, link->max_dp_link_rate); + link_info->rate =3D drm_dp_max_link_rate(dpcd); link_info->num_lanes =3D drm_dp_max_lane_count(dpcd); =20 /* Limit data lanes from data-lanes of endpoint property of dtsi */ - if (link_info->num_lanes > msm_dp_panel->max_dp_lanes) - link_info->num_lanes =3D msm_dp_panel->max_dp_lanes; + if (link_info->num_lanes > link->max_dp_lanes) + link_info->num_lanes =3D link->max_dp_lanes; =20 /* Limit link rate from link-frequencies of endpoint property of dtsi */ - if (link_info->rate > msm_dp_panel->max_dp_link_rate) - link_info->rate =3D msm_dp_panel->max_dp_link_rate; + if (link_info->rate > link->max_dp_link_rate) + link_info->rate =3D link->max_dp_link_rate; =20 /* Limit data lanes from LTTPR capabilities, if any */ max_lttpr_lanes =3D drm_dp_lttpr_max_lane_count(panel->link->lttpr_common= _caps); @@ -173,9 +175,6 @@ int msm_dp_panel_read_sink_caps(struct msm_dp_panel *ms= m_dp_panel, =20 panel =3D container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_= panel); =20 - drm_dbg_dp(panel->drm_dev, "max_lanes=3D%d max_link_rate=3D%d\n", - msm_dp_panel->max_dp_lanes, msm_dp_panel->max_dp_link_rate); - rc =3D msm_dp_panel_read_dpcd(msm_dp_panel); if (rc) { DRM_ERROR("read dpcd failed %d\n", rc); @@ -648,60 +647,6 @@ int msm_dp_panel_init_panel_info(struct msm_dp_panel *= msm_dp_panel) return 0; } =20 -static u32 msm_dp_panel_link_frequencies(struct device_node *of_node) -{ - struct device_node *endpoint; - u64 frequency =3D 0; - int cnt; - - endpoint =3D of_graph_get_endpoint_by_regs(of_node, 1, 0); /* port@1 */ - if (!endpoint) - return 0; - - cnt =3D of_property_count_u64_elems(endpoint, "link-frequencies"); - - if (cnt > 0) - of_property_read_u64_index(endpoint, "link-frequencies", - cnt - 1, &frequency); - of_node_put(endpoint); - - do_div(frequency, - 10 * /* from symbol rate to link rate */ - 1000); /* kbytes */ - - return frequency; -} - -static int msm_dp_panel_parse_dt(struct msm_dp_panel *msm_dp_panel) -{ - struct msm_dp_panel_private *panel; - struct device_node *of_node; - int cnt; - - panel =3D container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_= panel); - of_node =3D panel->dev->of_node; - - /* - * data-lanes is the property of msm_dp_out endpoint - */ - cnt =3D drm_of_get_data_lanes_count_ep(of_node, 1, 0, 1, DP_MAX_NUM_DP_LA= NES); - if (cnt < 0) { - /* legacy code, data-lanes is the property of mdss_dp node */ - cnt =3D drm_of_get_data_lanes_count(of_node, 1, DP_MAX_NUM_DP_LANES); - } - - if (cnt > 0) - msm_dp_panel->max_dp_lanes =3D cnt; - else - msm_dp_panel->max_dp_lanes =3D DP_MAX_NUM_DP_LANES; /* 4 lanes */ - - msm_dp_panel->max_dp_link_rate =3D msm_dp_panel_link_frequencies(of_node); - if (!msm_dp_panel->max_dp_link_rate) - msm_dp_panel->max_dp_link_rate =3D DP_LINK_RATE_HBR2; - - return 0; -} - struct msm_dp_panel *msm_dp_panel_get(struct device *dev, struct drm_dp_au= x *aux, struct msm_dp_link *link, void __iomem *link_base, @@ -709,7 +654,6 @@ struct msm_dp_panel *msm_dp_panel_get(struct device *de= v, struct drm_dp_aux *aux { struct msm_dp_panel_private *panel; struct msm_dp_panel *msm_dp_panel; - int ret; =20 if (!dev || !aux || !link) { DRM_ERROR("invalid input\n"); @@ -729,10 +673,6 @@ struct msm_dp_panel *msm_dp_panel_get(struct device *d= ev, struct drm_dp_aux *aux msm_dp_panel =3D &panel->msm_dp_panel; msm_dp_panel->max_bw_code =3D DP_LINK_BW_8_1; =20 - ret =3D msm_dp_panel_parse_dt(msm_dp_panel); - if (ret) - return ERR_PTR(ret); - return msm_dp_panel; } =20 diff --git a/drivers/gpu/drm/msm/dp/dp_panel.h b/drivers/gpu/drm/msm/dp/dp_= panel.h index d2cf401506dcbaf553192d5e18c87207337664ab..921a296852d4df65f817665d3e1= 344f2f7c9ece7 100644 --- a/drivers/gpu/drm/msm/dp/dp_panel.h +++ b/drivers/gpu/drm/msm/dp/dp_panel.h @@ -41,9 +41,6 @@ struct msm_dp_panel { bool vsc_sdp_supported; u32 hw_revision; =20 - u32 max_dp_lanes; - u32 max_dp_link_rate; - u32 max_bw_code; }; =20 --=20 2.34.1