From nobody Mon Oct 6 12:02:04 2025 Received: from NAM12-MW2-obe.outbound.protection.outlook.com (mail-mw2nam12on2053.outbound.protection.outlook.com [40.107.244.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 175B22367B0; Mon, 21 Jul 2025 20:05:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.244.53 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753128316; cv=fail; b=WEGL1ARKguj8okbcm2QZ6n/ol4QEiVcCt85zj5YNkGbPAJ36BrJWXPMMyzxw7lf0TYIfjE11cs4rfKFnRco+rnOMhlhx0aFLtsd0gFmZNJx0Lezj9SIgHXP8+Y/B/f+pizInRSOtcC57Z6iGbfx7ntlnkMKJfpi3mR8Xo0esDIg= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753128316; c=relaxed/simple; bh=ywTG86zSrSJYynn8vB7qKILrKKYyCO9vbtvcq6KU9bk=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=ejciaA90t4jH6sRCvuJbrNwW13AtZ0cM8tD2hzjiOlZ/d4HhmZ83f+DHgVVEPn+8QjV5N2MMfFADtEFgChpGcQ2wZ81hTX6rti3E61CmZgYNKkurmGLfFPJEjW/jPTTR5khDEvGBFr3o237jSFS/NZ4vZWAKYvv565hDU8iKoRI= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=S1WXuieg; arc=fail smtp.client-ip=40.107.244.53 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="S1WXuieg" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=wSth1OjPGwC3p4k2pp9O91vLpqsRj47OjkuU97AF0TkQoUqhX5DX63FsF9wBy9UFE2PY8oBRpIQbd99VX0uB1O1K0q/2amDvThGePD4YDFjvfS9VvBL1jrCk36fKRCOFnWjrRFR2C/rEKmi+nCZj/T9f57ytmKBTK6W9YAU7vPzu0Uugg+E5PIJgfJAhUepqn12yJyemdXkuG4rs8BOvPC419oBauiaZD25+8YqmX8a6gxXHVzRBrw3CqAO0+eih52NAnC/PdGMtUdcuFJWjrvLLwppt4yAJbBWkKXi4yeZv34kcuDQOCCUIEkiD8MmVaOxSxD7+mw9qwj+RtmIbdQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=FHiXigxA4hCOXWGH/DtJQxOyDx/fKf4nLlz61cNzowI=; b=XrdgVv04FuDyH7TB3ugvhQSgj72tugGAcbRfCvYrlJMcp1xXS9Hd7wA5g8t3zIz7dVXtlQ2NaGC+3TRWGHxr9TrzQy4+biKQliuo9NP+rzGUHtSTD5ZVCsnrLhUHME8uFBIjnlWuk7GKs4wd6+BpPs3/p244NXCt2A+HdrHyON/0sFx4LnNc5MKToVsYN61+qn412D1zNSQ9oCtMvUznSnNNkoYQDZGxRXuFx8yVEls80udR/ZBI33bW1bDVmC0pf5VdPvQTzwsF6CVOd58lRplgXd/xDJPedhAYhuKxmS2B2CNUFqKtdBrwL36GQr+kiv7KgLsmLtlRLJ8BH0rSKQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.118.233) smtp.rcpttodomain=kernel.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=FHiXigxA4hCOXWGH/DtJQxOyDx/fKf4nLlz61cNzowI=; b=S1WXuiegG5c/BiLbgig57ddB8c3fjDmSSyoDLtei7oPTTc4pqW8KOj0INDH2EV/VnB0gGRYNbuHbvz0wB/ebdyRI+QvBUXsheJRsvI4DZXw8pg5cJuVjttvQl3sEGy0yjYzP/MVPWknCEsYvUy2ybPad+vmiJoa4/3MBvSIFuqhztycWkHZaj3xnl71E8ooa42JTAWK4tAIS2eDUSz1B7/VIz3OiRkBiaBShPcx6Y/U4MYnKJxXuRwZxqB8GF7qVqid7J9QRd04dq/A76zZCUeflPC4avP4GXJArI47YAtmd4YGTQkb7dup1VCkDuD8avX1XR1aUioSpeC9dZWfiTg== Received: from BY3PR04CA0027.namprd04.prod.outlook.com (2603:10b6:a03:217::32) by IA0PR12MB8302.namprd12.prod.outlook.com (2603:10b6:208:40f::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8943.30; Mon, 21 Jul 2025 20:05:11 +0000 Received: from SJ1PEPF00001CE4.namprd03.prod.outlook.com (2603:10b6:a03:217:cafe::e1) by BY3PR04CA0027.outlook.office365.com (2603:10b6:a03:217::32) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.8943.29 via Frontend Transport; Mon, 21 Jul 2025 20:05:10 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.118.233) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.118.233 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.118.233; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.118.233) by SJ1PEPF00001CE4.mail.protection.outlook.com (10.167.242.20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8964.20 via Frontend Transport; Mon, 21 Jul 2025 20:05:10 +0000 Received: from drhqmail202.nvidia.com (10.126.190.181) by mail.nvidia.com (10.127.129.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Mon, 21 Jul 2025 13:04:56 -0700 Received: from drhqmail202.nvidia.com (10.126.190.181) by drhqmail202.nvidia.com (10.126.190.181) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.14; Mon, 21 Jul 2025 13:04:56 -0700 Received: from Asurada-Nvidia.nvidia.com (10.127.8.13) by mail.nvidia.com (10.126.190.181) with Microsoft SMTP Server id 15.2.1544.14 via Frontend Transport; Mon, 21 Jul 2025 13:04:55 -0700 From: Nicolin Chen To: , CC: , , , , , Subject: [PATCH v3 1/2] iommu/arm-smmu-v3: Do not bother impl_ops if IOMMU_VIOMMU_TYPE_ARM_SMMUV3 Date: Mon, 21 Jul 2025 13:04:43 -0700 Message-ID: <20250721200444.1740461-2-nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250721200444.1740461-1-nicolinc@nvidia.com> References: <20250721200444.1740461-1-nicolinc@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00001CE4:EE_|IA0PR12MB8302:EE_ X-MS-Office365-Filtering-Correlation-Id: 8269c930-69a4-4de8-3636-08ddc891e5c5 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|1800799024|36860700013|82310400026|7053199007; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?HpHcjZtL+mh63H1PBhEic48MpRd986yDOEOaAF2kfnqlk71gilB5Ep/DirzU?= =?us-ascii?Q?jwX5AT+j8AA6fF4ikdbSssb9aFu3uYkYAvnLkzsgOGYLxJ8s+t1/W3P6fvtC?= =?us-ascii?Q?nBMDFYMy0lbtc8vxgeLTz0GWRUt6/3bAtrGl7IQq9Uv/sqUNSpiXDcQVejYI?= =?us-ascii?Q?ikIdWMtwiemFCWN8SJ/do4upJNyhcGUOD5f2ATt800nl9z15P1+1+97AuNdc?= =?us-ascii?Q?3WBOoefywHSYnuIYYekypu7IZO1fD7abYx9gHlYa7rCGx/iI2c9DAXEdCWRO?= =?us-ascii?Q?Zgx1qb6OxZqyC6hMClt/ZTMVWQ8rxwVqFGxu2ULjvJfHBNP+0n/0PYAbdDIJ?= =?us-ascii?Q?xb7A1Z3D/MBxSAfYmWOforg2ADlDwvGNN1Z9qG6FaLGcY049/F29YY0924Yj?= =?us-ascii?Q?Pz3S6fcmjLJYjdCWzqMktUuvb3IGzW/cEuTtII1PEUQsO3pu6VgH+GaGmXYa?= =?us-ascii?Q?n0/Cz6O9cCSXmt5OSLTnJhYGrka9Ao9GczzwCmkoVbd8ErOU4DgU6wv4tnPw?= =?us-ascii?Q?pO/R79pt3baRC6xR+KOI0K5YvzZBAkyFuLbwZ+/fxi5t79njRWCyf+TtGIA+?= =?us-ascii?Q?JmhffHlDQ8YXP2T/FLpWKUhTCxXXIqCFaU4UT9OLalE6bIYQqNayXLKrdRyA?= =?us-ascii?Q?Pe2oNIGocQ93c6HVlhxWcO+3hX+vSdhnRhyUwUGG+PwUICrK628yVsXahEK4?= =?us-ascii?Q?WRNozTBGjdJfVFKy6CYK6GO2QvNodDckcxtv+65LhGo3sx0r9vkH09N49GWW?= =?us-ascii?Q?MXRpgvb9j8c87S1Dv+04DtTiYOZgvlNktRrCFN6FHG1FPLHDFBI/YSw3wPhs?= =?us-ascii?Q?CSW7Iu634dyIhT2WdNs79hpUVkSZYZyUFjbEVSZIvuu7/nxPt/QBVqGEgQWV?= =?us-ascii?Q?82oeSjFw5rCFsHmIULH3PCRNrpISaQG6PNIujgEVGmiNh56LMSAh475VuybH?= =?us-ascii?Q?NqEOCGHhZHAZuz3iBp8hoQZ7mhJXM6CeZnhj1rYKtl5YdP+5rCyIZLtx9wOT?= =?us-ascii?Q?PbHz4etC/yt3hNfgRWlQs8DwJYnWkDyDoPeZJipnblgtWUEzYvj25O231Js/?= =?us-ascii?Q?pBH7TovPNmGbsKAFJFtNTLKjOlFdTJyoe4TmFNtth7Go6Z64jdQIYSLE2SSD?= =?us-ascii?Q?ysWJgotyLx/ZubjWYxHyE/vWaSGkHBrq7LM6I/sJ0pUTFW80d1O1nmcSXi5O?= =?us-ascii?Q?s3qURR4yU+iiGYBzvxh+E+3jxcxFKXExCIJG+fDm4Mr1ui4JNa3lzE/IY/SR?= =?us-ascii?Q?nvRKyzh0NaYC3MxTmajxVtkNgeybO4+dxgga/L7tI0cjA+NZcq3jLyuDMxBa?= =?us-ascii?Q?5PhTwwwg5jhNO+zM0rO8gPC9Y5W3xCooot+rVWrN2+tKpI0dMG3PhZ9Y+vz3?= =?us-ascii?Q?NWGqlgpvuIpGGYXrMJNu8yRIxLhctkwqm6w4JH09gNlD4W65U2A4sUWpiCLT?= =?us-ascii?Q?YozMgUw2Hsy/iZjvmqmfJQmxuIEYBHvRYGkSid1k01USBbmKlZ5d/oa6267H?= =?us-ascii?Q?VB428SFfe+JQO8fZkc3dS0M6NfBxnB23gK42?= X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(1800799024)(36860700013)(82310400026)(7053199007);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Jul 2025 20:05:10.6999 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8269c930-69a4-4de8-3636-08ddc891e5c5 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00001CE4.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB8302 Content-Type: text/plain; charset="utf-8" When viommu type is IOMMU_VIOMMU_TYPE_ARM_SMMUV3, always return or init the standard struct arm_vsmmu, instead of going through impl_ops that must have its own viommu type than the standard IOMMU_VIOMMU_TYPE_ARM_SMMUV3. Given that arm_vsmmu_init() is called after arm_smmu_get_viommu_size(), any unsupported viommu->type must be a corruption. And it must be a driver bug that its vsmmu_size and vsmmu_init ops aren't paired. Warn these two cases. Suggested-by: Will Deacon Acked-by: Will Deacon Signed-off-by: Nicolin Chen Reviewed-by: Pranjal Shrivastava --- .../arm/arm-smmu-v3/arm-smmu-v3-iommufd.c | 24 ++++++++++--------- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 14 +++++++++++ 2 files changed, 27 insertions(+), 11 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c b/drivers/= iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c index d9bea8f1f636..c034d6c5468f 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c @@ -420,14 +420,13 @@ size_t arm_smmu_get_viommu_size(struct device *dev, !(smmu->features & ARM_SMMU_FEAT_S2FWB)) return 0; =20 - if (smmu->impl_ops && smmu->impl_ops->vsmmu_size && - viommu_type =3D=3D smmu->impl_ops->vsmmu_type) - return smmu->impl_ops->vsmmu_size; + if (viommu_type =3D=3D IOMMU_VIOMMU_TYPE_ARM_SMMUV3) + return VIOMMU_STRUCT_SIZE(struct arm_vsmmu, core); =20 - if (viommu_type !=3D IOMMU_VIOMMU_TYPE_ARM_SMMUV3) + if (!smmu->impl_ops || !smmu->impl_ops->vsmmu_size || + viommu_type !=3D smmu->impl_ops->vsmmu_type) return 0; - - return VIOMMU_STRUCT_SIZE(struct arm_vsmmu, core); + return smmu->impl_ops->vsmmu_size; } =20 int arm_vsmmu_init(struct iommufd_viommu *viommu, @@ -447,12 +446,15 @@ int arm_vsmmu_init(struct iommufd_viommu *viommu, /* FIXME Move VMID allocation from the S2 domain allocation to here */ vsmmu->vmid =3D s2_parent->s2_cfg.vmid; =20 - if (smmu->impl_ops && smmu->impl_ops->vsmmu_init && - viommu->type =3D=3D smmu->impl_ops->vsmmu_type) - return smmu->impl_ops->vsmmu_init(vsmmu, user_data); + if (viommu->type =3D=3D IOMMU_VIOMMU_TYPE_ARM_SMMUV3) { + viommu->ops =3D &arm_vsmmu_ops; + return 0; + } =20 - viommu->ops =3D &arm_vsmmu_ops; - return 0; + /* Unsupported type was rejected in arm_smmu_get_viommu_size() */ + if (WARN_ON(viommu->type !=3D smmu->impl_ops->vsmmu_type)) + return -EOPNOTSUPP; + return smmu->impl_ops->vsmmu_init(vsmmu, user_data); } =20 int arm_vmaster_report_event(struct arm_smmu_vmaster *vmaster, u64 *evt) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index 181d07bc1a9d..9f4ad3705801 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -4703,6 +4703,7 @@ static void arm_smmu_impl_remove(void *data) static struct arm_smmu_device *arm_smmu_impl_probe(struct arm_smmu_device = *smmu) { struct arm_smmu_device *new_smmu =3D ERR_PTR(-ENODEV); + const struct arm_smmu_impl_ops *ops; int ret; =20 if (smmu->impl_dev && (smmu->options & ARM_SMMU_OPT_TEGRA241_CMDQV)) @@ -4713,11 +4714,24 @@ static struct arm_smmu_device *arm_smmu_impl_probe(= struct arm_smmu_device *smmu) if (IS_ERR(new_smmu)) return new_smmu; =20 + ops =3D new_smmu->impl_ops; + if (ops) { + /* vsmmu_size and vsmmu_init ops must be paired */ + if (WARN_ON(!ops->vsmmu_size !=3D !ops->vsmmu_init)) { + ret =3D -EINVAL; + goto err_remove; + } + } + ret =3D devm_add_action_or_reset(new_smmu->dev, arm_smmu_impl_remove, new_smmu); if (ret) return ERR_PTR(ret); return new_smmu; + +err_remove: + arm_smmu_impl_remove(new_smmu); + return ERR_PTR(ret); } =20 static int arm_smmu_device_probe(struct platform_device *pdev) --=20 2.43.0 From nobody Mon Oct 6 12:02:04 2025 Received: from NAM02-SN1-obe.outbound.protection.outlook.com (mail-sn1nam02on2060.outbound.protection.outlook.com [40.107.96.60]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4FB12239E9E; Mon, 21 Jul 2025 20:05:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.96.60 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753128320; cv=fail; b=ivDwDQNUhpGo20fs/vQJSJ/ha5FS1gPdpileEpM8pJiOzEYttc7yPO+UZI10I+bdpFsTX7dZZYfWjMLz5w0rw9Ywi7QLc+62qSg/RSN19/mSSErfRF+XN1hJZHXhFWMRQKnAZ9Ex12v61FzD3h3C1qrEJQnm5OS7JG5q8ix1Q2o= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753128320; c=relaxed/simple; bh=//81EW72FbyHBeUSoqSeCTSDKJHXYxKWokLH6rFt7Cg=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=KRAXnKFcPwwxMv3yyHa12eNe4h2eFG1n996SDnICyxSdlkX9dy2NZkFEqEjT6u1A1vyzuFh9xHKbRwoAVQj5ESOHEf0BXEj1ycO7jYrMowSPOHygkCPhrYlzNdJemY4lZQ75LbBmis08XDwIcIHeCrf1rV5YqrXCEBiXytikQJ4= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=AE4ibYzC; arc=fail smtp.client-ip=40.107.96.60 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="AE4ibYzC" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=yzVK+wH4wB3w/QqN9ae/6M4VtMA3E2WEsIGYBnUbNe4R5vynpH01xvePmjyGWiBVHOvNHrKxrAC4RRtFxAZafjF17K88jmUZs0t9MdWXgyfJRaZDhg985yr+wyDXKvqquanwxA5Ze90ZD6tyheQoaHUvOsCBaNmh2zb6Zisi2/L7IaeV2Ef27L6gafihVj+02+2b5h+ArMkcniz15pvt8FJChOmFTLX2Q1Qa2WT0KQL+9Miy+Sak8nTCKGTHy5zZVIz5e4FoskUXn8Utfo/kEGBfSt60cFwbysM1Sz2l2SMKoUqJPoGJf/is/Vx0c2vypQkpMMfN58yuTvEUzgsUtA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=7wbMiWsmfGjUfhXCXATyJqAqZm+lcfL7JnN0xFiyQfw=; b=CSwuQJDhYXBMDX8Wecvb/h3XcNJRWdumAaXpxxUZMVWWSugXUu5G2N8Psdjz7K8TpKTezS80kfoaQHEB1a4lwBulAgszOi9/oPg5kJpZ4LUfd9zAu1ErtfLPLqKRfCP+AKqcFh/S2XTXgYaQZg/8XLzw93jvGZGqdU/0Vqei6lq20YcaaY43vsJWyNTkMAX8U839zm8LHVNwDYnqkABUo0lUn4rrCkQnnlPrDNidjWHDwgCI9tjT5+Mpj9hJXaLxbXgmU4qvIaL0jEUq1IxoO7ZNOvl8Sh3j7ucE0Ev0/1n/dwNiBVAcwRIiIeAyE5D5kGsXeQc/Z/O7xXe6wcKRUg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.118.233) smtp.rcpttodomain=kernel.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=7wbMiWsmfGjUfhXCXATyJqAqZm+lcfL7JnN0xFiyQfw=; b=AE4ibYzCXLQ6L5roaJjJSDHXO51TJWVq62u/F1RVqBwxtiERpBpRo/sLJW5TzL/CxETgA3YT/sSjAWuoVYEmu4VIvbEDqx3lc8dAidZltbS8VARKQoDxrBy9ad2FPP0rdphmg8kIY+jQd1qwVRtaZUBnEwKukjxeU1BCyvM+Zsv27Qiz/OMo5px2h5Y/IydFe8Xgn8AhPilRkA3g6TYIfOMtPa7XtrdGNrFvmIJZ/Ip0zXjaZDXp/lmvawQNcSDLjipyFPtWzqo3yrbF0fMxWMYdlWg8+gs2KHcLugR8gvzIjFLG2QGy4u6OJuPg9N+WGO9ZtkEjHMU1MGzWAJqtsA== Received: from BY3PR04CA0004.namprd04.prod.outlook.com (2603:10b6:a03:217::9) by LV2PR12MB5750.namprd12.prod.outlook.com (2603:10b6:408:17e::6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8943.30; Mon, 21 Jul 2025 20:05:14 +0000 Received: from SJ1PEPF00001CE4.namprd03.prod.outlook.com (2603:10b6:a03:217:cafe::f1) by BY3PR04CA0004.outlook.office365.com (2603:10b6:a03:217::9) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.8943.29 via Frontend Transport; Mon, 21 Jul 2025 20:05:11 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.118.233) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.118.233 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.118.233; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.118.233) by SJ1PEPF00001CE4.mail.protection.outlook.com (10.167.242.20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8964.20 via Frontend Transport; Mon, 21 Jul 2025 20:05:11 +0000 Received: from drhqmail201.nvidia.com (10.126.190.180) by mail.nvidia.com (10.127.129.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Mon, 21 Jul 2025 13:04:57 -0700 Received: from drhqmail202.nvidia.com (10.126.190.181) by drhqmail201.nvidia.com (10.126.190.180) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.14; Mon, 21 Jul 2025 13:04:57 -0700 Received: from Asurada-Nvidia.nvidia.com (10.127.8.13) by mail.nvidia.com (10.126.190.181) with Microsoft SMTP Server id 15.2.1544.14 via Frontend Transport; Mon, 21 Jul 2025 13:04:56 -0700 From: Nicolin Chen To: , CC: , , , , , Subject: [PATCH v3 2/2] iommu/arm-smmu-v3: Replace vsmmu_size/type with get_viommu_size Date: Mon, 21 Jul 2025 13:04:44 -0700 Message-ID: <20250721200444.1740461-3-nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250721200444.1740461-1-nicolinc@nvidia.com> References: <20250721200444.1740461-1-nicolinc@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00001CE4:EE_|LV2PR12MB5750:EE_ X-MS-Office365-Filtering-Correlation-Id: f96cc8f0-2a41-4174-798a-08ddc891e66e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|82310400026|1800799024|36860700013|7053199007; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?OG7FuAT++5NL4JRu3q41nYY2cqRJS2yotxdxcqVH7uYqtpAV02AioIPbF81C?= =?us-ascii?Q?tfI8OzOhauUF2/yUN9hr7g1XKKDJbCc7yw+Ktg+VRSzazhEmHGagjMp1vucx?= =?us-ascii?Q?PF8OcWtZMR3WKuJ9fbgo2G38q7K8PcVSXv0QmS062gleXfEp/BTlkGoiDaix?= =?us-ascii?Q?FM6Y4O0Sikw/s30S3r9nSJX/hlz0DTfCO9KNC8BLTZ3rtbNFVayBSS6fDLIK?= =?us-ascii?Q?koS/9q+pjRdaXtSehW882DYK+7XT6zSl0d/INuoCumbkXgjVxN0y8SVTHrUJ?= =?us-ascii?Q?ik6Gisp0GL9nJMPHxlzi/zDHSAb6Zq6X3yBAmwrFVdCy7ZwlLpuVhCt3bVnC?= =?us-ascii?Q?Gn55C9s9NEmNt54+i79Ze2W8Ymf7dyE8FqtaalcG3VEX4vcd0HHmMlA+yvPk?= =?us-ascii?Q?OtuGUnQIfHt9FNeniCn8hVLZ0JfI38FjDE7eiifZUcn9LSr5woPYdHCSQ9oa?= =?us-ascii?Q?DIGZ4B4taCVW6ZDTZYjr7EBJsfTZVNzQvA7U1KuHm69f1RUKXRaipnyLZi5R?= =?us-ascii?Q?Wc1a+kEOp+m7ORyXBXTeH75rqcGyD0VOLfAFumaj+v4FdO5jEDU02koYl4yb?= =?us-ascii?Q?7PqjsnHn5Sa5G6FGLaZc1VwzY97ys1RD1F40pTRTOqUVniA3jZiCHE4cqhIE?= =?us-ascii?Q?fYGLFacLticr4H+CvjiseOIOnOnriDxoLSKLhWyNAoxQUQW4w4PhsQodu+Sx?= =?us-ascii?Q?9/bHN4w+Z9PQmj2cNdja3DzG1UOX9dYyR45pRUm9rf9IFSO0vIWKNTNBpDWh?= =?us-ascii?Q?i14MJtp2qYlKoVdkCguAYRsXm7FHYClzJwDfhjp7AjsKTSVbS0VREeR9TyV/?= =?us-ascii?Q?j4glRxjsSv1CuAglh0MR3gM23wSfGw6OhMFbs0KExkSAVoTmvnyQeF71WFHW?= =?us-ascii?Q?zxCAbSVnMTNaT6qlUfXG8KYeCOi9+5uhkcptYbM4Q+0A6hJxQZcV1Yx6qWNK?= =?us-ascii?Q?+zZzi1bkI/mIW7gcqSdrr0/wsKqvT/4Xbl/C7JGRWpO6C0/nsOSxbWdYdmjB?= =?us-ascii?Q?8SfgkxswGVopJSs/xeDosQ/POJr7yXOBXSAhbu2j9/y2ByrRH0SLcC7aWQle?= =?us-ascii?Q?qA+2otjJeYWRjO0zt8e7CuRPwDS/8VxpIChQuFTCxyi4KSzXCnG2Fr/C4wRy?= =?us-ascii?Q?NJNkeCB1CTAX9HdikWxX8DAkGOC4rbhXt5UZlA3vtqxu4sy3zSP0MBa2zWK3?= =?us-ascii?Q?hpp6DF6LHHMwvleVyUIVKzIiKM4BPBdRPa6vjWRV7ygq3nSuXF2ShxBwvnF5?= =?us-ascii?Q?+5EkLNtVfb2buSYY1BHHlAnyb7Tio/VW2+fWcBPkJD+5CEf09HgRDErRUlY1?= =?us-ascii?Q?SJdSSSHehs0GtFdaqkQjtNFc3VNeZrWuDVu9DCFVrHD0+Vbh8IYkxxelIDEm?= =?us-ascii?Q?nYOSB9a+apRV9ppqptbp0/AxCpJIHMIPuGBdmGM/qdrV6hBwaY9rTMOnfSFx?= =?us-ascii?Q?eJE/uT3vw4mGofmy+SbXOlZvoAXGckKYwWf7U8r+aX9xJFtt6Zd0hY72xKWC?= =?us-ascii?Q?3RbJACl1fwjPyZkagv9/6T8yGQd3d0bf+wPq?= X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(82310400026)(1800799024)(36860700013)(7053199007);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Jul 2025 20:05:11.7941 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f96cc8f0-2a41-4174-798a-08ddc891e66e X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00001CE4.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV2PR12MB5750 Content-Type: text/plain; charset="utf-8" It's more flexible to have a get_viommu_size op. Replace static vsmmu_size and vsmmu_type with that. Suggested-by: Will Deacon Acked-by: Will Deacon Signed-off-by: Nicolin Chen Reviewed-by: Pranjal Shrivastava --- .../iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c | 8 ++------ drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 4 ++-- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 3 +-- drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c | 14 ++++++++++++-- 4 files changed, 17 insertions(+), 12 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c b/drivers/= iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c index c034d6c5468f..8cd8929bbfdf 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c @@ -423,10 +423,9 @@ size_t arm_smmu_get_viommu_size(struct device *dev, if (viommu_type =3D=3D IOMMU_VIOMMU_TYPE_ARM_SMMUV3) return VIOMMU_STRUCT_SIZE(struct arm_vsmmu, core); =20 - if (!smmu->impl_ops || !smmu->impl_ops->vsmmu_size || - viommu_type !=3D smmu->impl_ops->vsmmu_type) + if (!smmu->impl_ops || !smmu->impl_ops->get_viommu_size) return 0; - return smmu->impl_ops->vsmmu_size; + return smmu->impl_ops->get_viommu_size(viommu_type); } =20 int arm_vsmmu_init(struct iommufd_viommu *viommu, @@ -451,9 +450,6 @@ int arm_vsmmu_init(struct iommufd_viommu *viommu, return 0; } =20 - /* Unsupported type was rejected in arm_smmu_get_viommu_size() */ - if (WARN_ON(viommu->type !=3D smmu->impl_ops->vsmmu_type)) - return -EOPNOTSUPP; return smmu->impl_ops->vsmmu_init(vsmmu, user_data); } =20 diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index 9f4ad3705801..f56113107c8a 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -4716,8 +4716,8 @@ static struct arm_smmu_device *arm_smmu_impl_probe(st= ruct arm_smmu_device *smmu) =20 ops =3D new_smmu->impl_ops; if (ops) { - /* vsmmu_size and vsmmu_init ops must be paired */ - if (WARN_ON(!ops->vsmmu_size !=3D !ops->vsmmu_init)) { + /* get_viommu_size and vsmmu_init ops must be paired */ + if (WARN_ON(!ops->get_viommu_size !=3D !ops->vsmmu_init)) { ret =3D -EINVAL; goto err_remove; } diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.h index 3fa02c51df9f..e332f5ba2f8a 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -728,8 +728,7 @@ struct arm_smmu_impl_ops { */ void *(*hw_info)(struct arm_smmu_device *smmu, u32 *length, enum iommu_hw_info_type *type); - const size_t vsmmu_size; - const enum iommu_viommu_type vsmmu_type; + size_t (*get_viommu_size)(enum iommu_viommu_type viommu_type); int (*vsmmu_init)(struct arm_vsmmu *vsmmu, const struct iommu_user_data *user_data); }; diff --git a/drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c b/drivers/iommu= /arm/arm-smmu-v3/tegra241-cmdqv.c index 4c86eacd36b1..46005ed52bc2 100644 --- a/drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c +++ b/drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c @@ -832,6 +832,13 @@ static void *tegra241_cmdqv_hw_info(struct arm_smmu_de= vice *smmu, u32 *length, return info; } =20 +static size_t tegra241_cmdqv_get_vintf_size(enum iommu_viommu_type viommu_= type) +{ + if (viommu_type !=3D IOMMU_VIOMMU_TYPE_TEGRA241_CMDQV) + return 0; + return VIOMMU_STRUCT_SIZE(struct tegra241_vintf, vsmmu.core); +} + static struct arm_smmu_impl_ops tegra241_cmdqv_impl_ops =3D { /* For in-kernel use */ .get_secondary_cmdq =3D tegra241_cmdqv_get_cmdq, @@ -839,8 +846,7 @@ static struct arm_smmu_impl_ops tegra241_cmdqv_impl_ops= =3D { .device_remove =3D tegra241_cmdqv_remove, /* For user-space use */ .hw_info =3D tegra241_cmdqv_hw_info, - .vsmmu_size =3D VIOMMU_STRUCT_SIZE(struct tegra241_vintf, vsmmu.core), - .vsmmu_type =3D IOMMU_VIOMMU_TYPE_TEGRA241_CMDQV, + .get_viommu_size =3D tegra241_cmdqv_get_vintf_size, .vsmmu_init =3D tegra241_cmdqv_init_vintf_user, }; =20 @@ -1273,6 +1279,10 @@ tegra241_cmdqv_init_vintf_user(struct arm_vsmmu *vsm= mu, phys_addr_t page0_base; int ret; =20 + /* Unsupported type was rejected in tegra241_cmdqv_get_vintf_size() */ + if (WARN_ON(vsmmu->core.type !=3D IOMMU_VIOMMU_TYPE_TEGRA241_CMDQV)) + return -EOPNOTSUPP; + if (!user_data) return -EINVAL; =20 --=20 2.43.0