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charset="utf-8" Enhances code readability and future modifications within the new API. Move the code that handles the actual initialization of resources like clock and ICC paths to a separate function, making the probe function cleaner. Reviewed-by: Bryan O'Donoghue Signed-off-by: Praveen Talari --- v5 -> v6 - added reviewed-by tag v3 -> v4 - added version log after --- v1 -> v2 - updated subject description. - added a new line after function end --- drivers/tty/serial/qcom_geni_serial.c | 66 ++++++++++++++++----------- 1 file changed, 40 insertions(+), 26 deletions(-) diff --git a/drivers/tty/serial/qcom_geni_serial.c b/drivers/tty/serial/qco= m_geni_serial.c index 004f9a0d80f7..1e1c60d7aced 100644 --- a/drivers/tty/serial/qcom_geni_serial.c +++ b/drivers/tty/serial/qcom_geni_serial.c @@ -1619,6 +1619,43 @@ static struct uart_driver qcom_geni_uart_driver =3D { .nr =3D GENI_UART_PORTS, }; =20 +static int geni_serial_resource_init(struct qcom_geni_serial_port *port) +{ + int ret; + + port->se.clk =3D devm_clk_get(port->se.dev, "se"); + if (IS_ERR(port->se.clk)) { + ret =3D PTR_ERR(port->se.clk); + dev_err(port->se.dev, "Err getting SE Core clk %d\n", ret); + return ret; + } + + ret =3D geni_icc_get(&port->se, NULL); + if (ret) + return ret; + + port->se.icc_paths[GENI_TO_CORE].avg_bw =3D GENI_DEFAULT_BW; + port->se.icc_paths[CPU_TO_GENI].avg_bw =3D GENI_DEFAULT_BW; + + /* Set BW for register access */ + ret =3D geni_icc_set_bw(&port->se); + if (ret) + return ret; + + ret =3D devm_pm_opp_set_clkname(port->se.dev, "se"); + if (ret) + return ret; + + /* OPP table is optional */ + ret =3D devm_pm_opp_of_add_table(port->se.dev); + if (ret && ret !=3D -ENODEV) { + dev_err(port->se.dev, "invalid OPP table in device tree\n"); + return ret; + } + + return 0; +} + static void qcom_geni_serial_pm(struct uart_port *uport, unsigned int new_state, unsigned int old_state) { @@ -1739,12 +1776,10 @@ static int qcom_geni_serial_probe(struct platform_d= evice *pdev) port->dev_data =3D data; port->se.dev =3D &pdev->dev; port->se.wrapper =3D dev_get_drvdata(pdev->dev.parent); - port->se.clk =3D devm_clk_get(&pdev->dev, "se"); - if (IS_ERR(port->se.clk)) { - ret =3D PTR_ERR(port->se.clk); - dev_err(&pdev->dev, "Err getting SE Core clk %d\n", ret); + + ret =3D geni_serial_resource_init(port); + if (ret) return ret; - } =20 res =3D platform_get_resource(pdev, IORESOURCE_MEM, 0); if (!res) @@ -1764,17 +1799,6 @@ static int qcom_geni_serial_probe(struct platform_de= vice *pdev) return -ENOMEM; } =20 - ret =3D geni_icc_get(&port->se, NULL); - if (ret) - return ret; - port->se.icc_paths[GENI_TO_CORE].avg_bw =3D GENI_DEFAULT_BW; - port->se.icc_paths[CPU_TO_GENI].avg_bw =3D GENI_DEFAULT_BW; - - /* Set BW for register access */ - ret =3D geni_icc_set_bw(&port->se); - if (ret) - return ret; - port->name =3D devm_kasprintf(uport->dev, GFP_KERNEL, "qcom_geni_serial_%s%d", uart_console(uport) ? "console" : "uart", uport->line); @@ -1796,16 +1820,6 @@ static int qcom_geni_serial_probe(struct platform_de= vice *pdev) if (of_property_read_bool(pdev->dev.of_node, "cts-rts-swap")) port->cts_rts_swap =3D true; =20 - ret =3D devm_pm_opp_set_clkname(&pdev->dev, "se"); - if (ret) - return ret; - /* OPP table is optional */ - ret =3D devm_pm_opp_of_add_table(&pdev->dev); - if (ret && ret !=3D -ENODEV) { - dev_err(&pdev->dev, "invalid OPP table in device tree\n"); - return ret; - } - port->private_data.drv =3D drv; uport->private_data =3D &port->private_data; platform_set_drvdata(pdev, port); --=20 2.17.1