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charset="utf-8" From: Nikunj Kela SA8255p platform abstracts resources such as clocks, interconnect and GPIO pins configuration in Firmware. SCMI power and perf protocols are used to send request for resource configurations. Add DT bindings for the QUP GENI UART controller on sa8255p platform. The wakeup interrupt (IRQ) is treated as optional, as not all UART instances have a wakeup-capable interrupt routed via the PDC. Signed-off-by: Nikunj Kela Co-developed-by: Praveen Talari Signed-off-by: Praveen Talari Reviewed-by: Krzysztof Kozlowski --- v6 -> v7 From Krzysztof: - added minItems in interrupt-names v5 -> v6 - added description for interrupt-names - added wakeup irq as optional information in commit text and property description. - removed wake irq form example node. v4 -> v5 - added wake irq in example node v3 -> v4 - added version log after --- v2 -> v3 - dropped description for interrupt-names - rebased reg property order in required option v1 -> v2 - reorder sequence of tags in commit text - moved reg property after compatible field - added interrupt-names property --- .../serial/qcom,sa8255p-geni-uart.yaml | 69 +++++++++++++++++++ 1 file changed, 69 insertions(+) create mode 100644 Documentation/devicetree/bindings/serial/qcom,sa8255p-g= eni-uart.yaml diff --git a/Documentation/devicetree/bindings/serial/qcom,sa8255p-geni-uar= t.yaml b/Documentation/devicetree/bindings/serial/qcom,sa8255p-geni-uart.ya= ml new file mode 100644 index 000000000000..c8f01923cb25 --- /dev/null +++ b/Documentation/devicetree/bindings/serial/qcom,sa8255p-geni-uart.yaml @@ -0,0 +1,69 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/serial/qcom,sa8255p-geni-uart.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Geni based QUP UART interface + +maintainers: + - Praveen Talari + +allOf: + - $ref: /schemas/serial/serial.yaml# + +properties: + compatible: + enum: + - qcom,sa8255p-geni-uart + - qcom,sa8255p-geni-debug-uart + + reg: + maxItems: 1 + + interrupts: + minItems: 1 + items: + - description: UART core irq + - description: Wakeup irq (RX GPIO) + + interrupt-names: + description: + The UART interrupt and optionally the RX in-band wakeup interrupt + as not all UART instances have a wakeup-capable interrupt routed + via the PDC. + minItems: 1 + items: + - const: uart + - const: wakeup + + power-domains: + minItems: 2 + maxItems: 2 + + power-domain-names: + items: + - const: power + - const: perf + +required: + - compatible + - reg + - interrupts + - power-domains + - power-domain-names + +unevaluatedProperties: false + +examples: + - | + #include + + serial@990000 { + compatible =3D "qcom,sa8255p-geni-uart"; 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charset="utf-8" From: Nikunj Kela SA8255p platform abstracts resources such as clocks, interconnect configuration in Firmware. Add DT bindings for the QUP Wrapper on sa8255p platform. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Nikunj Kela Co-developed-by: Praveen Talari Signed-off-by: Praveen Talari --- v5 -> v6 - added Reviewed-by tag in commit v3 -> v4 - reordered required: after properties and patternproperties - added version log after --- v2 -> v3 - reordered required option v1 -> v2 - reorder sequence of tags in commit text - resolved waring errors while encountered in dt binding and dtb check. --- .../soc/qcom/qcom,sa8255p-geni-se-qup.yaml | 107 ++++++++++++++++++ 1 file changed, 107 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/qcom/qcom,sa8255p= -geni-se-qup.yaml diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,sa8255p-geni-s= e-qup.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,sa8255p-geni-s= e-qup.yaml new file mode 100644 index 000000000000..352af3426d34 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,sa8255p-geni-se-qup.y= aml @@ -0,0 +1,107 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/qcom/qcom,sa8255p-geni-se-qup.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: GENI Serial Engine QUP Wrapper Controller + +maintainers: + - Praveen Talari + +description: + Generic Interface (GENI) based Qualcomm Universal Peripheral (QUP) wrapp= er + is a programmable module for supporting a wide range of serial interfaces + like UART, SPI, I2C, I3C, etc. A single QUP module can provide up to 8 S= erial + Interfaces, using its internal Serial Engines. The GENI Serial Engine QUP + Wrapper controller is modeled as a node with zero or more child nodes ea= ch + representing a serial engine. + +properties: + compatible: + const: qcom,sa8255p-geni-se-qup + + reg: + description: QUP wrapper common register address and length. + maxItems: 1 + + "#address-cells": + const: 2 + + "#size-cells": + const: 2 + + ranges: true + + iommus: + maxItems: 1 + + dma-coherent: true + +patternProperties: + "spi@[0-9a-f]+$": + type: object + description: GENI serial engine based SPI controller. SPI in master mo= de + supports up to 50MHz, up to four chip selects, programmab= le + data path from 4 bits to 32 bits and numerous protocol + variants. + additionalProperties: true + + properties: + compatible: + const: qcom,sa8255p-geni-spi + + "i2c@[0-9a-f]+$": + type: object + description: GENI serial engine based I2C controller. + additionalProperties: true + + properties: + compatible: + const: qcom,sa8255p-geni-i2c + + "serial@[0-9a-f]+$": + type: object + description: GENI Serial Engine based UART Controller. + additionalProperties: true + + properties: + compatible: + enum: + - qcom,sa8255p-geni-uart + - qcom,sa8255p-geni-debug-uart + +required: + - compatible + - reg + - "#address-cells" + - "#size-cells" + - ranges + +additionalProperties: false + +examples: + - | + #include + + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + + geniqup@9c0000 { + compatible =3D "qcom,sa8255p-geni-se-qup"; + reg =3D <0 0x9c0000 0 0x6000>; + #address-cells =3D <2>; + #size-cells =3D <2>; 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Mon, 21 Jul 2025 17:46:17 GMT Received: from hu-ptalari-hyd.qualcomm.com (10.80.80.8) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Mon, 21 Jul 2025 10:46:11 -0700 From: Praveen Talari To: Greg Kroah-Hartman , Jiri Slaby , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , "Praveen Talari" , , , , , , CC: , , , , , , Subject: [PATCH v7 3/8] soc: qcom: geni-se: Enable QUPs on SA8255p Qualcomm platforms Date: Mon, 21 Jul 2025 23:15:27 +0530 Message-ID: <20250721174532.14022-4-quic_ptalari@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20250721174532.14022-1-quic_ptalari@quicinc.com> References: <20250721174532.14022-1-quic_ptalari@quicinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Authority-Analysis: v=2.4 cv=CZ4I5Krl c=1 sm=1 tr=0 ts=687e7cea cx=c_pps a=JYp8KDb2vCoCEuGobkYCKw==:117 a=JYp8KDb2vCoCEuGobkYCKw==:17 a=GEpy-HfZoHoA:10 a=Wb1JkmetP80A:10 a=COk6AnOGAAAA:8 a=ZThKv1m0n57AZib2rGMA:9 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-ORIG-GUID: 0273X1JvPV5SmbZ63bGYKUmS1brVkYtb X-Proofpoint-GUID: 0273X1JvPV5SmbZ63bGYKUmS1brVkYtb X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzIxMDE1MSBTYWx0ZWRfXxt4wCjwARTlR 2pP/0R8lMRvfD6iEbEcoCbU4xCnRlMGHlRzcglb8EHETWU8CdETA8B3TzD3G5AmuzXQ1k69Cq7j P48Uo/tp+OrhnIiHatHgFLMz4vfJA8Avcq6dOE+NNiuiL6MvOYURiRPgaNkst5waTeE92F5NkGD aLeVZgvrrU7VDE0OVuk9wJPQc3WfYKJ9haKSgqjZnyP6Ar7iDkY9sZy5qjrVdxCNc2lIYujv1Jf 12AtSAGc7kzXl0RHEMWaP6QUP7Z7BayRklO4zqaKFxSdlGb/aQdpBPP4JhSkWhmMrh5Ny2bKWRo J96cOMgo7GXrEYJihjdJe5LXzqDSgFb+5C6hlKdNNQRGIDepc0ukaF4powd1zVs7PJlLHrUjIJu U3cMvUI0cyRJQ0jGrKkPhbDy4AJ0hrEvC3n9NFRlRawHUTOWhM5HKRQ5cyb+nDmqkVB2AQhi X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-21_05,2025-07-21_02,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 suspectscore=0 mlxlogscore=999 impostorscore=0 clxscore=1015 mlxscore=0 lowpriorityscore=0 phishscore=0 adultscore=0 bulkscore=0 spamscore=0 malwarescore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507210151 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" On the sa8255p platform, resources such as clocks,interconnects and TLMM (GPIO) configurations are managed by firmware. Use the `num_clks` field in platform data to distinguish whether resource control is performed by firmware or directly by the driver in linux. Signed-off-by: Praveen Talari --- v6 -> v7 From Bjorn: - removed resources_init() callback function from platform data - removed geni_se_resource_init() and just add the additional expression to the condition - added sa8255p_qup_desc =3D {}; - updated commit text based on code changes v5 -> v6 - replaced dev_err with dev_err_probe - added a check for desc->num_clks with MAX_CLKS, an error if the specified num_clks in descriptor exceeds defined MAX_CLKS. - removed min_t which is not necessary. - renamed callback function names to resources_init. - resolved kernel bot warning error by documenting function pointer in geni_se_desc structure. v3 -> v4 - declared an empty struct for sa8255p and added check as num clks. - Added version log after --- v1 -> v2 - changed datatype of i from int to unsigned int as per comment. --- drivers/soc/qcom/qcom-geni-se.c | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/drivers/soc/qcom/qcom-geni-se.c b/drivers/soc/qcom/qcom-geni-s= e.c index 4cb959106efa..3c3b796333a6 100644 --- a/drivers/soc/qcom/qcom-geni-se.c +++ b/drivers/soc/qcom/qcom-geni-se.c @@ -895,6 +895,7 @@ static int geni_se_probe(struct platform_device *pdev) { struct device *dev =3D &pdev->dev; struct geni_wrapper *wrapper; + const struct geni_se_desc *desc; int ret; =20 wrapper =3D devm_kzalloc(dev, sizeof(*wrapper), GFP_KERNEL); @@ -906,13 +907,10 @@ static int geni_se_probe(struct platform_device *pdev) if (IS_ERR(wrapper->base)) return PTR_ERR(wrapper->base); =20 - if (!has_acpi_companion(&pdev->dev)) { - const struct geni_se_desc *desc; - int i; + desc =3D device_get_match_data(&pdev->dev); =20 - desc =3D device_get_match_data(&pdev->dev); - if (!desc) - return -EINVAL; + if (!has_acpi_companion(&pdev->dev) && desc->num_clks) { + int i; =20 wrapper->num_clks =3D min_t(unsigned int, desc->num_clks, MAX_CLKS); =20 @@ -953,6 +951,8 @@ static const struct geni_se_desc qup_desc =3D { .num_clks =3D ARRAY_SIZE(qup_clks), }; =20 +static const struct geni_se_desc sa8255p_qup_desc =3D {}; + static const char * const i2c_master_hub_clks[] =3D { "s-ahb", }; @@ -965,6 +965,7 @@ static const struct geni_se_desc i2c_master_hub_desc = =3D { static const struct of_device_id geni_se_dt_match[] =3D { { .compatible =3D "qcom,geni-se-qup", .data =3D &qup_desc }, { .compatible =3D "qcom,geni-se-i2c-master-hub", .data =3D &i2c_master_hu= b_desc }, + { .compatible =3D "qcom,sa8255p-geni-se-qup", .data =3D &sa8255p_qup_desc= }, {} }; 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charset="utf-8" Enhances code readability and future modifications within the new API. Move the code that handles the actual initialization of resources like clock and ICC paths to a separate function, making the probe function cleaner. Reviewed-by: Bryan O'Donoghue Signed-off-by: Praveen Talari --- v5 -> v6 - added reviewed-by tag v3 -> v4 - added version log after --- v1 -> v2 - updated subject description. - added a new line after function end --- drivers/tty/serial/qcom_geni_serial.c | 66 ++++++++++++++++----------- 1 file changed, 40 insertions(+), 26 deletions(-) diff --git a/drivers/tty/serial/qcom_geni_serial.c b/drivers/tty/serial/qco= m_geni_serial.c index 004f9a0d80f7..1e1c60d7aced 100644 --- a/drivers/tty/serial/qcom_geni_serial.c +++ b/drivers/tty/serial/qcom_geni_serial.c @@ -1619,6 +1619,43 @@ static struct uart_driver qcom_geni_uart_driver =3D { .nr =3D GENI_UART_PORTS, }; =20 +static int geni_serial_resource_init(struct qcom_geni_serial_port *port) +{ + int ret; + + port->se.clk =3D devm_clk_get(port->se.dev, "se"); + if (IS_ERR(port->se.clk)) { + ret =3D PTR_ERR(port->se.clk); + dev_err(port->se.dev, "Err getting SE Core clk %d\n", ret); + return ret; + } + + ret =3D geni_icc_get(&port->se, NULL); + if (ret) + return ret; + + port->se.icc_paths[GENI_TO_CORE].avg_bw =3D GENI_DEFAULT_BW; + port->se.icc_paths[CPU_TO_GENI].avg_bw =3D GENI_DEFAULT_BW; + + /* Set BW for register access */ + ret =3D geni_icc_set_bw(&port->se); + if (ret) + return ret; + + ret =3D devm_pm_opp_set_clkname(port->se.dev, "se"); + if (ret) + return ret; + + /* OPP table is optional */ + ret =3D devm_pm_opp_of_add_table(port->se.dev); + if (ret && ret !=3D -ENODEV) { + dev_err(port->se.dev, "invalid OPP table in device tree\n"); + return ret; + } + + return 0; +} + static void qcom_geni_serial_pm(struct uart_port *uport, unsigned int new_state, unsigned int old_state) { @@ -1739,12 +1776,10 @@ static int qcom_geni_serial_probe(struct platform_d= evice *pdev) port->dev_data =3D data; port->se.dev =3D &pdev->dev; port->se.wrapper =3D dev_get_drvdata(pdev->dev.parent); - port->se.clk =3D devm_clk_get(&pdev->dev, "se"); - if (IS_ERR(port->se.clk)) { - ret =3D PTR_ERR(port->se.clk); - dev_err(&pdev->dev, "Err getting SE Core clk %d\n", ret); + + ret =3D geni_serial_resource_init(port); + if (ret) return ret; - } =20 res =3D platform_get_resource(pdev, IORESOURCE_MEM, 0); if (!res) @@ -1764,17 +1799,6 @@ static int qcom_geni_serial_probe(struct platform_de= vice *pdev) return -ENOMEM; } =20 - ret =3D geni_icc_get(&port->se, NULL); - if (ret) - return ret; - port->se.icc_paths[GENI_TO_CORE].avg_bw =3D GENI_DEFAULT_BW; - port->se.icc_paths[CPU_TO_GENI].avg_bw =3D GENI_DEFAULT_BW; - - /* Set BW for register access */ - ret =3D geni_icc_set_bw(&port->se); - if (ret) - return ret; - port->name =3D devm_kasprintf(uport->dev, GFP_KERNEL, "qcom_geni_serial_%s%d", uart_console(uport) ? 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charset="utf-8" Supports use in PM system/runtime frameworks, helping to distinguish new resource control mechanisms and facilitate future modifications within the new API. The code that handles the actual enable or disable of resources like clock and ICC paths to a separate function (geni_serial_resources_on() and geni_serial_resources_off()) which enhances code readability. Introduced minor return checks in newly added function APIs to enhance error detection and prevent silent failures. Signed-off-by: Praveen Talari --- v5 -> v6 - updated commit text for checks in newly added function APIs - fiexd alignment - reordered newly added function API definations. v3 -> v4 - added version log after --- v1 -> v2 - returned 0 instead of ret variable --- drivers/tty/serial/qcom_geni_serial.c | 54 +++++++++++++++++++++------ 1 file changed, 42 insertions(+), 12 deletions(-) diff --git a/drivers/tty/serial/qcom_geni_serial.c b/drivers/tty/serial/qco= m_geni_serial.c index 1e1c60d7aced..45d9735247f8 100644 --- a/drivers/tty/serial/qcom_geni_serial.c +++ b/drivers/tty/serial/qcom_geni_serial.c @@ -1619,6 +1619,42 @@ static struct uart_driver qcom_geni_uart_driver =3D { .nr =3D GENI_UART_PORTS, }; =20 +static int geni_serial_resources_on(struct uart_port *uport) +{ + struct qcom_geni_serial_port *port =3D to_dev_port(uport); + int ret; + + ret =3D geni_icc_enable(&port->se); + if (ret) + return ret; + + ret =3D geni_se_resources_on(&port->se); + if (ret) { + geni_icc_disable(&port->se); + return ret; + } + + if (port->clk_rate) + dev_pm_opp_set_rate(uport->dev, port->clk_rate); + + return 0; +} + +static int geni_serial_resources_off(struct uart_port *uport) +{ + struct qcom_geni_serial_port *port =3D to_dev_port(uport); + int ret; + + dev_pm_opp_set_rate(uport->dev, 0); + ret =3D geni_se_resources_off(&port->se); + if (ret) + return ret; + + geni_icc_disable(&port->se); + + return 0; +} + static int geni_serial_resource_init(struct qcom_geni_serial_port *port) { int ret; @@ -1659,23 +1695,17 @@ static int geni_serial_resource_init(struct qcom_ge= ni_serial_port *port) static void qcom_geni_serial_pm(struct uart_port *uport, unsigned int new_state, unsigned int old_state) { - struct qcom_geni_serial_port *port =3D to_dev_port(uport); =20 /* If we've never been called, treat it as off */ if (old_state =3D=3D UART_PM_STATE_UNDEFINED) old_state =3D UART_PM_STATE_OFF; =20 - if (new_state =3D=3D UART_PM_STATE_ON && old_state =3D=3D UART_PM_STATE_O= FF) { - geni_icc_enable(&port->se); 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charset="utf-8" Facilitates future modifications within the new function, leading to better readability and maintainability of the code. Move the code that handles the actual logic of clock-rate calculations to a separate function geni_serial_set_rate() which enhances code readability. Signed-off-by: Praveen Talari --- v6 -> v7 From Bjorn: - removed error log from qcom_geni_serial_set_termios(). v5 -> v6 - used "unsigned int" instead of "unsigned long" in newly added API function params to avoid the format specifier warnings. v3 -> v4 - added version log after --- v1 -> v2 - resolved build warnings for datatype format specifiers - removed double spaces in log --- drivers/tty/serial/qcom_geni_serial.c | 52 ++++++++++++++++----------- 1 file changed, 32 insertions(+), 20 deletions(-) diff --git a/drivers/tty/serial/qcom_geni_serial.c b/drivers/tty/serial/qco= m_geni_serial.c index 45d9735247f8..81f385d900d0 100644 --- a/drivers/tty/serial/qcom_geni_serial.c +++ b/drivers/tty/serial/qcom_geni_serial.c @@ -1314,27 +1314,14 @@ static unsigned long get_clk_div_rate(struct clk *c= lk, unsigned int baud, return ser_clk; } =20 -static void qcom_geni_serial_set_termios(struct uart_port *uport, - struct ktermios *termios, - const struct ktermios *old) +static int geni_serial_set_rate(struct uart_port *uport, unsigned int baud) { - unsigned int baud; - u32 bits_per_char; - u32 tx_trans_cfg; - u32 tx_parity_cfg; - u32 rx_trans_cfg; - u32 rx_parity_cfg; - u32 stop_bit_len; - unsigned int clk_div; - u32 ser_clk_cfg; struct qcom_geni_serial_port *port =3D to_dev_port(uport); unsigned long clk_rate; - u32 ver, sampling_rate; unsigned int avg_bw_core; - unsigned long timeout; - - /* baud rate */ - baud =3D uart_get_baud_rate(uport, termios, old, 300, 8000000); + unsigned int clk_div; + u32 ver, sampling_rate; + u32 ser_clk_cfg; =20 sampling_rate =3D UART_OVERSAMPLING; /* Sampling rate is halved for IP versions >=3D 2.5 */ @@ -1348,7 +1335,7 @@ static void qcom_geni_serial_set_termios(struct uart_= port *uport, dev_err(port->se.dev, "Couldn't find suitable clock rate for %u\n", baud * sampling_rate); - return; + return -EINVAL; } =20 dev_dbg(port->se.dev, "desired_rate =3D %u, clk_rate =3D %lu, clk_div =3D= %u\n", @@ -1370,6 +1357,33 @@ static void qcom_geni_serial_set_termios(struct uart= _port *uport, port->se.icc_paths[CPU_TO_GENI].avg_bw =3D Bps_to_icc(baud); geni_icc_set_bw(&port->se); =20 + writel(ser_clk_cfg, uport->membase + GENI_SER_M_CLK_CFG); + writel(ser_clk_cfg, uport->membase + GENI_SER_S_CLK_CFG); + return 0; +} + +static void qcom_geni_serial_set_termios(struct uart_port *uport, + struct ktermios *termios, + const struct ktermios *old) +{ + struct qcom_geni_serial_port *port =3D to_dev_port(uport); + unsigned int baud; + unsigned long timeout; + u32 bits_per_char; + u32 tx_trans_cfg; + u32 tx_parity_cfg; + u32 rx_trans_cfg; + u32 rx_parity_cfg; + u32 stop_bit_len; + int ret =3D 0; + + /* baud rate */ + baud =3D uart_get_baud_rate(uport, termios, old, 300, 8000000); + + ret =3D geni_serial_set_rate(uport, baud); + if (ret) + return; + /* parity */ tx_trans_cfg =3D readl(uport->membase + SE_UART_TX_TRANS_CFG); tx_parity_cfg =3D readl(uport->membase + SE_UART_TX_PARITY_CFG); @@ -1437,8 +1451,6 @@ static void qcom_geni_serial_set_termios(struct uart_= port *uport, writel(bits_per_char, uport->membase + SE_UART_TX_WORD_LEN); writel(bits_per_char, uport->membase + SE_UART_RX_WORD_LEN); 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charset="utf-8" The GENI serial driver currently handles power resource management through calls to the statically defined geni_serial_resources_on() and geni_serial_resources_off() functions. This approach reduces modularity and limits support for platforms with diverse power management mechanisms, including resource managed by firmware. Improve modularity and enable better integration with platform-specific power management, introduce support for runtime PM. Use pm_runtime_resume_and_get() and pm_runtime_put_sync() within the qcom_geni_serial_pm() callback to control resource power state transitions based on UART power state changes. Reviewed-by: Bryan O'Donoghue Signed-off-by: Praveen Talari --- v6 -> v7 From Bjorn: - used devm_pm_runtime_enable() instead of pm_runtime_enable() - updated commit text. v5 -> v6 - added reviewed-by tag in commit - added __maybe_unused to PM callback functions to avoid warnings of defined but not used --- drivers/tty/serial/qcom_geni_serial.c | 24 ++++++++++++++++++++++-- 1 file changed, 22 insertions(+), 2 deletions(-) diff --git a/drivers/tty/serial/qcom_geni_serial.c b/drivers/tty/serial/qco= m_geni_serial.c index 81f385d900d0..aa08de659e34 100644 --- a/drivers/tty/serial/qcom_geni_serial.c +++ b/drivers/tty/serial/qcom_geni_serial.c @@ -1713,10 +1713,10 @@ static void qcom_geni_serial_pm(struct uart_port *u= port, old_state =3D UART_PM_STATE_OFF; =20 if (new_state =3D=3D UART_PM_STATE_ON && old_state =3D=3D UART_PM_STATE_O= FF) - geni_serial_resources_on(uport); + pm_runtime_resume_and_get(uport->dev); else if (new_state =3D=3D UART_PM_STATE_OFF && old_state =3D=3D UART_PM_STATE_ON) - geni_serial_resources_off(uport); + pm_runtime_put_sync(uport->dev); =20 } =20 @@ -1878,6 +1878,8 @@ static int qcom_geni_serial_probe(struct platform_dev= ice *pdev) if (ret) return ret; =20 + devm_pm_runtime_enable(port->se.dev); + ret =3D uart_add_one_port(drv, uport); if (ret) return ret; @@ -1909,6 +1911,22 @@ static void qcom_geni_serial_remove(struct platform_= device *pdev) uart_remove_one_port(drv, &port->uport); } =20 +static int __maybe_unused qcom_geni_serial_runtime_suspend(struct device *= dev) +{ + struct qcom_geni_serial_port *port =3D dev_get_drvdata(dev); + struct uart_port *uport =3D &port->uport; + + return geni_serial_resources_off(uport); +} + +static int __maybe_unused qcom_geni_serial_runtime_resume(struct device *d= ev) +{ + struct qcom_geni_serial_port *port =3D dev_get_drvdata(dev); + struct uart_port *uport =3D &port->uport; + + return geni_serial_resources_on(uport); +} + static int qcom_geni_serial_suspend(struct device *dev) { struct qcom_geni_serial_port *port =3D dev_get_drvdata(dev); @@ -1952,6 +1970,8 @@ static const struct qcom_geni_device_data qcom_geni_u= art_data =3D { }; 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Mon, 21 Jul 2025 17:46:50 GMT Received: from hu-ptalari-hyd.qualcomm.com (10.80.80.8) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Mon, 21 Jul 2025 10:46:45 -0700 From: Praveen Talari To: Greg Kroah-Hartman , Jiri Slaby , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , "Praveen Talari" , , , , , , CC: , , , , , , Subject: [PATCH v7 8/8] serial: qcom-geni: Enable Serial on SA8255p Qualcomm platforms Date: Mon, 21 Jul 2025 23:15:32 +0530 Message-ID: <20250721174532.14022-9-quic_ptalari@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20250721174532.14022-1-quic_ptalari@quicinc.com> References: <20250721174532.14022-1-quic_ptalari@quicinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Authority-Analysis: v=2.4 cv=CZ4I5Krl c=1 sm=1 tr=0 ts=687e7d0b cx=c_pps a=JYp8KDb2vCoCEuGobkYCKw==:117 a=JYp8KDb2vCoCEuGobkYCKw==:17 a=GEpy-HfZoHoA:10 a=Wb1JkmetP80A:10 a=KKAkSRfTAAAA:8 a=COk6AnOGAAAA:8 a=TwmaSWGEdcevDZ0QsRoA:9 a=cvBusfyB2V15izCimMoJ:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-ORIG-GUID: BbarhGipFW--8n6Xbd7mdaW28vaBf2Kg X-Proofpoint-GUID: BbarhGipFW--8n6Xbd7mdaW28vaBf2Kg X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzIxMDE1MSBTYWx0ZWRfXxiAqft7yOrhc zyvpkNB45vZrSSGiHjZ1xslABGwSi38fcD+grHfiKaNQbLFxNrkFc9g6vVNHlShfP/BYB0Ws5mH WyayeZksycihz3TTZeSN/gKxLbb8QnBtG32kAB3JvHSndnsQrtaIgPK0lWPFblU0pvXKlpMranW HHs1aMzC8c51Y2w8nZr2WSFOARU3yGeL4myfFzKpOPpHCIvlJ1pRM/Lj6JVLs9b353oJeIiwbUJ 8fQCu8u7sXNN4fnLY1lB/IEPAOzGjqYf/3dFdXjoVegxfv49ONIWOYr3DAVlbz6QPray7gX1lhu GO3b5HzyG/5w+rnYdPiI4/yn5ccoiVcqktiP+JJ524UYHQdP+2VkhVrR42QhP0SXZQ7afz7lfJ6 KrL1JX6aOy6DTZGXm75tA1tveGh/GCBU9GZLM+VY1eDTevy5gXDwUzNGlI6pu5sChbnE7Rlw X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-21_05,2025-07-21_02,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 suspectscore=0 mlxlogscore=999 impostorscore=0 clxscore=1015 mlxscore=0 lowpriorityscore=0 phishscore=0 adultscore=0 bulkscore=0 spamscore=0 malwarescore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507210151 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The Qualcomm automotive SA8255p SoC relies on firmware to configure platform resources, including clocks, interconnects and TLMM. The driver requests resources operations over SCMI using power and performance protocols. The SCMI power protocol enables or disables resources like clocks, interconnect paths, and TLMM (GPIOs) using runtime PM framework APIs, such as resume/suspend, to control power states(on/off). The SCMI performance protocol manages UART baud rates, with each baud rate represented by a performance level. The driver uses the dev_pm_opp_set_level() API to request the desired baud rate by specifying the performance level. Reviewed-by: Bryan O'Donoghue Signed-off-by: Praveen Talari --- v5 -> v6 - added reviewed-by tag in commit - used "unsigned int" instead of "unsigned long" in set_rate callback and geni_serial_set_level to avoid build warnings. v3 -> v4 - renamed callback function names to resources_init, set_rate and power_state --- drivers/tty/serial/qcom_geni_serial.c | 156 +++++++++++++++++++++++--- 1 file changed, 140 insertions(+), 16 deletions(-) diff --git a/drivers/tty/serial/qcom_geni_serial.c b/drivers/tty/serial/qco= m_geni_serial.c index aa08de659e34..32ec632fd080 100644 --- a/drivers/tty/serial/qcom_geni_serial.c +++ b/drivers/tty/serial/qcom_geni_serial.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -99,10 +100,16 @@ #define DMA_RX_BUF_SIZE 2048 =20 static DEFINE_IDA(port_ida); +#define DOMAIN_IDX_POWER 0 +#define DOMAIN_IDX_PERF 1 =20 struct qcom_geni_device_data { bool console; enum geni_se_xfer_mode mode; + struct dev_pm_domain_attach_data pd_data; + int (*resources_init)(struct uart_port *uport); + int (*set_rate)(struct uart_port *uport, unsigned int baud); + int (*power_state)(struct uart_port *uport, bool state); }; =20 struct qcom_geni_private_data { @@ -140,6 +147,7 @@ struct qcom_geni_serial_port { =20 struct qcom_geni_private_data private_data; const struct qcom_geni_device_data *dev_data; + struct dev_pm_domain_list *pd_list; }; =20 static const struct uart_ops qcom_geni_console_pops; @@ -1362,6 +1370,42 @@ static int geni_serial_set_rate(struct uart_port *up= ort, unsigned int baud) return 0; } =20 +static int geni_serial_set_level(struct uart_port *uport, unsigned int bau= d) +{ + struct qcom_geni_serial_port *port =3D to_dev_port(uport); + struct device *perf_dev =3D port->pd_list->pd_devs[DOMAIN_IDX_PERF]; + + /* + * The performance protocol sets UART communication + * speeds by selecting different performance levels + * through the OPP framework. + * + * Supported perf levels for baudrates in firmware are below + * +---------------------+--------------------+ + * | Perf level value | Baudrate values | + * +---------------------+--------------------+ + * | 300 | 300 | + * | 1200 | 1200 | + * | 2400 | 2400 | + * | 4800 | 4800 | + * | 9600 | 9600 | + * | 19200 | 19200 | + * | 38400 | 38400 | + * | 57600 | 57600 | + * | 115200 | 115200 | + * | 230400 | 230400 | + * | 460800 | 460800 | + * | 921600 | 921600 | + * | 2000000 | 2000000 | + * | 3000000 | 3000000 | + * | 3200000 | 3200000 | + * | 4000000 | 4000000 | + * +---------------------+--------------------+ + */ + + return dev_pm_opp_set_level(perf_dev, baud); +} + static void qcom_geni_serial_set_termios(struct uart_port *uport, struct ktermios *termios, const struct ktermios *old) @@ -1380,7 +1424,7 @@ static void qcom_geni_serial_set_termios(struct uart_= port *uport, /* baud rate */ baud =3D uart_get_baud_rate(uport, termios, old, 300, 8000000); =20 - ret =3D geni_serial_set_rate(uport, baud); + ret =3D port->dev_data->set_rate(uport, baud); if (ret) return; =20 @@ -1667,8 +1711,27 @@ static int geni_serial_resources_off(struct uart_por= t *uport) return 0; } =20 -static int geni_serial_resource_init(struct qcom_geni_serial_port *port) +static int geni_serial_resource_state(struct uart_port *uport, bool power_= on) +{ + return power_on ? geni_serial_resources_on(uport) : geni_serial_resources= _off(uport); +} + +static int geni_serial_pwr_init(struct uart_port *uport) +{ + struct qcom_geni_serial_port *port =3D to_dev_port(uport); + int ret; + + ret =3D dev_pm_domain_attach_list(port->se.dev, + &port->dev_data->pd_data, &port->pd_list); + if (ret <=3D 0) + return -EINVAL; + + return 0; +} + +static int geni_serial_resource_init(struct uart_port *uport) { + struct qcom_geni_serial_port *port =3D to_dev_port(uport); int ret; =20 port->se.clk =3D devm_clk_get(port->se.dev, "se"); @@ -1819,13 +1882,16 @@ static int qcom_geni_serial_probe(struct platform_d= evice *pdev) port->se.dev =3D &pdev->dev; port->se.wrapper =3D dev_get_drvdata(pdev->dev.parent); =20 - ret =3D geni_serial_resource_init(port); + ret =3D port->dev_data->resources_init(uport); if (ret) return ret; =20 res =3D platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (!res) - return -EINVAL; + if (!res) { + ret =3D -EINVAL; + goto error; + } + uport->mapbase =3D res->start; =20 uport->rs485_config =3D qcom_geni_rs485_config; @@ -1837,19 +1903,26 @@ static int qcom_geni_serial_probe(struct platform_d= evice *pdev) if (!data->console) { port->rx_buf =3D devm_kzalloc(uport->dev, DMA_RX_BUF_SIZE, GFP_KERNEL); - if (!port->rx_buf) - return -ENOMEM; + if (!port->rx_buf) { + ret =3D -ENOMEM; + goto error; + } } =20 port->name =3D devm_kasprintf(uport->dev, GFP_KERNEL, "qcom_geni_serial_%s%d", uart_console(uport) ? "console" : "uart", uport->line); - if (!port->name) - return -ENOMEM; + if (!port->name) { + ret =3D -ENOMEM; + goto error; + } =20 irq =3D platform_get_irq(pdev, 0); - if (irq < 0) - return irq; + if (irq < 0) { + ret =3D irq; + goto error; + } + uport->irq =3D irq; uport->has_sysrq =3D IS_ENABLED(CONFIG_SERIAL_QCOM_GENI_CONSOLE); =20 @@ -1871,7 +1944,7 @@ static int qcom_geni_serial_probe(struct platform_dev= ice *pdev) IRQF_TRIGGER_HIGH, port->name, uport); if (ret) { dev_err(uport->dev, "Failed to get IRQ ret %d\n", ret); - return ret; + goto error; } =20 ret =3D uart_get_rs485_mode(uport); @@ -1882,7 +1955,7 @@ static int qcom_geni_serial_probe(struct platform_dev= ice *pdev) =20 ret =3D uart_add_one_port(drv, uport); if (ret) - return ret; + goto error; =20 if (port->wakeup_irq > 0) { device_init_wakeup(&pdev->dev, true); @@ -1892,11 +1965,15 @@ static int qcom_geni_serial_probe(struct platform_d= evice *pdev) device_init_wakeup(&pdev->dev, false); ida_free(&port_ida, uport->line); uart_remove_one_port(drv, uport); - return ret; + goto error; } } =20 return 0; + +error: + dev_pm_domain_detach_list(port->pd_list); + return ret; } =20 static void qcom_geni_serial_remove(struct platform_device *pdev) @@ -1909,22 +1986,31 @@ static void qcom_geni_serial_remove(struct platform= _device *pdev) device_init_wakeup(&pdev->dev, false); ida_free(&port_ida, uport->line); uart_remove_one_port(drv, &port->uport); + dev_pm_domain_detach_list(port->pd_list); } =20 static int __maybe_unused qcom_geni_serial_runtime_suspend(struct device *= dev) { struct qcom_geni_serial_port *port =3D dev_get_drvdata(dev); struct uart_port *uport =3D &port->uport; + int ret =3D 0; + + if (port->dev_data->power_state) + ret =3D port->dev_data->power_state(uport, false); =20 - return geni_serial_resources_off(uport); + return ret; } =20 static int __maybe_unused qcom_geni_serial_runtime_resume(struct device *d= ev) { struct qcom_geni_serial_port *port =3D dev_get_drvdata(dev); struct uart_port *uport =3D &port->uport; + int ret =3D 0; =20 - return geni_serial_resources_on(uport); + if (port->dev_data->power_state) + ret =3D port->dev_data->power_state(uport, true); + + return ret; } =20 static int qcom_geni_serial_suspend(struct device *dev) @@ -1962,11 +2048,41 @@ static int qcom_geni_serial_resume(struct device *d= ev) static const struct qcom_geni_device_data qcom_geni_console_data =3D { .console =3D true, .mode =3D GENI_SE_FIFO, + .resources_init =3D geni_serial_resource_init, + .set_rate =3D geni_serial_set_rate, + .power_state =3D geni_serial_resource_state, }; =20 static const struct qcom_geni_device_data qcom_geni_uart_data =3D { .console =3D false, .mode =3D GENI_SE_DMA, + .resources_init =3D geni_serial_resource_init, + .set_rate =3D geni_serial_set_rate, + .power_state =3D geni_serial_resource_state, +}; + +static const struct qcom_geni_device_data sa8255p_qcom_geni_console_data = =3D { + .console =3D true, + .mode =3D GENI_SE_FIFO, + .pd_data =3D { + .pd_flags =3D PD_FLAG_DEV_LINK_ON, + .pd_names =3D (const char*[]) { "power", "perf" }, + .num_pd_names =3D 2, + }, + .resources_init =3D geni_serial_pwr_init, + .set_rate =3D geni_serial_set_level, +}; + +static const struct qcom_geni_device_data sa8255p_qcom_geni_uart_data =3D { + .console =3D false, + .mode =3D GENI_SE_DMA, + .pd_data =3D { + .pd_flags =3D PD_FLAG_DEV_LINK_ON, + .pd_names =3D (const char*[]) { "power", "perf" }, + .num_pd_names =3D 2, + }, + .resources_init =3D geni_serial_pwr_init, + .set_rate =3D geni_serial_set_level, }; =20 static const struct dev_pm_ops qcom_geni_serial_pm_ops =3D { @@ -1980,10 +2096,18 @@ static const struct of_device_id qcom_geni_serial_m= atch_table[] =3D { .compatible =3D "qcom,geni-debug-uart", .data =3D &qcom_geni_console_data, }, + { + .compatible =3D "qcom,sa8255p-geni-debug-uart", + .data =3D &sa8255p_qcom_geni_console_data, + }, { .compatible =3D "qcom,geni-uart", .data =3D &qcom_geni_uart_data, }, + { + .compatible =3D "qcom,sa8255p-geni-uart", + .data =3D &sa8255p_qcom_geni_uart_data, + }, {} }; MODULE_DEVICE_TABLE(of, qcom_geni_serial_match_table); --=20 2.17.1