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To: simona@ffwll.ch, deller@gmx.de Cc: linux-fbdev@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, dishank@siqol.com, "Darshan R." Subject: [PATCH] fbdev: svgalib: Clean up coding style Date: Mon, 21 Jul 2025 12:56:47 +0000 Message-ID: <20250721125648.27179-1-rathod.darshan.0896@gmail.com> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This patch addresses various coding style issues in `svgalib.c` to improve = readability and better align the code with the Linux kernel's formatting st= andards. The changes primarily consist of: - Adjusting whitespace around operators and after keywords. - Standardizing brace placement for control flow statements. - Removing unnecessary braces on single-statement if/else blocks. - Deleting extraneous blank lines throughout the file. These changes are purely stylistic and introduce no functional modification= s. Signed-off-by: Darshan R. --- drivers/video/fbdev/core/svgalib.c | 95 +++++++++++++----------------- 1 file changed, 42 insertions(+), 53 deletions(-) diff --git a/drivers/video/fbdev/core/svgalib.c b/drivers/video/fbdev/core/= svgalib.c index 821b89a0a645..5234ad109dfd 100644 --- a/drivers/video/fbdev/core/svgalib.c +++ b/drivers/video/fbdev/core/svgalib.c @@ -19,7 +19,6 @@ #include #include =20 - /* Write a CRT register value spread across multiple registers */ void svga_wcrt_multi(void __iomem *regbase, const struct vga_regset *regse= t, u32 value) { @@ -31,12 +30,13 @@ void svga_wcrt_multi(void __iomem *regbase, const struc= t vga_regset *regset, u32 while (bitnum <=3D regset->highbit) { bitval =3D 1 << bitnum; regval =3D regval & ~bitval; - if (value & 1) regval =3D regval | bitval; - bitnum ++; + if (value & 1) + regval =3D regval | bitval; + bitnum++; value =3D value >> 1; } vga_wcrt(regbase, regset->regnum, regval); - regset ++; + regset++; } } =20 @@ -51,12 +51,13 @@ void svga_wseq_multi(void __iomem *regbase, const struc= t vga_regset *regset, u32 while (bitnum <=3D regset->highbit) { bitval =3D 1 << bitnum; regval =3D regval & ~bitval; - if (value & 1) regval =3D regval | bitval; - bitnum ++; + if (value & 1) + regval =3D regval | bitval; + bitnum++; value =3D value >> 1; } vga_wseq(regbase, regset->regnum, regval); - regset ++; + regset++; } } =20 @@ -66,15 +67,13 @@ static unsigned int svga_regset_size(const struct vga_r= egset *regset) =20 while (regset->regnum !=3D VGA_REGSET_END_VAL) { count +=3D regset->highbit - regset->lowbit + 1; - regset ++; + regset++; } return 1 << count; } =20 - /* -----------------------------------------------------------------------= -- */ =20 - /* Set graphics controller registers to sane values */ void svga_set_default_gfx_regs(void __iomem *regbase) { @@ -102,7 +101,7 @@ void svga_set_default_atc_regs(void __iomem *regbase) vga_w(regbase, VGA_ATT_W, 0x00); =20 /* All standard ATC registers (AR00 - AR14) */ - for (count =3D 0; count <=3D 0xF; count ++) + for (count =3D 0; count <=3D 0xF; count++) svga_wattr(regbase, count, count); =20 svga_wattr(regbase, VGA_ATC_MODE, 0x01); @@ -187,10 +186,8 @@ void svga_dump_var(struct fb_var_screeninfo *var, int = node) } #endif /* 0 */ =20 - /* -----------------------------------------------------------------------= -- */ =20 - void svga_settile(struct fb_info *info, struct fb_tilemap *map) { const u8 *font =3D map->data; @@ -229,7 +226,7 @@ void svga_tilecopy(struct fb_info *info, struct fb_tile= area *area) ((area->sy =3D=3D area->dy) && (area->sx > area->dx))) { src =3D fb + area->sx * colstride + area->sy * rowstride; dst =3D fb + area->dx * colstride + area->dy * rowstride; - } else { + } else { src =3D fb + (area->sx + area->width - 1) * colstride + (area->sy + area->height - 1) * rowstride; dst =3D fb + (area->dx + area->width - 1) * colstride @@ -237,7 +234,7 @@ void svga_tilecopy(struct fb_info *info, struct fb_tile= area *area) =20 colstride =3D -colstride; rowstride =3D -rowstride; - } + } =20 for (dy =3D 0; dy < area->height; dy++) { u16 __iomem *src2 =3D src; @@ -284,19 +281,19 @@ void svga_tileblit(struct fb_info *info, struct fb_ti= leblit *blit) u8 __iomem *fb =3D (u8 __iomem *)info->screen_base; fb +=3D blit->sx * colstride + blit->sy * rowstride; =20 - i=3D0; - for (dy=3D0; dy < blit->height; dy ++) { + i =3D 0; + for (dy =3D 0; dy < blit->height; dy++) { u8 __iomem *fb2 =3D fb; - for (dx =3D 0; dx < blit->width; dx ++) { + for (dx =3D 0; dx < blit->width; dx++) { fb_writeb(blit->indices[i], fb2); fb_writeb(attr, fb2 + 1); fb2 +=3D colstride; - i ++; - if (i =3D=3D blit->length) return; + i++; + if (i =3D=3D blit->length) + return; } fb +=3D rowstride; } - } =20 /* Set cursor in text (tileblit) mode */ @@ -308,15 +305,15 @@ void svga_tilecursor(void __iomem *regbase, struct fb= _info *info, struct fb_tile + (cursor->sy + (info->var.yoffset / 16)) * (info->var.xres_virtual / 8); =20 - if (! cursor -> mode) + if (!cursor->mode) return; =20 svga_wcrt_mask(regbase, 0x0A, 0x20, 0x20); /* disable cursor */ =20 - if (cursor -> shape =3D=3D FB_TILE_CURSOR_NONE) + if (cursor->shape =3D=3D FB_TILE_CURSOR_NONE) return; =20 - switch (cursor -> shape) { + switch (cursor->shape) { case FB_TILE_CURSOR_UNDERLINE: cs =3D 0x0d; break; @@ -374,7 +371,6 @@ EXPORT_SYMBOL(svga_get_caps); =20 /* -----------------------------------------------------------------------= -- */ =20 - /* * Compute PLL settings (M, N, R) * F_VCO =3D (F_BASE * M) / N @@ -385,7 +381,7 @@ int svga_compute_pll(const struct svga_pll *pll, u32 f_= wanted, u16 *m, u16 *n, u u16 am, an, ar; u32 f_vco, f_current, delta_current, delta_best; =20 - pr_debug("fb%d: ideal frequency: %d kHz\n", node, (unsigned int) f_wanted= ); + pr_debug("fb%d: ideal frequency: %d kHz\n", node, (unsigned int)f_wanted); =20 ar =3D pll->r_max; f_vco =3D f_wanted << ar; @@ -416,7 +412,7 @@ int svga_compute_pll(const struct svga_pll *pll, u32 f_= wanted, u16 *m, u16 *n, u =20 while ((am <=3D pll->m_max) && (an <=3D pll->n_max)) { f_current =3D (pll->f_base * am) / an; - delta_current =3D abs_diff (f_current, f_vco); + delta_current =3D abs_diff(f_current, f_vco); =20 if (delta_current < delta_best) { delta_best =3D delta_current; @@ -424,58 +420,55 @@ int svga_compute_pll(const struct svga_pll *pll, u32 = f_wanted, u16 *m, u16 *n, u *n =3D an; } =20 - if (f_current <=3D f_vco) { - am ++; - } else { - an ++; - } + if (f_current <=3D f_vco) + am++; + else + an++; } =20 f_current =3D (pll->f_base * *m) / *n; - pr_debug("fb%d: found frequency: %d kHz (VCO %d kHz)\n", node, (int) (f_c= urrent >> ar), (int) f_current); - pr_debug("fb%d: m =3D %d n =3D %d r =3D %d\n", node, (unsigned int) *m, (= unsigned int) *n, (unsigned int) *r); + pr_debug("fb%d: found frequency: %d kHz (VCO %d kHz)\n", node, (int)(f_cu= rrent >> ar), (int)f_current); + pr_debug("fb%d: m =3D %d n =3D %d r =3D %d\n", node, (unsigned int)*m, (u= nsigned int)*n, (unsigned int)*r); return 0; } =20 - /* -----------------------------------------------------------------------= -- */ =20 - /* Check CRT timing values */ int svga_check_timings(const struct svga_timing_regs *tm, struct fb_var_sc= reeninfo *var, int node) { u32 value; =20 - var->xres =3D (var->xres+7)&~7; - var->left_margin =3D (var->left_margin+7)&~7; - var->right_margin =3D (var->right_margin+7)&~7; - var->hsync_len =3D (var->hsync_len+7)&~7; + var->xres =3D (var->xres + 7) & ~7; + var->left_margin =3D (var->left_margin + 7) & ~7; + var->right_margin =3D (var->right_margin + 7) & ~7; + var->hsync_len =3D (var->hsync_len + 7) & ~7; =20 /* Check horizontal total */ value =3D var->xres + var->left_margin + var->right_margin + var->hsync_l= en; - if (((value / 8) - 5) >=3D svga_regset_size (tm->h_total_regs)) + if (((value / 8) - 5) >=3D svga_regset_size(tm->h_total_regs)) return -EINVAL; =20 /* Check horizontal display and blank start */ value =3D var->xres; - if (((value / 8) - 1) >=3D svga_regset_size (tm->h_display_regs)) + if (((value / 8) - 1) >=3D svga_regset_size(tm->h_display_regs)) return -EINVAL; - if (((value / 8) - 1) >=3D svga_regset_size (tm->h_blank_start_regs)) + if (((value / 8) - 1) >=3D svga_regset_size(tm->h_blank_start_regs)) return -EINVAL; =20 /* Check horizontal sync start */ value =3D var->xres + var->right_margin; - if (((value / 8) - 1) >=3D svga_regset_size (tm->h_sync_start_regs)) + if (((value / 8) - 1) >=3D svga_regset_size(tm->h_sync_start_regs)) return -EINVAL; =20 /* Check horizontal blank end (or length) */ value =3D var->left_margin + var->right_margin + var->hsync_len; - if ((value =3D=3D 0) || ((value / 8) >=3D svga_regset_size (tm->h_blank_e= nd_regs))) + if ((value =3D=3D 0) || ((value / 8) >=3D svga_regset_size(tm->h_blank_en= d_regs))) return -EINVAL; =20 /* Check horizontal sync end (or length) */ value =3D var->hsync_len; - if ((value =3D=3D 0) || ((value / 8) >=3D svga_regset_size (tm->h_sync_en= d_regs))) + if ((value =3D=3D 0) || ((value / 8) >=3D svga_regset_size(tm->h_sync_end= _regs))) return -EINVAL; =20 /* Check vertical total */ @@ -497,12 +490,12 @@ int svga_check_timings(const struct svga_timing_regs = *tm, struct fb_var_screenin =20 /* Check vertical blank end (or length) */ value =3D var->upper_margin + var->lower_margin + var->vsync_len; - if ((value =3D=3D 0) || (value >=3D svga_regset_size (tm->v_blank_end_reg= s))) + if ((value =3D=3D 0) || (value >=3D svga_regset_size(tm->v_blank_end_regs= ))) return -EINVAL; =20 /* Check vertical sync end (or length) */ value =3D var->vsync_len; - if ((value =3D=3D 0) || (value >=3D svga_regset_size (tm->v_sync_end_regs= ))) + if ((value =3D=3D 0) || (value >=3D svga_regset_size(tm->v_sync_end_regs)= )) return -EINVAL; =20 return 0; @@ -596,18 +589,15 @@ void svga_set_timings(void __iomem *regbase, const st= ruct svga_timing_regs *tm, vga_w(regbase, VGA_MIS_W, regval); } =20 - /* -----------------------------------------------------------------------= -- */ =20 - static inline int match_format(const struct svga_fb_format *frm, struct fb_var_screeninfo *var) { int i =3D 0; int stored =3D -EINVAL; =20 - while (frm->bits_per_pixel !=3D SVGA_FORMAT_END_VAL) - { + while (frm->bits_per_pixel !=3D SVGA_FORMAT_END_VAL) { if ((var->bits_per_pixel =3D=3D frm->bits_per_pixel) && (var->red.length <=3D frm->red.length) && (var->green.length <=3D frm->green.length) && @@ -647,7 +637,6 @@ int svga_match_format(const struct svga_fb_format *frm, return i; } =20 - EXPORT_SYMBOL(svga_wcrt_multi); EXPORT_SYMBOL(svga_wseq_multi); =20 --=20 2.43.0